WO2013002338A1 - 半導体装置ならびに半導体装置の製造方法 - Google Patents

半導体装置ならびに半導体装置の製造方法 Download PDF

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WO2013002338A1
WO2013002338A1 PCT/JP2012/066571 JP2012066571W WO2013002338A1 WO 2013002338 A1 WO2013002338 A1 WO 2013002338A1 JP 2012066571 W JP2012066571 W JP 2012066571W WO 2013002338 A1 WO2013002338 A1 WO 2013002338A1
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Prior art keywords
electrode surface
solder
electrode
conductor member
spreading
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PCT/JP2012/066571
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English (en)
French (fr)
Inventor
伸一 藤野
吉成　英人
山下　志郎
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日立オートモティブシステムズ株式会社
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Application filed by 日立オートモティブシステムズ株式会社 filed Critical 日立オートモティブシステムズ株式会社
Priority to EP12804282.7A priority Critical patent/EP2728615A4/en
Priority to CN201280031864.9A priority patent/CN103688352B/zh
Priority to US14/123,909 priority patent/US9306020B2/en
Publication of WO2013002338A1 publication Critical patent/WO2013002338A1/ja

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Definitions

  • the present invention relates to a semiconductor device having a configuration in which both surfaces of a semiconductor element are joined to a conductor member by solder.
  • a power semiconductor element such as an IGBT chip is used in a semiconductor device mounted on a hybrid electric vehicle or a power conversion device of a pure electric vehicle.
  • the IGBT chip has a structure in which thousands to tens of thousands of IGBT cells or thousands to tens of thousands are repeatedly arranged.
  • the IGBT chip is a three-terminal device composed of an emitter electrode, a collector electrode, and a gate electrode. Structurally, the emitter electrode and the gate electrode are formed in an insulated state on the same plane of the IGBT chip.
  • the gate electrode is connected to a gate wiring made of a material having high conductivity such as aluminum in order to reduce the variation in the transmission delay time of the control signal.
  • This gate wiring is connected to the gate of the IGBT cell via a polysilicon wiring or the like. Connected to.
  • the emitter electrode of an IGBT chip is generally divided into a plurality of regions by this gate wiring (see Patent Document 1).
  • the divided emitter electrode may be connected to the conductor member by solder.
  • an emitter electrode is divided into a plurality of parts by an aluminum gate wiring having a smaller electric resistance than a polysilicon wiring.
  • the aluminum gate wiring is covered with a protective film having insulation properties such as polyimide resin having low wettability with solder.
  • the spread of the solder on the emitter electrode surface of the IGBT chip is limited by the protective film, and the void ratio increases due to uneven flow of the solder. There was a problem. Further, since the spreading direction of the solder is limited to a predetermined direction, there is a possibility that the solder flows excessively in that direction, and a solder flow that flows beyond the emitter electrode surface of the IGBT chip may occur.
  • a semiconductor device includes a semiconductor element having at least one electrode surface on each of both surfaces, a first conductor member bonded to an electrode surface provided on one surface of the semiconductor element by solder, And a second conductor member joined by solder to an electrode surface provided on the other surface of the semiconductor element, and at least one of the electrode surfaces provided on the one surface of the semiconductor element has a comb-like shape.
  • the two comb-shaped electrode surfaces extend in a comb shape on both sides of the main solder spreading electrode surface and the main solder spreading electrode surface. It preferably has a secondary solder spreading electrode surface.
  • the gate wiring is disposed at the periphery of the both comb-shaped electrode surfaces, and the gate wiring is compared to the both comb-shaped electrode surfaces. It is preferable that the solder has low wettability and is covered with an insulating protective film.
  • the first conductor member and the second conductor member are made of a copper material, and the first conductor member and the second conductor member are It is preferable that surface treatment is not performed on the joint surface with the solder.
  • the semiconductor device includes an IGBT chip and a diode chip, at least one emitter electrode surface provided on one surface of the IGBT chip, and an anode electrode surface provided on one surface of the diode chip by soldering.
  • At least one of the emitter electrode surfaces provided on one surface of the electrode has a comb-like shape, and the both comb-like electrode surfaces have a main solder spreading electrode surface and a comb shape on both sides from the main solder spreading electrode surface.
  • a semiconductor device includes an upper arm IGBT chip, an upper arm diode chip, a lower arm IGBT chip, a lower arm diode chip, and an upper arm IGBT chip that constitute upper and lower arms of an inverter circuit.
  • a second AC electrode lead frame joined by solder to an emitter electrode surface provided on at least one surface of the electrode and an anode electrode surface provided on one surface of the upper arm diode chip, and the other of the IGBT chip for the upper arm At least one DC positive electrode lead frame joined by solder to the collector electrode surface provided on the surface and the cathode electrode surface provided on the other surface of the upper arm diode chip, and one surface of the lower arm IGBT chip Emitter electrode surface provided and lower arm die
  • a DC negative electrode lead frame joined to the anode electrode surface provided on one surface of the diode chip by solder, a collector electrode surface provided on the other surface of the lower arm IGBT chip, and the other surface of the lower arm diode chip A first AC electrode lead frame joined to the cathode electrode surface by solder, and at least one of the emitter electrode surfaces provided on one surface of each of the upper arm IGBT chip and the lower arm IGBT chip is both
  • the comb-like electrode surface has a main solder spreading electrode surface
  • a gate wiring is disposed on the periphery of the gate electrode, and the gate wiring is formed by a protective film having low solder wettability and insulating properties compared to the emitter electrode surface. It is covered Te.
  • both comb-teeth electrode surfaces are subjected to nickel plating for improving solder wettability. Is preferred.
  • a method of manufacturing a semiconductor device according to an eighth aspect of the present invention is a method of manufacturing the semiconductor device according to any one of the second to fourth aspects, and includes a semiconductor element having at least one of both comb-like electrode surfaces.
  • a step of preparing a first conductor member and a second conductor member a step of joining an electrode surface provided on the other surface of the semiconductor element to the second conductor member by solder, and a comb-like shape of the semiconductor element Dripping molten solder into a predetermined region including a part of the main solder spreading electrode surface constituting the electrode surface of the first electrode, or a region facing the predetermined region of the first conductor member, and the first conductor member and the semiconductor element
  • the solder surface is spread from the main solder spreading electrode surface to the sub solder spreading electrode surface by reducing the distance from the electrode surface provided on one surface of the electrode, and the electrode surface provided on one surface of the semiconductor element by the solder To the first conductor member
  • a method for manufacturing a semiconductor device is a method for manufacturing the semiconductor device according to any one of the second to fourth aspects, wherein the semiconductor element has at least one of both comb-like electrode surfaces. And a step of preparing a first conductor member and a second conductor member, a step of joining an electrode surface provided on the other surface of the semiconductor element to the second conductor member by solder, and a dropping region of the first conductor member A step including dripping molten solder on the surface and a part of the main solder spreading electrode surface that constitutes the comb-shaped electrode surface on which the solder dripped onto the dripping region is provided on one surface of the semiconductor element Positioning so as to be opposed to the region, bringing one surface of the semiconductor element close to the first conductor member, spreading the molten solder from the main solder spreading electrode surface to the sub solder spreading electrode surface, Soldered on one side of the semiconductor element with solder
  • a method for manufacturing a semiconductor device according to a tenth aspect of the present invention is a method for manufacturing the semiconductor device according to the fifth aspect, comprising: an IGBT chip having at least one comb-like emitter electrode surface; a diode chip; , A step of preparing the first conductor plate and the second conductor plate, and a central position of the collector electrode surface of the IGBT chip and a cathode electrode surface of the diode chip, or a second conductor plate facing the respective central positions A step of dropping molten solder at a predetermined position of the first electrode, and simultaneously bringing the collector electrode surface of the IGBT chip and the cathode electrode surface of the diode chip close to the second conductor plate so that the molten solder is spread over the collector electrode surface and the cathode electrode surface.
  • each of the collector electrode surface of the IGBT chip and the cathode electrode surface of the diode chip is soldered to the second conductor plate with solder.
  • the molten solder is spread to the anode electrode surface, and the first conductor is connected to the emitter electrode surface of the IGBT chip and the anode electrode surface of the diode chip by the solder.
  • a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device according to any one of the second to fourth aspects, wherein the semiconductor element has at least one of both comb-like electrode surfaces.
  • a step of preparing a first conductor member and a second conductor member, a step of joining an electrode surface provided on the other surface of the semiconductor element to the second conductor member by solder, and a comb-like shape of the semiconductor element A step of installing solder in a predetermined region including a part of the main solder spreading electrode surface constituting the electrode surface of the electrode, or a region facing the predetermined region of the first conductor member, and heating and melting the solder, By bringing the distance between the conductor member and the electrode surface provided on one surface of the semiconductor element closer to each other, the molten solder is spread from the main solder spreading electrode surface to the sub solder spreading electrode surface, and by soldering, one surface of the semiconductor element Electrode surface And a step of joining the first conductive member, and
  • FIG. 7A is a schematic cross-sectional view of a power semiconductor unit cut along a line BB in FIG. 6, and FIG. FIG. 7 is a schematic cross-sectional view of a power semiconductor unit cut along line CC in FIG. 6. Process drawing which shows the manufacturing method of a power semiconductor unit.
  • the schematic diagram which shows the setting position of solder and the spreading direction of solder The schematic diagram which shows a mode that the solder of a molten state spreads in the emitter electrode surface of an IGBT chip
  • FIG. 1 is a perspective view showing an external appearance of the power module 300
  • FIG. 2 is a schematic sectional view of the power module 300.
  • the power module 300 includes a power semiconductor unit 330 (see FIG. 2) that includes a switching element and is transfer-molded in a metal module case 310.
  • the power module 300 is used, for example, in a power conversion device mounted on an electric vehicle such as a pure electric vehicle or a hybrid electric vehicle.
  • the module case 310 has a pair of heat radiating plates in which a plurality of heat radiating fins 305 are erected.
  • the heat sink is formed of a metal such as aluminum having a high thermal conductivity.
  • one heat radiating plate located on the left side in the drawing is provided with a thick portion 303 in which a plurality of heat radiating fins 305 are erected and a thin portion 302 provided in the periphery thereof. Yes.
  • the thin portion 302 By plastically deforming the thin portion 302, the heat radiation surface of the power semiconductor unit 330 housed inside and the inner peripheral surface of the thick portion 303 are brought into close contact with each other. As shown in FIG.
  • FIG. 3 is an exploded perspective view of the power semiconductor unit 330
  • FIG. 4 is a circuit diagram of the power semiconductor unit 330.
  • the transfer mold is not shown.
  • IGBT (insulated gate bipolar transistor) chips 155 and 157 and diode chips 156 and 158 are provided as power semiconductor elements.
  • two IGBT chips 155 and 157 and two diode chips 156 and 158 are provided in parallel.
  • a DC positive electrode lead frame 315 and a first AC electrode lead frame 316 are arranged on one side with a power semiconductor element sandwiched therebetween, and the second side is arranged on the other side.
  • the AC electrode lead frame 318 and the DC negative electrode lead frame 319 are arranged in substantially the same plane.
  • Each power semiconductor element has a flat plate-like structure, and each electrode is formed on the front and back surfaces.
  • a collector electrode of the upper arm IGBT chip 155 and a cathode electrode of the upper arm diode chip 156 are fixed to the element fixing portion 322 of the DC positive electrode lead frame 315 by solder 160.
  • the collector electrode of the IGBT chip 157 for the lower arm and the cathode electrode of the diode chip 158 for the lower arm are fixed to the element fixing portion 322 of the first AC electrode lead frame 316 by the solder 160.
  • the emitter electrode of the upper arm IGBT chip 155 and the anode electrode of the upper arm diode chip 156 are fixed to the element fixing portion 322 of the second AC electrode lead frame 318 by solder 160.
  • the emitter electrode of the lower arm IGBT chip 157 and the anode electrode of the lower arm diode chip 158 are fixed to the element fixing portion 322 of the DC negative electrode lead frame 319 by solder 160.
  • the DC positive electrode lead frame 315 and the second AC electrode lead frame 318 face each other substantially in parallel with the IGBT chip 155 and the diode chip 156 interposed therebetween.
  • the first AC electrode lead frame 316 and the DC negative electrode lead frame 319 are opposed substantially in parallel with each IGBT chip 157 and the diode chip 158 interposed therebetween.
  • the first AC electrode lead frame 316 and the second AC electrode lead frame 318 are connected via an intermediate electrode 159. By connecting with the intermediate electrode 159, the upper arm circuit and the lower arm circuit are electrically connected to form an upper and lower arm series circuit as shown in FIG.
  • the DC positive electrode wiring 315A is integrally formed with the DC positive electrode lead frame 315, and the DC positive electrode terminal 315B is formed at the tip of the DC positive electrode wiring 315A.
  • the DC negative electrode wiring 319A is integrally formed with the DC negative electrode lead frame 319, and a DC negative electrode terminal 319B is formed at the tip of the DC negative electrode wiring 319A.
  • An AC wiring 320 is formed integrally with the first AC electrode lead frame 316, and an AC terminal 321 is formed at the tip of the AC wiring 320.
  • thermoplastic resin terminal block 600 is provided between the DC positive electrode wiring 315A and the DC negative electrode wiring 319A. As shown in FIG. 1, the DC positive electrode wiring 315A and the DC negative electrode wiring 319A extend so as to protrude from the module case 310 in a state of facing each other substantially in parallel.
  • the signal terminals 325L, 325U, 326L, and 326U are integrally formed with the thermoplastic resin terminal block 600, and extend so as to protrude from the module case 310 in the same direction as the DC positive electrode wiring 315A and the DC negative electrode wiring 319A. ing. Therefore, insulation between the DC positive electrode wiring 315A and the DC negative electrode wiring 319A and insulation between the signal wiring and each wiring board can be ensured, and high-density wiring is possible.
  • thermoplastic resin terminal block 600 As a resin material used for the thermoplastic resin terminal block 600, a thermoplastic resin having a heat resistance higher than the temperature of the mold of the transfer mold (for example, 180 ° C. or higher) and an insulating property is suitable.
  • a thermoplastic resin having a heat resistance higher than the temperature of the mold of the transfer mold (for example, 180 ° C. or higher) and an insulating property is suitable.
  • Polyphenylene sulfide (PPS) ) Or liquid crystal polymer (LCP).
  • FIG. 5 is a schematic sectional view of the power semiconductor unit 330.
  • 6 is a schematic diagram showing the electrode surface 11a of the emitter electrode 11 of the IGBT chip 1 and the electrode surface 21a of the anode electrode 21 of the diode chip 2, and is a cross-sectional view taken along the line AA of FIG.
  • the sealing member 20 and the solders 5 and 7 are not shown.
  • the direction in which the IGBT chips 1 and the diode chips 2 are arranged in a row is defined as the y direction
  • the direction orthogonal to the y direction is defined as the x direction.
  • Components for upper arm such as IGBT chip for upper arm, diode chip for upper arm and various wirings for upper arm, and lower arm IGBT chip, diode chip for lower arm and various wiring for lower arm Since the structural members have substantially the same configuration, the structural members for the upper arm or the lower arm are defined and described as follows.
  • the upper arm IGBT chip 155 and the lower arm IGBT chip 157 are simply referred to as the IGBT chip 1, and the upper arm diode chip 156 and the lower arm diode chip 158 are simply referred to as the diode chip 2.
  • the second AC electrode lead frame 318 and the DC negative electrode lead frame 319 are simply referred to as the first bus bar 3, and the DC positive electrode lead frame 315 and the first AC electrode lead frame 316 are simply referred to as the second bus bar 4.
  • the signal lines including the signal terminals 325U, 325L, 326L, and 326U are referred to as gate pins 9, respectively.
  • the IGBT chip 1 is provided with the electrode surface 11a of the emitter electrode 11 and the terminal electrode 13, that is, the emitter terminal electrode 13a and the gate terminal electrode 13b on one surface, and the other surface.
  • the electrode surface 12a of the collector electrode 12 is provided on the surface.
  • a drive signal from a driver circuit (not shown) connected to the power module is input to the gate terminal electrode 13b. From the emitter terminal electrode 13a, information on the current flowing through the emitter electrode 11 of the IGBT chip 1 is output to a driver circuit (not shown).
  • the IGBT chip 1 according to the present embodiment has a size of about 10 mm ⁇ 10 mm.
  • the electrode surface 11 a of the emitter electrode 11 is joined to the first bus bar 3 by solder 5.
  • the electrode surface 12 a of the collector electrode 12 is joined to the second bus bar 4 by solder 6.
  • Each of the emitter terminal electrode 13 a and the gate terminal electrode 13 b is joined to the gate pin 9 with an aluminum wire 10.
  • the diode chip 2 is provided with the electrode surface 21a of the anode electrode 21 on one surface and the electrode surface 22a of the cathode electrode 22 on the other surface.
  • the electrode surface 21a of the anode electrode 21 is joined by the solder 7 on the same surface as the surface to which the IGBT chip 1 of the first bus bar 3 is joined.
  • the electrode surface 22a of the cathode electrode 22 is joined by the solder 8 on the same surface as the surface to which the IGBT chip 1 of the second bus bar 4 is joined.
  • Each of the emitter electrode surface 11a, the anode electrode surface 21a, the collector electrode surface 12a, and the cathode electrode surface 22a is subjected to surface processing such as nickel plating, to which solder can be joined.
  • the first bus bar 3 and the second bus bar 4 are made of a copper material, and the surface of the first bus bar 3 and the second bus bar 4 with the solder is not subjected to surface processing such as plating, and the surface is made of a copper material. Innocent.
  • the aluminum wire 10 that connects the IGBT chip 1 and the diode chip 2 sandwiched between the first bus bar 3 and the second bus bar 4 and the IGBT chip 1 and the gate pin 9 is made of epoxy resin or the like. It is sealed by a sealing member 20 made of an insulating organic material having insulating properties. The opposite side of the connecting portion of the gate pin 9 to the aluminum wire 10 protrudes to the outside of the sealing member 20 and is used for an external interface of the drive signal.
  • the surface of the first bus bar 3 (318, 319) and the second bus bar 4 (315, 316) to which the IGBT chip 1 (155, 157) and the diode chip 2 (156, 158) are connected The opposite surface is exposed without being sealed with resin.
  • This exposed surface is in contact with the inner surface of the module case 310 via an insulating sheet 333 or the like. Therefore, the heat generated from the IGBT chip 1 and the diode chip 2 is generated by the heat radiation fins 305 and the module of the module case 310 via the first bus bar 3 (318, 319), the second bus bar 4 (315, 316) and the insulating sheet 333.
  • the heat is transmitted to the surface of the case 310 and is radiated by the refrigerant (not shown) in contact with the heat radiation fins 305 and the surface of the module case 310.
  • the electrode surface 11a of the emitter electrode 11 has a comb-teeth shape in which four pairs of band-like electrode surfaces protrude in the + y direction and the -y direction from the electrode surface extending in the x direction in plan view.
  • the electrode surface 11a of the emitter electrode 11 has a main solder spreading electrode surface 11a1 extending in the x direction at the center as shown in the figure, and + y that is on both sides of the main solder spreading electrode surface 11a1.
  • a secondary solder spreading electrode surface 11a2 extending in a comb shape in the direction and -y direction.
  • the shape of the electrode surface 21a of the anode electrode 21 of the diode chip 2 is rectangular in plan view as shown in the figure. Although not shown, the electrode surface 12a of the collector electrode 12 of the IGBT chip 1 and the cathode electrode 22 of the diode chip 2 are not shown. The shape of the electrode surface 22a is also rectangular in plan view.
  • FIG. 7A is a schematic cross-sectional view of the power semiconductor unit 330 cut along the line BB in FIG. 6, and FIG. 7B is an enlarged view of a portion D in FIG. 7A.
  • FIG. 8 is a schematic cross-sectional view of the power semiconductor unit 330 cut along line CC in FIG. 7 and 8, the sealing member 20 is omitted.
  • FIG. 6 and FIG. 7 in order to connect the gate (not shown) of each IGBT cell and the gate terminal electrode 13b between adjacent strip electrode surfaces constituting the sub solder spreading electrode surface 11a2.
  • Aluminum gate wiring 15 is provided.
  • the aluminum gate wiring 15 and the gate of each IGBT cell are connected through, for example, a polysilicon wiring.
  • the electrical resistance value of the polysilicon wiring is about several tens to several hundred times higher than the electrical resistance value of the aluminum gate wiring 15. Therefore, if the polysilicon wiring becomes longer, the electrical resistance to each IGBT cell increases, and the responsiveness of each IGBT cell deteriorates.
  • the aluminum gate wiring 15 is disposed on the periphery of the emitter electrode surface 11a including between adjacent strip electrode surfaces constituting the sub solder spreading electrode surface 11a2, thereby shortening the polysilicon wiring. Yes.
  • the aluminum gate wiring 15 is covered with a protective film 14 having an insulating property.
  • a protective film is applied to the entire surface of the IGBT chip 1 including each electrode surface, and after drying, the protective film on the electrode surface is removed by an etching process, so that an aluminum gate wiring 15 is formed as shown in FIGS.
  • a protective film 14 is formed on the chip electrode surface.
  • an insulating protective film 24 is formed on the periphery of the electrode surface 21 a of the anode electrode 21 of the diode chip 2.
  • the protective films 14 and 24 polyimide resin, polyamide resin, or the like can be used.
  • the protective film 14 has lower solder wettability than the emitter electrode surface 11 a of the IGBT chip 1. Therefore, as shown in FIG. 7B, the solder 5 does not spread on the protective film 14 formed between the adjacent strip electrode surfaces constituting the sub solder spreading electrode surface 11a2 of the IGBT chip 1. A non-wetting space 16 in which the solder 5 does not exist is formed. The unwetted space 16 may penetrate to the first bus bar 3 as indicated by a broken line X in FIG.
  • the protective film 14 does not exist in the CC cross section of FIG. 6, and the non-wetting space 16 does not exist except for solder defects (not shown) such as voids (fine cavities).
  • solder defects not shown
  • voids fine cavities
  • FIG. 9 is a process diagram showing a method of manufacturing the power semiconductor unit 330
  • FIG. 10 is a schematic diagram showing the setting positions of the solders 5a and 7a and the spreading directions of the solders 5a and 7a.
  • the IGBT chip 1 and the diode chip 2, the first bus bar 3, and the second bus bar 4 are prepared.
  • the molten solder is applied to the solder dripping region on the surface of the second bus bar 4.
  • 6a and solder 8a are dropped.
  • the solder dripping region on the surface of the second bus bar 4 is a region facing the center position of the collector electrode surface 12 a of the IGBT chip 1 and a region facing the center position of the cathode electrode surface 22 a of the diode chip 2.
  • the solder 6a is dropped on the solder dripping region of the second bus bar 4 facing the central position of the collector electrode surface 12a of the IGBT chip 1.
  • the solder 8a is dropped on the solder dripping region of the second bus bar 4 facing the central position of the cathode electrode surface 22a of the diode chip 2.
  • the molten solder 6 a is disposed to face the central position of the collector electrode surface 12 a of the IGBT chip 1, and the molten solder 8 a is the cathode of the diode chip 2.
  • the IGBT chip 1 and the diode chip 2 are positioned on the chip mounting surface of the second bus bar 4 so as to face the center position of the electrode surface 22a.
  • the collector electrode surface 12a of the IGBT chip 1 and the cathode electrode surface 22a of the diode chip 2 are simultaneously pressed against the second bus bar 4 against the molten solder 6a and the solder 8a, and the molten solder 6a is applied to the collector electrode surface.
  • the molten solder 8a is spread on the cathode electrode surface 22a.
  • the collector electrode surface 12 a of the IGBT chip 1 and the cathode electrode surface 22 a of the diode chip 2 are collectively bonded to the second bus bar 4 by the solders 6 and 8.
  • the collector electrode surface 12a of the IGBT chip 1 and the cathode electrode surface 22a of the diode chip 2 are rectangular in plan view. Therefore, the molten solders 6a and 8a installed at the center of each electrode surface flow evenly (radially) outward and spread over the entire electrode surface.
  • molten solder 5 a and solder 7 a are dropped onto the dropping area on the surface of the first bus bar 3.
  • the dripping region on the surface of the first bus bar 3 is a region facing the solder setting region 50 (see FIG. 10) located at the center of the emitter electrode surface 11a of the IGBT chip 1 and the center of the anode electrode surface 21a of the diode chip 2. This is a region facing the solder setting region 70 (see FIG. 10) located in the region.
  • the solder 5a is dropped on the dropping area of the first bus bar 3 facing the solder setting area 50
  • the solder 7a is dropped on the dropping area of the first bus bar 3 facing the solder setting area 70a.
  • the solder setting area 50 is set so as to include a part of the main solder spreading electrode surface 11a1 constituting the emitter electrode surface 11a of the IGBT chip 1.
  • the molten solder 5a is disposed to face the solder setting area 50 (see FIG. 10)
  • the molten solder 7a is disposed to face the solder setting area 70 (see FIG. 10).
  • the second bus bar set 30 shown in FIG. 9C is turned over, and the IGBT chip 1 and the diode chip 2 are positioned on the chip mounting surface of the first bus bar 3.
  • the emitter electrode surface 11a of the IGBT chip 1 and the anode electrode surface 21a of the diode chip 2 of the second bus bar assembly 30 turned upside down are simultaneously pressed against the molten solders 5a and 7a on the first bus bar 3.
  • the molten solder 5a is removed from the solder setting region 50 of the emitter electrode surface 11a as schematically shown by the arrows in FIG.
  • the solder 7a in a molten state spreads outward (radially) from the solder setting region 70 of the anode electrode surface 21a outward (radially).
  • the anode electrode surface 21a of the diode chip 2 is rectangular in plan view. Therefore, the molten solder 7a uniformly flows outward (radially) from the solder setting region 70 at the center of the anode electrode surface 21a and spreads over the entire anode electrode surface 21a.
  • FIG. 11 is a schematic diagram showing how the molten solder 5 a spreads on the emitter electrode surface 11 a of the IGBT chip 1.
  • the solder 5a When the emitter electrode surface 11a is pressed against the molten solder 5a, as shown in FIGS. 11A to 11C, the solder 5a extends in the + x direction and the ⁇ x direction from the center of the main solder spreading electrode surface 11a1. Flowing. The solder 5a advances from the main solder spreading electrode surface 11a1 to the sub solder spreading electrode surface 11a2, and flows toward the tip of the sub solder spreading electrode surface 11a2, that is, in the + y direction and the ⁇ y direction. At this time, the molten solder 5a does not spread in the direction across the protective film 14.
  • the solder wettability of the protective film 14 provided around the two comb-like emitter electrode surfaces 11a including between the strip-shaped electrode surfaces constituting the sub-solder spreading electrode surface 11a2 is determined by the emitter electrode. This is because it is lower than the surface 11a. In other words, the wettability of the emitter electrode surface 11a to the solder is superior to the wettability of the protective film 14 to the solder.
  • the molten solder 5a extends from the main solder spreading electrode surface 11a1 to the sub solder spreading electrode surface 11a2 along the comb-shaped emitter electrodes 11. It spreads (see FIG. 11A and FIG. 11B), and finally spreads over the entire emitter electrode surface 11a (see FIG. 11C).
  • solder 5a can be spread evenly on the emitter electrode surface 11a, the suppression of the protrusion of the solder 5a and the effect of reducing voids can be expected.
  • the first bus bar 3 is joined to the emitter electrode surface 11a of the IGBT chip 1 by the solder 5, as shown in FIG.
  • the first bus bar 3 is joined to the anode electrode surface 21 a of the diode chip 2 by the solder 7.
  • each electrode surface of the terminal electrode 13 (13a, 13b) of the IGBT chip 1 and the gate pin 9 are electrically connected by an aluminum wire 10, and the first bus bar 3 and the sealing member 20 are used.
  • the power semiconductor unit 330 is completed by sealing each member including the second bus bar 4 (see FIG. 5).
  • FIG. 12 is a schematic diagram showing how the molten solder 105a spreads on the emitter electrode surface 111a of the conventional IGBT chip 101.
  • the conventional IGBT chip 101 has a plurality of strip-shaped emitter electrode surfaces 111a. It should be noted that the wettability of the protective film 114 interposed between the adjacent band-shaped emitter electrode surfaces 111a with respect to the solder 105a is lower than the wettability of the emitter electrode surface 111a with respect to the solder 105a.
  • the spread of the molten solder 105a is restricted by the protective film 114 as shown in FIG.
  • the spreading direction of the solder 105a on 111a is mainly the y direction. Therefore, as shown in FIG. 12B, the solder 105a flows excessively in the y direction.
  • the solder 105a does not spread over the entire emitter electrode surface 111a, and a solder non-wetting area 105b where the solder 105a does not exist on the emitter electrode surface 111a is formed. In some cases, the solder flow 105c flows over the emitter electrode surface 111a.
  • Japanese Patent Application Laid-Open No. 2006-210519 describes a technique for improving the bondability with solder by providing a metal foil on a polyimide film (insulating protective film). According to this prior art, the solder can be spread evenly on the chip.
  • this conventional technique is expensive due to the provision of a metal foil on the polyimide film, and furthermore, a new bonding site between the metal foil and the solder and the metal foil and the polyimide film is generated, so that the life of the bonded portion is reduced. Concerned.
  • the emitter electrode surface 11a has a comb-teeth shape in which the sub solder spreading electrode surface 11a2 extends in a comb shape from both sides of the main solder spreading electrode surface 11a1.
  • a protective film 14 having low solder wettability is formed on the periphery of the emitter electrode surface 11 a so as to cover the aluminum gate wiring 15.
  • the molten solder 5a disposed in the central portion of the emitter electrode surface 11a flows radially by being sandwiched between the emitter electrode surface 11a and the first bus bar 3, and on the main solder spreading electrode surface 11a1 and the sub solder spreading electrode surface 11a2. While flowing evenly, the solder flow beyond the emitter electrode surface 11a can be prevented.
  • the voids can be reduced by discharging the voids to the electrode outer peripheral side.
  • the solder wettability of the bus bar affects the joining of the semiconductor element and the solder. If the solder wettability of the bus bar is too good, the solder spreads mainly on the bus bar side and hardly spreads on the semiconductor element side. On the contrary, if the solder wettability of the bus bar is poor, the solder is difficult to spread on the bus bar side and spreads too much on the semiconductor element side.
  • the first bus bar 3 and the second bus bar 4 are made of a copper material, and surface processing such as plating is not performed on the joint surface with the solder. For this reason, when joining solder, for example, by changing the temperature of the bus bar by heating the bus bar or the like, it becomes possible to adjust the wettability of the bus bar with the solder. It is possible to improve the bondability.
  • the IGBT chip 1 and the diode chip 2 are collectively bonded to the first bus bar 3, and the IGBT chip 1 and the diode chip 2 are collectively bonded to the second bus bar 4.
  • both the comb-like emitter electrode surfaces 11a are plated with nickel, the wettability of solder can be improved.
  • the IGBT chip 201 may be provided with a plurality of both comb-like electrode surfaces 211a and 211b.
  • the IGBT chip 201 shown in FIG. 13A electrode surfaces 211a and 211b divided into two in the x direction are provided, and one electrode surface 211a has a main solder spreading electrode surface 211a1 extending in the x direction.
  • sub-solder spreading electrode surface 211a2 extending in a comb shape in the + y direction and the -y direction on both sides from the spreading electrode surface 211a1.
  • the other electrode surface 211b has a main solder spreading electrode surface 211b1 extending in the x direction, and a sub solder spreading extending in a comb shape in the + y direction and the ⁇ y direction on both sides from the main solder spreading electrode surface 211b1. It has an electrode surface 211b2.
  • the solder setting area 250 is set substantially at the center of the IGBT chip 201 so as to include a part of the main solder spreading electrode surfaces 211a1 and 211b1 as shown.
  • the molten solder set on one electrode surface 211a is + x along the shape of the electrode surface 211a, that is, from the main solder spreading electrode surface 211a1 to the sub solder spreading electrode surface 211a2 when the bus bar is pressed. Flows in the direction, + y direction and -y direction and spreads over the entire electrode surface 211a.
  • the bus bar when the bus bar is pressed against the molten solder set on the other electrode surface 211b, it follows the shape of the electrode surface 211b, that is, from the main solder spreading electrode surface 211b1 to the sub solder spreading electrode surface 211b2. Thus, it flows in the ⁇ x direction, the + y direction, and the ⁇ y direction and spreads over the entire electrode surface 211b. Thereby, the protrusion of the solder from which the molten solder flows out from the electrode surfaces 211a and 211b is suppressed, and the voids are further reduced.
  • the present invention is not limited to the case where all of the emitter electrode surfaces formed on one surface of the IGBT chip have a comb-teeth shape.
  • a plurality of emitter electrode surfaces are formed on one surface of the semiconductor element, at least one electrode surface is formed in a comb shape.
  • both comb-like electrode surfaces 311 a and 311 b and a strip-shaped electrode surface 311 c may be formed on one surface of the IGBT chip 301.
  • the solder setting region 350 is set at substantially the center of the IGBT chip 301 so as to include a part of the electrode surfaces 311a and 311b as shown.
  • the molten solder is dropped at one location in the center of the electrode surface of the semiconductor element.
  • the present invention is not limited to this.
  • molten solder may be dropped at a plurality of locations.
  • FIG. 14A when four emitter electrode surfaces having two pairs of strip electrode surfaces are arranged in parallel, or as shown in FIG. 14B, it has eight pairs of strip electrode surfaces.
  • the present invention can also be applied when one emitter electrode surface is provided.
  • the solder is spread by dropping the molten solder into two locations of the solder setting area 450a and the solder setting area 450b including a part of the main solder spreading electrode surface.
  • the solder Since the solder flows radially from the electrode surface so as to extend from the electrode surface to the sub-solder electrode surface, the solder can be spread over the entire electrode surface. As shown in FIG. 14 (b), the solder is spread by dropping the molten solder into two places, a solder setting area 550a and a solder setting area 550b including a part of the main solder spreading electrode surface, and spreading the solder. Since the solder flows radially from the electrode surface so as to extend from the electrode surface to the sub-solder electrode surface, the solder can be spread over the entire electrode surface.
  • the position, number, and area of the solder setting region are appropriately determined according to the size of the IGBT chip, the number of electrode surfaces, the shape of the electrode surfaces, and the like.
  • the electrode surface of the semiconductor device according to the present invention is formed in various shapes having a main solder spreading electrode surface and a sub solder spreading electrode surface extending in a comb shape on both sides from the main solder spreading electrode surface. be able to. Another example of the shape of the electrode surface will be described with reference to FIGS. 15 (a) to 15 (c).
  • the electrode surface 611a shown in FIG. 15A has a main solder spreading electrode surface 611a1 extending in the x direction, a sub solder spreading electrode surface 611a2 extending in a comb shape from the main solder spreading electrode surface 611a1 in the + y direction, A sub solder spreading electrode surface 611a3 extending in a comb shape in the ⁇ y direction from the main solder spreading electrode surface 611a1 is provided.
  • the secondary solder spreading electrode surface 611a2 extending in the + y direction has four belt-like electrode surfaces
  • the secondary solder spreading electrode surface 611a3 extending in the -y direction has three belt-like electrode surfaces. is doing.
  • An electrode surface 711a shown in FIG. 15B includes a main solder spreading electrode surface 711a1 extending in the x direction, a sub solder spreading electrode surface 711a2 extending in a comb shape from the main solder spreading electrode surface 711a1 in the + y direction, A secondary solder spreading electrode surface 711a3 extending in a comb shape in the ⁇ y direction from the main solder spreading electrode surface 711a1.
  • the secondary solder spreading electrode surface 711a2 extending in the + y direction has four belt-like electrode surfaces, and the secondary solder spreading electrode surface 711a3 extending in the -y direction has six belt-like electrode surfaces.
  • the width in the x direction of the strip-shaped electrode surface of the sub solder spreading electrode surface 711a2 is different from the width in the x direction of the strip shaped electrode surface of the sub solder spreading electrode surface 711a3.
  • the electrode surface 811a shown in FIG. 15C has three pairs of narrow strip-shaped electrode surfaces and two pairs of wide strip-shaped electrode surfaces on both sides (+ y direction and ⁇ y) from the main solder spreading electrode surface 811a1.
  • Direction As shown in FIGS. 15A to 15C, it has a main solder spreading electrode surface extending in one direction and a sub solder spreading electrode surface extending in a comb shape from both sides of the main solder spreading electrode surface.
  • the molten solder arranged in the solder setting area including the main solder spreading electrode surface can be spread over the entire electrode surface.
  • the manufacturing method of the power semiconductor unit 330 according to the present invention is not limited to the case shown in FIG.
  • molten solder 6a, 8a is dropped onto IGBT chip 1 and diode chip 2
  • second bus bar 4 is positioned above molten solder 6a, 8a with IGBT chip 1 and diode chip 2 disposed below.
  • the second bus bar 4 and the IGBT chip 1 and the diode chip 2 are joined by the solders 6 and 8 to form the second bus bar set 30.
  • the second bus bar set 30 is turned over and placed, and the molten solders 5a and 7a are dropped onto the IGBT chip 1 and the diode chip 2 so that the first bus bar 3 is placed with the second bus bar set 30 placed below.
  • the first bus bar 3, the IGBT chip 1, and the diode chip 2 may be bonded to the molten solders 5 a and 7 a from above by solders 5 and 7.
  • the present invention is not limited to the case where the IGBT chip 1 and the diode chip 2 are simultaneously brought close to the second bus bar 4 and bonded together.
  • the junction between the second bus bar 4 and the IGBT chip 1 and the diode chip 2 and the junction between the first bus bar 3 and the IGBT chip 1 and the diode chip 2 may be reversed.
  • the dropping method in which the molten solder is dropped and the electrode surface of the semiconductor element and the bus bar are joined by the solder is adopted, but the present invention is not limited to this.
  • a method may be employed in which the cream solder is placed in the solder setting area and then placed in a heating furnace to reflow the solder.
  • a semiconductor element having at least one comb-like electrode surface on one surface, a first conductor member, and a second conductor member are prepared.
  • an electrode surface provided on the other surface of the semiconductor element is joined to the second conductor member by solder.
  • a predetermined region including a part of the main solder spreading electrode surface constituting both comb-like electrode surfaces of the semiconductor element for example, the solder setting region 50 of FIG. 10 or the first region facing the predetermined region. Cream solder is installed in the area of the conductor member.
  • the cream solder is heated and melted, and the melted solder is spread from the main solder spreading electrode surface to the sub solder by bringing the first conductor member and the electrode surface provided on one surface of the semiconductor element closer to each other.
  • the electrode surface provided on one surface of the semiconductor element is joined to the first conductor member by soldering and spreading on the electrode surface.
  • the first conductor member and the second conductor member are sealed with a sealing member.
  • the solder is heated and melted, and the conductor member and the electrode surface of the semiconductor element are brought close to each other, whereby the melted solder can be spread on the electrode surface.
  • the IGBT is adopted as the switching semiconductor element.
  • other semiconductor elements such as a metal oxide semiconductor field effect transistor (MOSFET) may be adopted depending on a necessary frequency and voltage.
  • MOSFET metal oxide semiconductor field effect transistor
  • IGBT is suitable when the DC voltage is relatively high
  • MOSFET is suitable when the DC voltage is relatively low.
  • the electrode surface of the emitter electrode has a double comb shape, but the present invention is not limited to this. It is only necessary that at least one of the electrode surfaces provided on one surface of the semiconductor element has a comb shape.
  • the semiconductor device incorporated in the power conversion device mounted on the hybrid electric vehicle or the pure electric vehicle has been described, but the present invention is not limited to this.
  • Semiconductors mounted on power conversion devices that can be used in power supply devices for vehicles such as other electric vehicles, such as railway vehicles such as hybrid trains, passenger cars such as buses, cargo vehicles such as trucks, and industrial vehicles such as battery-powered forklift trucks
  • the present invention may be applied to an apparatus.

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Abstract

　半導体装置は、両面のそれぞれに少なくとも１つの電極面を有する半導体素子と、半導体素子の一方の面に設けられる電極面に半田により接合される第１導体部材と、半導体素子の他方の面に設けられる電極面に半田により接合される第２導体部材とを備え、半導体素子の一方の面に設けられる電極面の少なくとも１つが両櫛歯状とされている。

Description

半導体装置ならびに半導体装置の製造方法
　本発明は、半導体素子の両面が半田により導体部材に接合された構成を有する半導体装置に関する。
　ハイブリット型の電気自動車や純粋な電気自動車の電力変換装置などに搭載される半導体装置には、ＩＧＢＴチップなどのパワー半導体素子が用いられている。ＩＧＢＴチップは、ＩＧＢＴセルが数千～数万個あるいは数千～数万本繰り返し配置される構造となっている。ＩＧＢＴチップはエミッタ電極、コレクタ電極およびゲート電極からなる３端子デバイスであり、構造上、エミッタ電極とゲート電極はＩＧＢＴチップの同一面内に絶縁された状態で形成される。
　ゲート電極には制御信号の伝達遅延時間のばらつきを小さくするために、アルミニウムなどの導電率の高い材料を用いたゲート配線が接続され、このゲート配線はポリシリコン配線等を介してＩＧＢＴセルのゲートに接続される。
　ＩＧＢＴチップのエミッタ電極は、このゲート配線によって複数の領域に分割されることが一般的である（特許文献１参照）。なお、この分割されたエミッタ電極は、半田により導体部材と接続される場合がある。
　ハイブリット型の電気自動車や純粋な電気自動車の電力変換装置などに搭載される半導体装置は、近年のシステムの大出力化にともない、入力電流が増加する傾向にある。半導体素子と導体部材との接続に半田を用いる場合、入力電流の増加は半導体素子の温度変化を大きくし、半導体素子と導体部材とを接続する半田を劣化させる。半田の劣化は、ボイド率に影響するため、半田接続の時に生じるボイドを抑制することが、温度変化に対する半田の寿命を向上させる上で重要な課題となっている。
日本国特開２００４－２２１２６９号公報
　特許文献１に記載の半導体装置のように、一般的な半導体装置では、ポリシリコン配線に比べて電気抵抗の小さいアルミゲート配線により、エミッタ電極が複数に分割されている。アルミゲート配線は、半田との濡れ性が低いポリイミド樹脂などの絶縁性を有する保護膜によって覆われている。
　このため、半田によってエミッタ電極面と導体部材とを接続する場合、ＩＧＢＴチップのエミッタ電極面での半田の広がりが保護膜によって制限され、半田が不均等に流れることによりボイド率が高くなってしまうといった問題があった。さらに、半田の広がり方向が所定方向に制限されるため、その方向に半田が過剰に流れ、ＩＧＢＴチップのエミッタ電極面を越えて流れる半田流れが発生するおそれもある。
　本発明の第１の態様による半導体装置は、両面のそれぞれに少なくとも１つの電極面を有する半導体素子と、半導体素子の一方の面に設けられる電極面に半田により接合される第１導体部材と、半導体素子の他方の面に設けられる電極面に半田により接合される第２導体部材とを備え、半導体素子の一方の面に設けられる電極面の少なくとも１つが両櫛歯状とされている。
　本発明の第２の態様によると、第１の態様の半導体装置において、両櫛歯状の電極面は、主半田広がり電極面と、主半田広がり電極面から両側方に櫛状に延在する副半田広がり電極面とを有していることが好ましい。
　本発明の第３の態様によると、第１または２の半導体装置において、両櫛歯状の電極面の周縁にはゲート配線が配設され、ゲート配線は、両櫛歯状の電極面に比べて半田の濡れ性が低く、かつ、絶縁性を有する保護膜によって覆われていることが好ましい。
　本発明の第４の態様によると、第１ないし３のいずれか１の態様の半導体装置において、第１導体部材および第２導体部材は銅材からなり、第１導体部材および第２導体部材における半田との接合面には表面加工が施されていないことが好ましい。
　本発明の第５の態様による半導体装置は、ＩＧＢＴチップおよびダイオードチップと、ＩＧＢＴチップの一方の面に少なくとも１つ設けられるエミッタ電極面およびダイオードチップの一方の面に設けられるアノード電極面に半田により接合される第１導体板と、ＩＧＢＴチップの他方の面に設けられるコレクタ電極面およびダイオードチップの他方の面に設けられるカソード電極面に半田により接合される第２導体板とを備え、ＩＧＢＴチップの一方の面に設けられるエミッタ電極面の少なくとも１つは両櫛歯状とされ、両櫛歯状の電極面は、主半田広がり電極面と、主半田広がり電極面から両側方に櫛状に延在する副半田広がり電極面とを有し、エミッタ電極面の周縁にはゲート配線が配設され、ゲート配線は、エミッタ電極面に比べて半田の濡れ性が低く、かつ、絶縁性を有する保護膜によって覆われている。
　本発明の第６の態様による半導体装置は、インバータ回路の上下アームを構成する上アーム用ＩＧＢＴチップおよび上アーム用ダイオードチップならびに下アーム用ＩＧＢＴチップおよび下アーム用ダイオードチップと、上アーム用ＩＧＢＴチップの一方の面に少なくとも１つ設けられるエミッタ電極面および上アーム用ダイオードチップの一方の面に設けられるアノード電極面に半田により接合される第２交流電極リードフレームと、上アーム用ＩＧＢＴチップの他方の面に設けられるコレクタ電極面および上アーム用ダイオードチップの他方の面に設けられるカソード電極面に半田により接合される直流正極電極リードフレームと、下アーム用ＩＧＢＴチップの一方の面に少なくとも１つ設けられるエミッタ電極面および下アーム用ダイオードチップの一方の面に設けられるアノード電極面に半田により接合される直流負極電極リードフレームと、下アーム用ＩＧＢＴチップの他方の面に設けられるコレクタ電極面および下アーム用ダイオードチップの他方の面に設けられるカソード電極面に半田により接合される第１交流電極リードフレームとを備え、上アーム用ＩＧＢＴチップおよび下アーム用ＩＧＢＴチップの一方の面のそれぞれに設けられるエミッタ電極面の少なくとも１つは両櫛歯状とされ、両櫛歯状の電極面は、主半田広がり電極面と、主半田広がり電極面から両側方に櫛状に延在する副半田広がり電極面とを有し、エミッタ電極面の周縁にはゲート配線が配設され、ゲート配線は、エミッタ電極面に比べて半田の濡れ性が低く、かつ、絶縁性を有する保護膜によって覆われている。
　本発明の第７の態様によると、第１ないし６のいずれか１の態様の半導体装置において、両櫛歯状の電極面には、半田の濡れ性を向上させるニッケルめっきが施されていることが好ましい。
　本発明の第８の態様による半導体装置の製造方法は、第２ないし４のいずれか１の態様の半導体装置を製造する方法であって、両櫛歯状の電極面を少なくとも１つ有する半導体素子と、第１導体部材と、第２導体部材とを準備する工程と、半田により半導体素子の他方の面に設けられる電極面を第２導体部材に接合する工程と、半導体素子の両櫛歯状の電極面を構成する主半田広がり電極面の一部を含む所定領域、または、第１導体部材における所定領域に対向する領域に溶融状態の半田を滴下する工程と、第１導体部材と半導体素子の一方の面に設けられる電極面との距離を近づけることで溶融状態の半田を主半田広がり電極面から副半田広がり電極面に広がらせて、半田により半導体素子の一方の面に設けられる電極面を第１導体部材に接合する工程と、第１導体部材と第２導体部材とを封止部材により封止する工程とを含む。
　本発明の第９の態様による半導体装置の製造方法は、第２ないし４のいずれか１の態様の半導体装置を製造する方法であって、両櫛歯状の電極面を少なくとも１つ有する半導体素子と、第１導体部材と、第２導体部材とを準備する工程と、半田により半導体素子の他方の面に設けられる電極面を第２導体部材に接合する工程と、第１導体部材の滴下領域に溶融状態の半田を滴下する工程と、滴下領域に滴下された半田が半導体素子の一方の面に設けられた両櫛歯状の電極面を構成する主半田広がり電極面の一部を含む所定領域に対向して配置されるように位置決めする工程と、第１導体部材に半導体素子の一方の面を近づけ、溶融状態の半田を主半田広がり電極面から副半田広がり電極面に広がらせて、半田により半導体素子の一方の面に設けられる電極面を第１導体部材に接合する工程と、第１導体部材と第２導体部材とを封止部材により封止する工程とを含む。
　本発明の第１０の態様による半導体装置の製造方法は、第５の態様の半導体装置を製造する方法であって、両櫛歯状のエミッタ電極面を少なくとも１つ有するＩＧＢＴチップと、ダイオードチップと、第１導体板と、第２導体板とを準備する工程と、ＩＧＢＴチップのコレクタ電極面およびダイオードチップのカソード電極面のそれぞれの中央位置、または、それぞれの中央位置に対向する第２導体板の所定位置に溶融状態の半田を滴下する工程と、第２導体板にＩＧＢＴチップのコレクタ電極面およびダイオードチップのカソード電極面を同時に近づけ、溶融状態の半田をコレクタ電極面およびカソード電極面に広がらせて、半田によりＩＧＢＴチップのコレクタ電極面およびダイオードチップのカソード電極面のそれぞれを第２導体板に接合する工程と、ＩＧＢＴチップのエミッタ電極面を構成する主半田広がり電極面の一部を含む所定領域およびダイオードチップのアノード電極面の中央位置、または、所定領域およびアノード電極面の中央位置に対向する第１導体板の所定位置に溶融状態の半田を滴下する工程と、第１導体板にＩＧＢＴチップのエミッタ電極面およびダイオードチップのアノード電極面を同時に近づけ、溶融状態の半田をエミッタ電極面における主半田広がり電極面から副半田広がり電極面に広がらせるとともに、溶融状態の半田をアノード電極面に広がらせて、半田によりＩＧＢＴチップのエミッタ電極面およびダイオードチップのアノード電極面のそれぞれを第１導体板に接合する工程と、第１導体板と第２導体板とを封止部材により封止する工程とを含む。
　本発明の第１１の態様による半導体装置の製造方法は、第２ないし４のいずれか１の態様の半導体装置を製造する方法であって、両櫛歯状の電極面を少なくとも１つ有する半導体素子と、第１導体部材と、第２導体部材とを準備する工程と、半田により半導体素子の他方の面に設けられる電極面を第２導体部材に接合する工程と、半導体素子の両櫛歯状の電極面を構成する主半田広がり電極面の一部を含む所定領域、または、第１導体部材における所定領域に対向する領域に半田を設置する工程と、半田を加熱して溶融させ、第１導体部材と半導体素子の一方の面に設けられる電極面との距離を近づけることで溶融状態の半田を主半田広がり電極面から副半田広がり電極面に広がらせて、半田により半導体素子の一方の面に設けられる電極面を第１導体部材に接合する工程と、第１導体部材と第２導体部材とを封止部材により封止する工程とを含む。
　本発明によれば、ボイドの発生と半田流れを抑制し、半田接合部の長寿命化を図ることができるため、高い信頼性の半導体装置と、その製造方法を提供することができる。
パワーモジュールの外観を示す斜視図。 パワーモジュールの断面模式図。 パワー半導体ユニットの分解斜視図。 パワー半導体ユニットの回路図。 パワー半導体ユニットの断面模式図。 ＩＧＢＴチップのエミッタ電極面およびダイオードチップのアノード電極面を示す模式図。 （ａ）は図６のＢ－Ｂ線で切断したパワー半導体ユニットの断面模式図、（ｂ）は（ａ）のＤ部拡大図。 図６のＣ－Ｃ線で切断したパワー半導体ユニットの断面模式図。 パワー半導体ユニットの製造方法を示す工程図。 半田の設定位置と半田の広がり方向を示す模式図。 ＩＧＢＴチップのエミッタ電極面において溶融状態の半田が広がる様子を示す模式図。 従来のＩＧＢＴチップのエミッタ電極面において溶融状態の半田が広がる様子を示す模式図。 変形例に係るＩＧＢＴチップのエミッタ電極面における半田の設定位置と半田の広がり方向を示す模式図。 変形例に係るＩＧＢＴチップのエミッタ電極面における半田の設定位置と半田の広がり方向を示す模式図。 変形例に係るＩＧＢＴチップのエミッタ電極面を示す模式図。
　以下、図を参照して本発明を実施するための形態について説明する。図１はパワーモジュール３００の外観を示す斜視図であり、図２はパワーモジュール３００の断面模式図である。パワーモジュール３００は、スイッチング素子を含みトランスファーモールドされたパワー半導体ユニット３３０（図２参照）を、金属製のモジュールケース３１０内に収納したものである。パワーモジュール３００は、たとえば、純粋な電気自動車やハイブリッド型の電気自動車等の電気車両に搭載される電力変換装置に用いられる。
　モジュールケース３１０は、複数の放熱フィン３０５が立設された１対の放熱板を有している。放熱板は、熱伝導率の高いアルミニウムなどの金属により形成される。図２に示すように、図中左側に位置する一方の放熱板には、複数の放熱フィン３０５が立設された厚肉部３０３と、その周囲に設けられた薄肉部３０２とが設けられている。薄肉部３０２を塑性変形させることで、内部に収納されたパワー半導体ユニット３３０の放熱面と、厚肉部３０３の内周面とが密着されている。図１に示すように、モジュールケース３１０の一面からは、パワー半導体ユニット３３０に設けられた直流正極端子３１５Ｂ、直流負極端子３１９Ｂおよび交流端子３２１と信号端子３２５Ｌ，３２５Ｕ，３２６Ｌ，３２６Ｕとが突出している。
　図３はパワー半導体ユニット３３０の分解斜視図であり、図４はパワー半導体ユニット３３０の回路図である。なお、図３では、トランスファーモールドの図示を省略した。本実施形態では、パワー半導体素子としてＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）チップ１５５，１５７とダイオードチップ１５６，１５８とが設けられている。図３に示す例では、ＩＧＢＴチップ１５５，１５７およびダイオードチップ１５６，１５８がそれぞれ並列に２つ設けられているが、図４の回路図では、説明を簡単にするために、それらの一方のみを示した。
　図３に示すように、パワー半導体素子を挟んで一方の側に直流正極電極リードフレーム３１５と第１交流電極リードフレーム３１６とが略同一平面状に配置されており、他方の側には第２交流電極リードフレーム３１８と直流負極電極リードフレーム３１９とが略同一平面状に配置されている。
　各パワー半導体素子は板状の扁平構造であり、各電極は表裏面に形成されている。直流正極電極リードフレーム３１５の素子固着部３２２には、上アーム用ＩＧＢＴチップ１５５のコレクタ電極と上アーム用ダイオードチップ１５６のカソード電極とが半田１６０により固着されている。
　一方、第１交流電極リードフレーム３１６の素子固着部３２２には、下アーム用ＩＧＢＴチップ１５７のコレクタ電極と下アーム用ダイオードチップ１５８のカソード電極とが、半田１６０により固着されている。
　第２交流電極リードフレーム３１８の素子固着部３２２には、上アーム用ＩＧＢＴチップ１５５のエミッタ電極と上アーム用ダイオードチップ１５６のアノード電極とが半田１６０により固着されている。一方、直流負極電極リードフレーム３１９の素子固着部３２２には、下アーム用ＩＧＢＴチップ１５７のエミッタ電極と下アーム用ダイオードチップ１５８のアノード電極とが半田１６０により固着されている。
　図３に示すように、直流正極電極リードフレーム３１５と第２交流電極リードフレーム３１８とは、各ＩＧＢＴチップ１５５およびダイオードチップ１５６を挟むようにして略平行に対向している。同様に、第１交流電極リードフレーム３１６と直流負極電極リードフレーム３１９とは、各ＩＧＢＴチップ１５７およびダイオードチップ１５８を挟むようにして略平行に対向している。図４に示すように、第１交流電極リードフレーム３１６と第２交流電極リードフレーム３１８とは、中間電極１５９を介して接続されている。中間電極１５９で接続することにより、上アーム回路と下アーム回路が電気的に接続され、図４に示すような上下アーム直列回路が形成される。
　図３に示すように、直流正極配線３１５Ａは直流正極電極リードフレーム３１５に一体で形成され、直流正極配線３１５Ａの先端には直流正極端子３１５Ｂが形成されている。同様に、直流負極配線３１９Ａは直流負極電極リードフレーム３１９に一体で形成され、直流負極配線３１９Ａの先端には直流負極端子３１９Ｂが形成されている。第１交流電極リードフレーム３１６には交流配線３２０が一体で形成されており、交流配線３２０の先端には交流端子３２１が形成されている。
　直流正極配線３１５Ａと直流負極配線３１９Ａの間には、熱可塑性樹脂端子ブロック６００が設けられている。図１に示すように、直流正極配線３１５Ａと直流負極配線３１９Ａは、略平行に対向した状態でモジュールケース３１０から突出するように延在している。信号端子３２５Ｌ，３２５Ｕ，３２６Ｌ，３２６Ｕは、熱可塑性樹脂端子ブロック６００に一体成型されており、直流正極配線３１５Ａおよび直流負極配線３１９Ａと同様の方向に、モジュールケース３１０から突出するように延在している。そのため、直流正極配線３１５Ａと直流負極配線３１９Ａとの間の絶縁性と、信号用配線と各配線板との絶縁性が確保でき、高密度配線が可能となる。
　熱可塑性樹脂端子ブロック６００に用いる樹脂材料には、トランスファーモールドの金型の温度以上（たとえば、１８０℃以上）の耐熱性と、絶縁性とを有する熱可塑性樹脂が適しており、ポリフェニレンサルファイド（ＰＰＳ）や液晶ポリマー（ＬＣＰ）などが用いられる。
　図５はパワー半導体ユニット３３０の断面模式図である。図６はＩＧＢＴチップ１のエミッタ電極１１の電極面１１ａおよびダイオードチップ２のアノード電極２１の電極面２１ａを示す模式図であって、図５のＡ－Ａ断面図である。図６において封止部材２０および半田５，７は図示を省略している。なお、図６で示すように、ＩＧＢＴチップ１、ダイオードチップ２が１列に並べられる方向をｙ方向とし、ｙ方向に直交する方向をｘ方向とする。
　上アーム用ＩＧＢＴチップ、上アーム用ダイオードチップおよび上アーム用各種配線等の上アーム用の構成部材と、下アーム用ＩＧＢＴチップ、下アーム用ダイオードチップおよび下アーム用各種配線等の下アーム用の構成部材とは、ほぼ同じ構成であるため、上アーム用または下アーム用の構成部材を以下のように定義して説明する。
　上アーム用ＩＧＢＴチップ１５５および下アーム用ＩＧＢＴチップ１５７は単にＩＧＢＴチップ１とし、上アーム用ダイオードチップ１５６および下アーム用ダイオードチップ１５８は単にダイオードチップ２と称す。第２交流電極リードフレーム３１８および直流負極電極リードフレーム３１９は単に第１バスバー３と称し、直流正極電極リードフレーム３１５および第１交流電極リードフレーム３１６は単に第２バスバー４と称す。信号端子３２５Ｕ，３２５Ｌ，３２６Ｌ，３２６Ｕを含む信号用配線は、それぞれゲートピン９と称す。
　図５および図６に示すように、ＩＧＢＴチップ１は、一方の面にエミッタ電極１１の電極面１１ａと、端子電極１３、すなわちエミッタ端子電極１３ａおよびゲート端子電極１３ｂとが設けられ、他方の面にコレクタ電極１２の電極面１２ａが設けられている。ゲート端子電極１３ｂには、パワーモジュールに接続されるドライバ回路（不図示）からの駆動信号が入力される。エミッタ端子電極１３ａからは、ＩＧＢＴチップ１のエミッタ電極１１に流れる電流の情報がドライバ回路（不図示）に出力される。なお、本実施の形態に係るＩＧＢＴチップ１は、１０ｍｍ×１０ｍｍ程度のサイズである。
　エミッタ電極１１の電極面１１ａは、第１バスバー３に半田５により接合されている。コレクタ電極１２の電極面１２ａは、第２バスバー４に半田６により接合されている。エミッタ端子電極１３ａおよびゲート端子電極１３ｂのそれぞれは、アルミワイヤー１０でゲートピン９と接合されている。
　ダイオードチップ２は、一方の面にアノード電極２１の電極面２１ａが設けられ、他方の面にカソード電極２２の電極面２２ａが設けられている。アノード電極２１の電極面２１ａは、第１バスバー３のＩＧＢＴチップ１が接合された面と同一の面上に半田７により接合されている。カソード電極２２の電極面２２ａは、第２バスバー４のＩＧＢＴチップ１が接合された面と同一の面上に半田８により接合されている。
　エミッタ電極面１１ａ、アノード電極面２１ａ、コレクタ電極面１２ａおよびカソード電極面２２ａのそれぞれには、半田が接合可能な、たとえば、ニッケルめっきなどの表面加工が施されている。一方、第１バスバー３および第２バスバー４は銅材からなり、第１バスバー３および第２バスバー４における半田との接合面にはめっきなどの表面加工は施されておらず、表面は銅材無垢である。
　図５に示すように、第１バスバー３および第２バスバー４の間に挟持されたＩＧＢＴチップ１およびダイオードチップ２と、ＩＧＢＴチップ１とゲートピン９とを接続するアルミワイヤー１０は、エポキシ樹脂などの絶縁性を有する絶縁性有機材料の封止部材２０により封止されている。ゲートピン９のアルミワイヤー１０との接続部の反対側は、封止部材２０の外側に突き出し、駆動信号の外部インターフェイスに用いられる。
　図２に示すように、第１バスバー３（３１８，３１９）および第２バスバー４（３１５，３１６）におけるＩＧＢＴチップ１（１５５，１５７）およびダイオードチップ２（１５６，１５８）が接続された面と反対側の面は、樹脂封止されずに露出している。この露出面は、モジュールケース３１０の内面と絶縁シート３３３などを介して接している。したがって、ＩＧＢＴチップ１とダイオードチップ２から発生した熱は、第１バスバー３（３１８，３１９）および第２バスバー４（３１５，３１６）や絶縁シート３３３を介してモジュールケース３１０の放熱フィン３０５やモジュールケース３１０の表面に伝わり、放熱フィン３０５やモジュールケース３１０の表面に接する冷媒（不図示）によって放熱される。
　図６に示すように、エミッタ電極１１の電極面１１ａは、平面視でｘ方向に延びる電極面から＋ｙ方向および－ｙ方向に４対の帯状の電極面が突き出した両櫛歯状とされている。具体的には、エミッタ電極１１の電極面１１ａは、図示するようにその中央部にｘ方向に延在する主半田広がり電極面１１ａ１を有し、主半田広がり電極面１１ａ１から両側方である＋ｙ方向および－ｙ方向に櫛状に延在する副半田広がり電極面１１ａ２とを有している。
　ダイオードチップ２のアノード電極２１の電極面２１ａの形状は、図示するように平面視で矩形状とされ、図示しないがＩＧＢＴチップ１のコレクタ電極１２の電極面１２ａおよびダイオードチップ２のカソード電極２２の電極面２２ａの形状も平面視で矩形状とされている。
　図７（ａ）は図６のＢ－Ｂ線で切断したパワー半導体ユニット３３０の断面模式図であり、図７（ｂ）は図７（ａ）のＤ部拡大図である。図８は図６のＣ－Ｃ線で切断したパワー半導体ユニット３３０の断面模式図である。図７および図８において封止部材２０は省略している。図６および図７に示すように、副半田広がり電極面１１ａ２を構成する隣り合う帯状電極面同士の間には、ＩＧＢＴ各セルのゲート（不図示）と、ゲート端子電極１３ｂとを接続するためのアルミゲート配線１５が配設されている。
　図示しないが、アルミゲート配線１５とＩＧＢＴ各セルのゲートとは、たとえばポリシリコン配線を介して接続されている。ポリシリコン配線の電気抵抗値は、アルミゲート配線１５の電気抵抗値に比べて数十～数百倍程度高い。したがって、ポリシリコン配線が長くなるとＩＧＢＴ各セルまでの電気抵抗が増えるため、ＩＧＢＴ各セルの応答性が悪くなる。本実施の形態では、アルミゲート配線１５を副半田広がり電極面１１ａ２を構成する隣り合う帯状電極面同士の間を含むエミッタ電極面１１ａの周縁に配設することで、ポリシリコン配線を短くしている。
　図６～図８に示すように、アルミゲート配線１５は、絶縁性を有する保護膜１４によって覆われている。各電極面を含むＩＧＢＴチップ１の面全体に保護膜を塗布し、乾燥後、電極面上の保護膜をエッチング処理により除去することで、図７および図８に示すように、アルミゲート配線１５を覆う保護膜１４がチップ電極面上に形成される。図６に示すように、ダイオードチップ２のアノード電極２１の電極面２１ａの周縁には、絶縁性を有する保護膜２４が形成されている。保護膜１４，２４としては、ポリイミド樹脂やポリアミド樹脂などを用いることができる。
　保護膜１４は、ＩＧＢＴチップ１のエミッタ電極面１１ａに比べて半田の濡れ性が低い。したがって、図７（ｂ）に示すように、ＩＧＢＴチップ１の副半田広がり電極面１１ａ２を構成する隣り合う帯状電極面同士の間に形成される保護膜１４の上に、半田５が濡れ広がらない空間であって、半田５が存在しない未濡れ空間１６が形成されている。なお、未濡れ空間１６は、図７（ａ）の破線Ｘで示すように、第１バスバー３まで貫通する場合もある。
　図８に示すように、図６のＣ－Ｃ断面には、保護膜１４が存在せず、ボイド（微細な空洞）などの半田欠陥（不図示）を除き未濡れ空間１６は存在しない。このように、未濡れ空間１６は、副半田広がり電極面１１ａ２を構成する帯状電極面同士の間に形成される保護膜１４上に存在している（図７参照）。
　本発明に係る半導体装置の製造方法の実施形態を図９および図１０を参照して説明する。図９はパワー半導体ユニット３３０の製造方法を示す工程図であり、図１０は半田５ａ，７ａの設定位置と半田５ａ，７ａの広がり方向を示す模式図である。
　まず、ＩＧＢＴチップ１およびダイオードチップ２と、第１バスバー３と、第２バスバー４とを準備し、図９（ａ）に示すように第２バスバー４の表面の半田滴下領域に溶融状態の半田６ａおよび半田８ａを滴下する。第２バスバー４の表面の半田滴下領域は、ＩＧＢＴチップ１のコレクタ電極面１２ａの中央位置に対向する領域、および、ダイオードチップ２のカソード電極面２２ａの中央位置に対向する領域である。ＩＧＢＴチップ１のコレクタ電極面１２ａの中央位置に対向する第２バスバー４の半田滴下領域には半田６ａを滴下する。ダイオードチップ２のカソード電極面２２ａの中央位置に対向する第２バスバー４の半田滴下領域には半田８ａを滴下する。
　続いて、図９（ｂ）に示すように、溶融状態の半田６ａがＩＧＢＴチップ１のコレクタ電極面１２ａの中央位置に対向して配置され、かつ、溶融状態の半田８ａがダイオードチップ２のカソード電極面２２ａの中央位置に対向して配置されるよう、第２バスバー４のチップ実装面上においてＩＧＢＴチップ１とダイオードチップ２を位置決めする。
　位置決めを行った後、第２バスバー４にＩＧＢＴチップ１のコレクタ電極面１２ａおよびダイオードチップ２のカソード電極面２２ａを溶融状態の半田６ａおよび半田８ａに同時に押し付け、溶融状態の半田６ａをコレクタ電極面１２ａで広がらせるとともに、溶融状態の半田８ａをカソード電極面２２ａで広がらせる。これにより、図９（ｃ）に示すように、半田６，８によりＩＧＢＴチップ１のコレクタ電極面１２ａおよびダイオードチップ２のカソード電極面２２ａが一括して第２バスバー４に接合される。
　このようにして形成されたものを第２バスバー組み３０と称す。なお、上述したようにＩＧＢＴチップ１のコレクタ電極面１２ａおよびダイオードチップ２のカソード電極面２２ａは平面視矩形状とされている。したがって、それぞれの電極面中央に設置された溶融状態の半田６ａ，８ａは、外方に向かって（放射状に）均等に流れ、それぞれの電極面全体に広がる。
　図９（ｄ）に示すように、第１バスバー３の表面の滴下領域に溶融状態の半田５ａおよび半田７ａを滴下する。第１バスバー３の表面の滴下領域は、ＩＧＢＴチップ１のエミッタ電極面１１ａの中央に位置する半田設定領域５０（図１０参照）に対向する領域、および、ダイオードチップ２のアノード電極面２１ａの中央に位置する半田設定領域７０（図１０参照）に対向する領域である。半田設定領域５０に対向する第１バスバー３の滴下領域には半田５ａを滴下し、半田設定領域７０ａに対向する第１バスバー３の滴下領域には半田７ａを滴下する。
　半田設定領域５０は、図１０に示すように、ＩＧＢＴチップ１のエミッタ電極面１１ａを構成する主半田広がり電極面１１ａ１の一部を含むように設定される。図９（ｅ）に示すように、溶融半田５ａが半田設定領域５０（図１０参照）に対向して配置され、かつ、溶融半田７ａが半田設定領域７０（図１０参照）に対向して配置されるよう、図９（ｃ）に示す第２バスバー組３０を裏返しにし、第１バスバー３のチップ実装面上においてＩＧＢＴチップ１とダイオードチップ２を位置決めする。
　位置決めを行った後、裏返しにした第２バスバー組み３０のＩＧＢＴチップ１のエミッタ電極面１１ａおよびダイオードチップ２のアノード電極面２１ａを第１バスバー３上の溶融半田５ａ，７ａに同時に押し付ける。
　各電極面１１ａ，２１ａを溶融状態の半田５ａ，７ａに押し当てることで、図１０中の矢印で模式的に示すように、溶融状態の半田５ａはエミッタ電極面１１ａの半田設定領域５０から外方に向かって（放射状に）広がり、溶融状態の半田７ａはアノード電極面２１ａの半田設定領域７０から外方に向かって（放射状に）広がる。なお、上述したようにダイオードチップ２のアノード電極面２１ａは平面視矩形状とされている。したがって、溶融半田７ａは、アノード電極面２１ａの中央の半田設定領域７０から外方に向かって（放射状に）均等に流れ、アノード電極面２１ａ全体に広がる。
　第２バスバー組み３０を溶融状態の半田５ａに押し当てたときの半田５ａの広がりについて、図１１を参照して説明する。図１１は、ＩＧＢＴチップ１のエミッタ電極面１１ａにおいて溶融状態の半田５ａが広がる様子を示す模式図である。
　エミッタ電極面１１ａを溶融状態の半田５ａに押し当てると、図１１（ａ）～図１１（ｃ）に示すように、半田５ａは主半田広がり電極面１１ａ１の中央から＋ｘ方向および－ｘ方向に流れる。半田５ａは主半田広がり電極面１１ａ１から副半田広がり電極面１１ａ２に進出して、副半田広がり電極面１１ａ２の先端に向かって、すなわち＋ｙ方向および－ｙ方向に流れる。このとき、溶融状態の半田５ａは保護膜１４を跨ぐ方向には広がらない。これは、上述したように、副半田広がり電極面１１ａ２を構成する帯状電極面相互間を含む両櫛歯状のエミッタ電極面１１ａの周囲に設けられた保護膜１４の半田の濡れ性がエミッタ電極面１１ａに比べて低いためである。換言すれば、保護膜１４の半田に対する濡れ性に比べて、エミッタ電極面１１ａの半田に対する濡れ性の方が優れているためである。
　第１バスバー３とＩＧＢＴチップ１との距離を近づけていくと、溶融状態の半田５ａは、両櫛歯状のエミッタ電極１１に沿って、主半田広がり電極面１１ａ１から副半田広がり電極面１１ａ２に広がり（図１１（ａ）および図１１（ｂ）参照）、最終的にエミッタ電極面１１ａ全体に広がる（図１１（ｃ）参照）。
　このように、半田５ａをエミッタ電極面１１ａ上においても均等に広がらせることができるため、半田５ａの食み出しの抑制と、ボイドの低減効果が期待できる。
　その後、半田５ａ，７ａが電極面１１ａ，２１ａ全体に広がった状態で冷えると、図９（ｆ）に示すように半田５によりＩＧＢＴチップ１のエミッタ電極面１１ａに第１バスバー３が接合され、半田７によりダイオードチップ２のアノード電極面２１ａに第１バスバー３が接合される。
　さらに、図示していないが、ＩＧＢＴチップ１の端子電極１３（１３ａ，１３ｂ）の電極面のそれぞれとゲートピン９とをアルミワイヤー１０により電気的に接続し、封止部材２０によって第１バスバー３および第２バスバー４を含む各部材を封止することによってパワー半導体ユニット３３０が完成する（図５参照）。
　図１２は、従来のＩＧＢＴチップ１０１のエミッタ電極面１１１ａにおいて溶融状態の半田１０５ａが広がる様子を示す模式図である。従来のＩＧＢＴチップ１０１は、図１２に示すように、帯状のエミッタ電極面１１１ａが複数形成されている。なお、隣り合う帯状のエミッタ電極面１１１ａ相互間に介在する保護膜１１４の半田１０５ａに対する濡れ性は、エミッタ電極面１１１ａにの半田１０５ａに対する濡れ性に比べて低い。
　図９と同様の方法でエミッタ電極面１１１を溶融状態の半田１０５ａに押し当てると、図１２（ａ）に示すように、溶融半田１０５ａは保護膜１１４によって広がりが制限されるため、エミッタ電極面１１１ａ上の半田１０５ａの広がり方向は主にｙ方向となる。よって、図１２（ｂ）に示すように、半田１０５ａはｙ方向に過剰に流れる。
　この結果、図１２（ｃ）に示すように、エミッタ電極面１１１ａの全体に半田１０５ａが広がらず、半田１０５ａがエミッタ電極面１１１ａ上に存在しない半田未濡れエリア１０５ｂが形成されてしまったり、半田１０５ａがエミッタ電極面１１１ａを越えて流れる半田流れ１０５ｃが生じてしまったりすることがある。
　なお、特開２００６―２１０５１９号公報には、ポリイミド膜（絶縁性保護膜）に金属箔を設けて半田との接合性を向上させる技術が記載されている。この従来技術によれば、チップ上で半田を均等に広げることができる。しかしながら、この従来技術は、ポリイミド膜に金属箔を設けることで高コストとなり、さらに、金属箔と半田、および、金属箔とポリイミド膜の新たな接合部位が生じるため、接合部の寿命の低下が懸念される。
　以上説明した本実施の形態によれば、以下のような作用効果を奏することができる。
（１）エミッタ電極面１１ａは、主半田広がり電極面１１ａ１から両側方に櫛状に副半田広がり電極面１１ａ２が延在する両櫛歯状とされている。エミッタ電極面１１ａの周縁にはアルミゲート配線１５を覆うように半田濡れ性の低い保護膜１４が形成されている。エミッタ電極面１１ａの中央部に配置された溶融半田５ａは、エミッタ電極面１１ａと第１バスバー３とで挟まれることにより放射状に流れ、主半田広がり電極面１１ａ１と副半田広がり電極面１１ａ２上に満遍なく流れるとともに、エミッタ電極面１１ａを越えた半田流れを防止できる。
（２）溶融状態の半田が電極面において放射状に均等に広がるため、ボイドを電極外周側に排出してボイドを低減することができる。
（３）（１）および（２）により、半田接合部の寿命、および、製造歩留りが向上する。これにより、半導体装置の高信頼性、低コストが実現できる。
（４）なお、上述した特開２００６―２１０５１９号公報に記載の従来技術のように、保護膜の上に新たに金属箔を設ける必要がないため、コスト高とならない。
（５）本実施の形態のように半田を用いてバスバーと半導体素子とを接合する場合、バスバーの半田濡れ性が、半導体素子と半田の接合に影響する。バスバーの半田濡れ性が良すぎると、半田は主にバスバー側に広がり、半導体素子側に広がりにくくなる。逆に、バスバーの半田濡れ性が悪いと、半田はバスバー側に広がりにくくなり、半導体素子側に広がりすぎてしまう。本実施の形態では、第１バスバー３および第２バスバー４は銅材からなり、半田との接合面にはめっきなどの表面加工が施されていない。このため、半田を接合する時に、たとえば、バスバーを加熱するなどしてバスバーの温度を変えることで、バスバーの半田との濡れ性を調整することが可能となるため、容易に半導体素子と半田との接合性を向上することができる。
（６）ＩＧＢＴチップ１とダイオードチップ２とを一括して第１バスバー３に接合し、ＩＧＢＴチップ１とダイオードチップ２とを一括して第２バスバー４に接合する方法を採用した。これにより、接合時間を短く、すなわち生産工程を短縮することができるため、生産コストを低減できる。
（７）両櫛歯状のエミッタ電極面１１ａには、ニッケルめっきが施されているため、半田の濡れ性を向上させることができる。
　次のような変形も本発明の範囲内であり、変形例の一つ、もしくは複数を前述の実施形態と組み合わせることも可能である。
（１）本発明による半導体装置の電極面の形状は、上述した実施の形態に限定されない。たとえば、図１３（ａ）に示すように、ＩＧＢＴチップ２０１に複数の両櫛歯状の電極面２１１ａ，２１１ｂを設けてもよい。図１３（ａ）に示すＩＧＢＴチップ２０１では、ｘ方向に２分割された電極面２１１ａ，２１１ｂが設けられ、一方の電極面２１１ａはｘ方向に延びる主半田広がり電極面２１１ａ１を有し、主半田広がり電極面２１１ａ１から両側方である＋ｙ方向および－ｙ方向に櫛状に延在する副半田広がり電極面２１１ａ２を有している。他方の電極面２１１ｂも同様に、ｘ方向に延びる主半田広がり電極面２１１ｂ１を有し、主半田広がり電極面２１１ｂ１から両側方である＋ｙ方向および－ｙ方向に櫛状に延在する副半田広がり電極面２１１ｂ２を有している。
　半田設定領域２５０は、図示するように主半田広がり電極面２１１ａ１，２１１ｂ１の一部を含むようにＩＧＢＴチップ２０１のほぼ中央に設定される。一方の電極面２１１ａに設定される溶融状態の半田は、バスバーが押し当てられると、電極面２１１ａの形状に沿って、すなわち主半田広がり電極面２１１ａ１から副半田広がり電極面２１１ａ２に向かうように＋ｘ方向ならびに＋ｙ方向および－ｙ方向に流れて電極面２１１ａの全体に広がる。同様に、他方の電極面２１１ｂに設定される溶融状態の半田は、バスバーが押し当てられると、電極面２１１ｂの形状に沿って、すなわち主半田広がり電極面２１１ｂ１から副半田広がり電極面２１１ｂ２に向かうように－ｘ方向ならびに＋ｙ方向および－ｙ方向に流れて電極面２１１ｂの全体に広がる。これにより、溶融半田が電極面２１１ａ，２１１ｂから食み出して流れてしまう半田の食み出しが抑制され、さらに、ボイドが低減される。
（２）本発明は、ＩＧＢＴチップの一方の面に形成されるエミッタ電極面の全てを両櫛歯状とする場合に限定されない。半導体素子の一方の面にエミッタ電極面が複数形成される場合、少なくとも１つの電極面が両櫛歯状に形成される。たとえば、図１３（ｂ）に示すように、ＩＧＢＴチップ３０１の一方の面に、両櫛歯状の電極面３１１ａ，３１１ｂと短冊形状の電極面３１１ｃを形成してもよい。図１３（ｂ）に示すＩＧＢＴチップ３０１では、半田設定領域３５０が図示するように電極面３１１ａ，３１１ｂの一部を含むようにＩＧＢＴチップ３０１のほぼ中央に設定される。一方の電極面３１１ａに設定される溶融状態の半田は、バスバーが押し当てられると、電極面３１１ａの形状に沿って、すなわち主半田広がり電極面３１１ａ１から副半田広がり電極面３１１ａ２に向かうように＋ｘ方向ならびに＋ｙ方向および－ｙ方向に流れて電極面３１１ａの全体に広がる。同様に、他方の電極面３１１ｂに設定される溶融状態の半田は、バスバーが押し当てられると、電極面３１１ｂの形状に沿って、すなわち主半田広がり電極面３１１ｂ１から副半田広がり電極面３１１ｂ２に向かうように－ｘ方向ならびに＋ｙ方向および－ｙ方向に流れて電極面３１１ｂの全体に広がる。これにより、溶融半田が電極面３１１ａ，３１１ｂから食み出して流れてしまう半田の食み出しが抑制され、さらに、ボイドが低減される。
（３）上述した実施の形態では、図６に示したように１０ｍｍ×１０ｍｍのＩＧＢＴチップにおいて、主半田広がり電極面から延在する帯状電極面を４対設けたが、本発明はこれに限定されない。ＩＧＢＴチップのサイズが大きい場合には、５対以上の帯状電極面を設けてもよい。半導体素子のサイズが小さい場合には２対あるいは３対の帯状電極面を設けることとしてもよい。なお、帯状電極面の数は、ＩＧＢＴチップのサイズに応じて設定される。帯状電極面の形状も平面視矩形状に限定されない。
（４）上述した実施の形態では、半導体素子の電極面のほぼ中央の１カ所に溶融半田を滴下することとしたが、本発明はこれに限定されない。電極面の形状に合わせて、複数カ所に溶融半田を滴下してもよい。たとえば、図１４（ａ）に示すように２対の帯状電極面を有するエミッタ電極面が４つ並設されている場合や、図１４（ｂ）に示すように８対の帯状電極面を有するエミッタ電極面が１つ設けられている場合にも本発明を適用することができる。図１４（ａ）に示すように、主半田広がり電極面の一部を含む半田設定領域４５０ａおよび半田設定領域４５０ｂの２カ所に溶融状態の半田を滴下し押し広げることで、半田が主半田広がり電極面から副半田広がり電極面に向かうように半田設定領域から放射状に流れるため、半田を電極面の全体に広がらせることができる。図１４（ｂ）に示すように、主半田広がり電極面の一部を含む半田設定領域５５０ａおよび半田設定領域５５０ｂの２カ所に溶融状態の半田を滴下し押し広げることで、半田が主半田広がり電極面から副半田広がり電極面に向かうように半田設定領域から放射状に流れるため、半田を電極面の全体に広がらせることができる。半田設定領域の位置や数、面積は、ＩＧＢＴチップの大きさや電極面の数、電極面の形状等に応じて適宜決定される。
（５）本発明に係る半導体装置の電極面は、主半田広がり電極面と、主半田広がり電極面から両側方に櫛状に延在する副半田広がり電極面とを有する様々な形状に形成することができる。電極面の形状の他の例について、図１５（ａ）～（ｃ）を参照して説明する。
　図１５（ａ）に示す電極面６１１ａは、ｘ方向に延在する主半田広がり電極面６１１ａ１と、主半田広がり電極面６１１ａ１から＋ｙ方向に櫛状に延在する副半田広がり電極面６１１ａ２と、主半田広がり電極面６１１ａ１から－ｙ方向に櫛状に延在する副半田広がり電極面６１１ａ３を有している。本変形例では、＋ｙ方向に延在する副半田広がり電極面６１１ａ２は帯状の電極面を４つ有し、－ｙ方向に延在する副半田広がり電極面６１１ａ３は帯状の電極面を３つ有している。
　図１５（ｂ）に示す電極面７１１ａは、ｘ方向に延在する主半田広がり電極面７１１ａ１と、主半田広がり電極面７１１ａ１から＋ｙ方向に櫛状に延在する副半田広がり電極面７１１ａ２と、主半田広がり電極面７１１ａ１から－ｙ方向に櫛状に延在する副半田広がり電極面７１１ａ３とを有している。＋ｙ方向に延在する副半田広がり電極面７１１ａ２は帯状の電極面を４つ有し、－ｙ方向に延在する副半田広がり電極面７１１ａ３は帯状の電極面を６つ有している。本変形例では、副半田広がり電極面７１１ａ２の帯状の電極面のｘ方向の幅と、副半田広がり電極面７１１ａ３の帯状の電極面のｘ方向の幅が異なっている。
　図１５（ｃ）に示す電極面８１１ａは、幅狭の３対の帯状の電極面と、幅広の２対の帯状の電極面とが主半田広がり電極面８１１ａ１から両側方（＋ｙ方向および－ｙ方向）に延在している。
　図１５（ａ）～（ｃ）に示すように、一方向に延在する主半田広がり電極面と、主半田広がり電極面から両側方に櫛状に延在する副半田広がり電極面とを有することで、主半田広がり電極面を含む半田設定領域に配置した溶融状態の半田を電極面全体に広がらせることができる。
（６）本発明によるパワー半導体ユニット３３０の製造方法は、図９に示した場合に限定されない。たとえば、溶融状態の半田６ａ，８ａをＩＧＢＴチップ１およびダイオードチップ２に滴下して、ＩＧＢＴチップ１およびダイオードチップ２を下に配置した状態で第２バスバー４を溶融半田６ａ，８ａに対して上方から押し当てて、第２バスバー４とＩＧＢＴチップ１およびダイオードチップ２とを半田６，８により接合し、第２バスバー組み３０を形成する。その後、第２バスバー組み３０を裏返して配置し、溶融状態の半田５ａ，７ａをＩＧＢＴチップ１およびダイオードチップ２に滴下して、第２バスバー組み３０を下に配置した状態で第１バスバー３を溶融半田５ａ，７ａに対して上方から押し当てて、第１バスバー３とＩＧＢＴチップ１およびダイオードチップ２とを半田５，７により接合してもよい。
（７）本発明はＩＧＢＴチップ１とダイオードチップ２とを第２バスバー４に同時に近づけて一括して接合する場合に限定されることもない。第２バスバー４とＩＧＢＴチップ１およびダイオードチップ２との接合と、第１バスバー３とＩＧＢＴチップ１およびダイオードチップ２との接合は逆の順序であってもよい。
（８）上述した実施の形態では、溶融した半田を滴下して、半導体素子の電極面とバスバーとを半田により接合する滴下法を採用したが、本発明はこれに限定されない。クリーム半田を半田設定領域に配置させた後、加熱炉などに入れて半田をリフローさせる方法を採用してもよい。
　この方法を採用した場合の工程について説明する。第１工程では、両櫛歯状の電極面を一方の面に少なくとも１つ有する半導体素子と、第１導体部材と、第２導体部材とを準備する。第２工程では、半田により半導体素子の他方の面に設けられる電極面を第２導体部材に接合する。第３工程では、半導体素子の両櫛歯状の電極面を構成する主半田広がり電極面の一部を含む所定領域、たとえば図１０の半田設定領域５０、または、その所定領域に対向する第１導体部材における領域にクリーム半田を設置する。
　第４工程では、クリーム半田を加熱して溶融させ、第１導体部材と半導体素子の一方の面に設けられる電極面との距離を近づけることで溶融状態の半田を主半田広がり電極面から副半田広がり電極面に広がらせて、半田により半導体素子の一方の面に設けられる電極面を第１導体部材に接合する。第５工程では、第１導体部材と第２導体部材とを封止部材により封止する。
　このように、クリーム半田を所定領域に設定した後、半田を加熱して溶融させ、導体部材と半導体素子の電極面とを近づけることで、溶融した半田を電極面に広がらせることができる。
（９）上述した実施の形態では、スイッチング半導体素子としてＩＧＢＴを採用したが、必要な周波数や電圧によって、金属酸化物半導体型電界効果トランジスタ（ＭＯＳＦＥＴ）などの他の半導体素子を採用してもよい。スイッチング半導体素子としては、ＩＧＢＴは直流電圧が比較的高い場合に適していて、ＭＯＳＦＥＴは直流電圧が比較的低い場合に適している。
（１０）上述した実施の形態では、エミッタ電極の電極面を両櫛歯状としたが、本発明はこれに限定されない。半導体素子の一方の面に設けられる電極面の少なくとも１つが、両櫛歯状とされていればよい。
（１１）上述した実施の形態では、ハイブリッド型の電気自動車や純粋な電気自動車に搭載される電力変換装置に組み込まれる半導体装置について説明したが本発明はこれに限定されない。他の電動車両、たとえばハイブリッド電車などの鉄道車両、バスなどの乗合自動車、トラックなどの貨物自動車、バッテリ式フォークリフトトラックなどの産業車両などの車両用電源装置に利用可能な電力変換装置に搭載する半導体装置に本発明を適用してもよい。
　上記では、種々の実施の形態および変形例を説明したが、本発明はこれらの内容に限定されるものではない。本発明の技術的思想の範囲内で考えられるその他の態様も本発明の範囲内に含まれる。
　次の優先権基礎出願の開示内容は引用文としてここに組み込まれる。
　日本国特許出願２０１１年第１４４５９３号（２０１１年６月２９日出願）

Claims (11)

  1. 　半導体装置であって、
    　両面のそれぞれに少なくとも１つの電極面を有する半導体素子と、
    　前記半導体素子の一方の面に設けられる電極面に半田により接合される第１導体部材と、
    　前記半導体素子の他方の面に設けられる電極面に半田により接合される第２導体部材とを備え、
    　前記半導体素子の一方の面に設けられる電極面の少なくとも１つが両櫛歯状とされている半導体装置。
  2. 　請求項１に記載の半導体装置において、
    　前記両櫛歯状の電極面は、主半田広がり電極面と、前記主半田広がり電極面から両側方に櫛状に延在する副半田広がり電極面とを有している半導体装置。
  3. 　請求項１または２に記載の半導体装置において、
    　前記両櫛歯状の電極面の周縁にはゲート配線が配設され、
    　前記ゲート配線は、前記両櫛歯状の電極面に比べて半田の濡れ性が低く、かつ、絶縁性を有する保護膜によって覆われている半導体装置。
  4. 　請求項１ないし３のいずれか１項に記載の半導体装置において、
    　前記第１導体部材および前記第２導体部材は銅材からなり、前記第１導体部材および前記第２導体部材における前記半田との接合面には表面加工が施されていない半導体装置。
  5. 　半導体装置であって、
    　ＩＧＢＴチップおよびダイオードチップと、
    　ＩＧＢＴチップの一方の面に少なくとも１つ設けられるエミッタ電極面およびダイオードチップの一方の面に設けられるアノード電極面に半田により接合される第１導体板と、
    　ＩＧＢＴチップの他方の面に設けられるコレクタ電極面およびダイオードチップの他方の面に設けられるカソード電極面に半田により接合される第２導体板とを備え、
    　前記ＩＧＢＴチップの一方の面に設けられるエミッタ電極面の少なくとも１つは両櫛歯状とされ、
    　前記両櫛歯状の電極面は、主半田広がり電極面と、前記主半田広がり電極面から両側方に櫛状に延在する副半田広がり電極面とを有し、
    　前記エミッタ電極面の周縁にはゲート配線が配設され、
    　前記ゲート配線は、前記エミッタ電極面に比べて半田の濡れ性が低く、かつ、絶縁性を有する保護膜によって覆われている半導体装置。
  6. 　半導体装置であって、
    　インバータ回路の上下アームを構成する上アーム用ＩＧＢＴチップおよび上アーム用ダイオードチップならびに下アーム用ＩＧＢＴチップおよび下アーム用ダイオードチップと、
    　前記上アーム用ＩＧＢＴチップの一方の面に少なくとも１つ設けられるエミッタ電極面および上アーム用ダイオードチップの一方の面に設けられるアノード電極面に半田により接合される第２交流電極リードフレームと、
    　前記上アーム用ＩＧＢＴチップの他方の面に設けられるコレクタ電極面および上アーム用ダイオードチップの他方の面に設けられるカソード電極面に半田により接合される直流正極電極リードフレームと、
    　前記下アーム用ＩＧＢＴチップの一方の面に少なくとも１つ設けられるエミッタ電極面および下アーム用ダイオードチップの一方の面に設けられるアノード電極面に半田により接合される直流負極電極リードフレームと、
    　前記下アーム用ＩＧＢＴチップの他方の面に設けられるコレクタ電極面および下アーム用ダイオードチップの他方の面に設けられるカソード電極面に半田により接合される第１交流電極リードフレームとを備え、
    　前記上アーム用ＩＧＢＴチップおよび前記下アーム用ＩＧＢＴチップの一方の面のそれぞれに設けられるエミッタ電極面の少なくとも１つは両櫛歯状とされ、
    　前記両櫛歯状の電極面は、主半田広がり電極面と、前記主半田広がり電極面から両側方に櫛状に延在する副半田広がり電極面とを有し、
    　前記エミッタ電極面の周縁にはゲート配線が配設され、
    　前記ゲート配線は、前記エミッタ電極面に比べて半田の濡れ性が低く、かつ、絶縁性を有する保護膜によって覆われている半導体装置。
  7. 　請求項１ないし６のいずれか１項に記載の半導体装置において、
    　前記両櫛歯状の電極面には、半田の濡れ性を向上させるニッケルめっきが施されている半導体装置。
  8. 　請求項２ないし４のいずれか１項に記載の半導体装置を製造する方法であって、
    　前記両櫛歯状の電極面を少なくとも１つ有する半導体素子と、前記第１導体部材と、前記第２導体部材とを準備する工程と、
    　半田により前記半導体素子の他方の面に設けられる電極面を前記第２導体部材に接合する工程と、
    　前記半導体素子の両櫛歯状の電極面を構成する前記主半田広がり電極面の一部を含む所定領域、または、前記第１導体部材における前記所定領域に対向する領域に溶融状態の半田を滴下する工程と、
    　前記第１導体部材と前記半導体素子の一方の面に設けられる電極面との距離を近づけることで前記溶融状態の半田を前記主半田広がり電極面から前記副半田広がり電極面に広がらせて、半田により前記半導体素子の一方の面に設けられる電極面を前記第１導体部材に接合する工程と、
    　前記第１導体部材と前記第２導体部材とを封止部材により封止する工程とを含む半導体装置の製造方法。
  9. 　請求項２ないし４のいずれか１項に記載の半導体装置を製造する方法であって、
    　前記両櫛歯状の電極面を少なくとも１つ有する半導体素子と、前記第１導体部材と、前記第２導体部材とを準備する工程と、
    　半田により前記半導体素子の他方の面に設けられる電極面を前記第２導体部材に接合する工程と、
    　前記第１導体部材の滴下領域に溶融状態の半田を滴下する工程と、
    　前記滴下領域に滴下された半田が前記半導体素子の一方の面に設けられた両櫛歯状の電極面を構成する前記主半田広がり電極面の一部を含む所定領域に対向して配置されるように位置決めする工程と、
    　前記第１導体部材に前記半導体素子の一方の面を近づけ、前記溶融状態の半田を前記主半田広がり電極面から前記副半田広がり電極面に広がらせて、半田により前記半導体素子の一方の面に設けられる電極面を前記第１導体部材に接合する工程と、
    　前記第１導体部材と前記第２導体部材とを封止部材により封止する工程とを含む半導体装置の製造方法。
  10. 　請求項５に記載の半導体装置を製造する方法であって、
    　前記両櫛歯状のエミッタ電極面を少なくとも１つ有するＩＧＢＴチップと、前記ダイオードチップと、前記第１導体板と、前記第２導体板とを準備する工程と、
    　前記ＩＧＢＴチップのコレクタ電極面および前記ダイオードチップのカソード電極面のそれぞれの中央位置、または、前記それぞれの中央位置に対向する第２導体板の所定位置に溶融状態の半田を滴下する工程と、
    　前記第２導体板に前記ＩＧＢＴチップのコレクタ電極面および前記ダイオードチップのカソード電極面を同時に近づけ、前記溶融状態の半田を前記コレクタ電極面および前記カソード電極面に広がらせて、半田により前記ＩＧＢＴチップのコレクタ電極面および前記ダイオードチップのカソード電極面のそれぞれを前記第２導体板に接合する工程と、
    　前記ＩＧＢＴチップのエミッタ電極面を構成する前記主半田広がり電極面の一部を含む所定領域および前記ダイオードチップのアノード電極面の中央位置、または、前記所定領域および前記アノード電極面の中央位置に対向する第１導体板の所定位置に溶融状態の半田を滴下する工程と、
    　前記第１導体板に前記ＩＧＢＴチップのエミッタ電極面および前記ダイオードチップのアノード電極面を同時に近づけ、前記溶融状態の半田を前記エミッタ電極面における前記主半田広がり電極面から前記副半田広がり電極面に広がらせるとともに、前記溶融状態の半田を前記アノード電極面に広がらせて、半田により前記ＩＧＢＴチップのエミッタ電極面および前記ダイオードチップのアノード電極面のそれぞれを前記第１導体板に接合する工程と、
    　前記第１導体板と前記第２導体板とを封止部材により封止する工程とを含む半導体装置の製造方法。
  11. 　請求項２ないし４のいずれか１項に記載の半導体装置を製造する方法であって、
    　前記両櫛歯状の電極面を少なくとも１つ有する半導体素子と、前記第１導体部材と、前記第２導体部材とを準備する工程と、
    　半田により前記半導体素子の他方の面に設けられる電極面を前記第２導体部材に接合する工程と、
    　前記半導体素子の両櫛歯状の電極面を構成する前記主半田広がり電極面の一部を含む所定領域、または、前記第１導体部材における前記所定領域に対向する領域に半田を設置する工程と、
    　前記半田を加熱して溶融させ、前記第１導体部材と前記半導体素子の一方の面に設けられる電極面との距離を近づけることで前記溶融状態の半田を前記主半田広がり電極面から前記副半田広がり電極面に広がらせて、半田により前記半導体素子の一方の面に設けられる電極面を前記第１導体部材に接合する工程と、
    　前記第１導体部材と前記第２導体部材とを封止部材により封止する工程とを含む半導体装置の製造方法。
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US9306020B2 (en) 2016-04-05
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US20140110752A1 (en) 2014-04-24
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