JP2007536581A - プロセス変動バンドを用いた集積回路レイアウト設計法 - Google Patents

プロセス変動バンドを用いた集積回路レイアウト設計法 Download PDF

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Publication number
JP2007536581A
JP2007536581A JP2007511692A JP2007511692A JP2007536581A JP 2007536581 A JP2007536581 A JP 2007536581A JP 2007511692 A JP2007511692 A JP 2007511692A JP 2007511692 A JP2007511692 A JP 2007511692A JP 2007536581 A JP2007536581 A JP 2007536581A
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layout
design
band
variation
objects
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Japanese (ja)
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ロブレス， ファン エー． トレス
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メンター・グラフィクス・コーポレーション
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/04—Constraint-based CAD
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/08—Probabilistic or stochastic CAD
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/80—Technologies aiming to reduce greenhouse gasses emissions common to all road transportation technologies
    • Y02T10/82—Elements for improving aerodynamics

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2007511692A 2004-05-07 2005-05-06 プロセス変動バンドを用いた集積回路レイアウト設計法 Pending JP2007536581A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US56884904P 2004-05-07 2004-05-07
US65583705P 2005-02-23 2005-02-23
PCT/US2005/016115 WO2005111874A2 (en) 2004-05-07 2005-05-06 Integrated circuit layout design methodology with process variation bands

Related Child Applications (1)

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JP2010261858A Division JP5706675B2 (ja) 2004-05-07 2010-11-24 プロセス変動バンドを用いた集積回路レイアウト設計法

Publications (1)

Publication Number Publication Date
JP2007536581A true JP2007536581A (ja) 2007-12-13

Family

ID=35385625

Family Applications (5)

Application Number Title Priority Date Filing Date
JP2007511692A Pending JP2007536581A (ja) 2004-05-07 2005-05-06 プロセス変動バンドを用いた集積回路レイアウト設計法
JP2010261858A Expired - Lifetime JP5706675B2 (ja) 2004-05-07 2010-11-24 プロセス変動バンドを用いた集積回路レイアウト設計法
JP2015000081A Expired - Lifetime JP6069369B2 (ja) 2004-05-07 2015-01-05 プロセス変動バンドを用いた集積回路レイアウト設計法
JP2016147134A Expired - Lifetime JP6377106B2 (ja) 2004-05-07 2016-07-27 プロセス変動バンドを用いた集積回路レイアウト設計法
JP2018011369A Pending JP2018106728A (ja) 2004-05-07 2018-01-26 プロセス変動バンドを用いた集積回路レイアウト設計法

Family Applications After (4)

Application Number Title Priority Date Filing Date
JP2010261858A Expired - Lifetime JP5706675B2 (ja) 2004-05-07 2010-11-24 プロセス変動バンドを用いた集積回路レイアウト設計法
JP2015000081A Expired - Lifetime JP6069369B2 (ja) 2004-05-07 2015-01-05 プロセス変動バンドを用いた集積回路レイアウト設計法
JP2016147134A Expired - Lifetime JP6377106B2 (ja) 2004-05-07 2016-07-27 プロセス変動バンドを用いた集積回路レイアウト設計法
JP2018011369A Pending JP2018106728A (ja) 2004-05-07 2018-01-26 プロセス変動バンドを用いた集積回路レイアウト設計法

Country Status (5)

Country Link
US (4) US8799830B2 (enExample)
EP (1) EP1747520B1 (enExample)
JP (5) JP2007536581A (enExample)
TW (1) TW200604870A (enExample)
WO (1) WO2005111874A2 (enExample)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009141352A (ja) * 2007-12-05 2009-06-25 Brion Technologies Inc リソグラフィプロセスウィンドウをシミュレートするための方法及びシステム
JP2010026076A (ja) * 2008-07-16 2010-02-04 Renesas Technology Corp リソグラフィシミュレーション装置、ならびにリソグラフィシミュレーションプログラムおよびそれを使用した半導体装置設計製造方法
JP4755655B2 (ja) * 2005-01-21 2011-08-24 インターナショナル・ビジネス・マシーンズ・コーポレーション 差分交互位相シフト・マスクの最適化
JP2012511168A (ja) * 2008-12-05 2012-05-17 マイクロニック マイデータ アーベー マイクロリソグラフ印刷における勾配を援用した画像再サンプリング
JP2013507773A (ja) * 2009-10-07 2013-03-04 クアルコム，インコーポレイテッド チップ識別構造体を有する垂直積層可能なダイ
US9411647B2 (en) 2010-01-22 2016-08-09 Qualcomm Incorporated Hierarchical routing and interface selection for multi-processor multimode network devices
US20220128899A1 (en) * 2020-10-22 2022-04-28 D2S, Inc. Methods and systems to determine shapes for semiconductor or flat panel display fabrication
US12387029B2 (en) 2021-07-23 2025-08-12 D2S, Inc. Computing parasitic values for semiconductor designs
US12475283B2 (en) 2022-01-19 2025-11-18 D2S, Inc. Generating and display an animation of a predicted overlap shape in an IC design
US12499301B2 (en) 2022-08-16 2025-12-16 D2S, Inc. Computing parasitic values for semiconductor designs

Families Citing this family (202)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7293249B2 (en) * 2002-01-31 2007-11-06 Juan Andres Torres Robles Contrast based resolution enhancement for photolithographic processing
US6931613B2 (en) * 2002-06-24 2005-08-16 Thomas H. Kauth Hierarchical feature extraction for electrical interaction calculations
WO2004034463A1 (ja) * 2002-10-10 2004-04-22 Fujitsu Limited レイアウト方法及び装置並びにそのプログラム及び記録媒体
EP1467294A3 (en) * 2003-04-04 2005-06-01 Interuniversitair Microelektronica Centrum Vzw Design method for electronic systems using library of hardware components with performance parameters and cost functions
US7698665B2 (en) 2003-04-06 2010-04-13 Luminescent Technologies, Inc. Systems, masks, and methods for manufacturable masks using a functional representation of polygon pattern
US7124394B1 (en) * 2003-04-06 2006-10-17 Luminescent Technologies, Inc. Method for time-evolving rectilinear contours representing photo masks
EP1747520B1 (en) 2004-05-07 2018-10-24 Mentor Graphics Corporation Integrated circuit layout design methodology with process variation bands
US7240305B2 (en) 2004-06-02 2007-07-03 Lippincott George P OPC conflict identification and edge priority system
US7689951B2 (en) * 2004-08-31 2010-03-30 Freescale Semiconductor, Inc. Design rule checking system and method, for checking compliance of an integrated circuit design with a plurality of design rules
US7302651B2 (en) * 2004-10-29 2007-11-27 International Business Machines Corporation Technology migration for integrated circuits with radical design restrictions
US7269818B2 (en) * 2005-01-06 2007-09-11 International Business Machines Corporation Circuit element function matching despite auto-generated dummy shapes
US20060242618A1 (en) * 2005-02-14 2006-10-26 Yao-Ting Wang Lithographic simulations using graphical processing units
US8037429B2 (en) * 2005-03-02 2011-10-11 Mentor Graphics Corporation Model-based SRAF insertion
US20060199087A1 (en) * 2005-03-03 2006-09-07 Lucas Kevin D Method of making an integrated circuit by modifying a design layout by accounting for a parameter that varies based on a location within an exposure field
EP1889195A4 (en) 2005-05-20 2012-09-12 Cadence Desing Systems Inc PRODUCTION-DESIGN DESIGN AND DESIGNED PRODUCTION
US7395516B2 (en) * 2005-05-20 2008-07-01 Cadence Design Systems, Inc. Manufacturing aware design and design aware manufacturing
US7458058B2 (en) * 2005-06-10 2008-11-25 Texas Instruments Incorporated Verifying a process margin of a mask pattern using intermediate stage models
US7797668B2 (en) * 2005-06-30 2010-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method for optimally converting a circuit design into a semiconductor device
US8219940B2 (en) * 2005-07-06 2012-07-10 Semiconductor Insights Inc. Method and apparatus for removing dummy features from a data structure
DE102005036207A1 (de) * 2005-08-02 2007-02-22 X-Fab Semiconductor Foundries Ag Verfahren zum Entwurf von integrierten Schaltungen
US7568174B2 (en) * 2005-08-19 2009-07-28 Cadence Design Systems, Inc. Method for checking printability of a lithography target
WO2007041602A2 (en) * 2005-10-03 2007-04-12 Luminescent Technologies, Inc. Lithography verification using guard bands
WO2007041600A2 (en) 2005-10-03 2007-04-12 Luminescent Technologies, Inc. Mask-pattern determination using topology types
WO2007041701A2 (en) 2005-10-04 2007-04-12 Luminescent Technologies, Inc. Mask-patterns including intentional breaks
WO2007044557A2 (en) 2005-10-06 2007-04-19 Luminescent Technologies, Inc. System, masks, and methods for photomasks optimized with approximate and accurate merit functions
US7266798B2 (en) * 2005-10-12 2007-09-04 International Business Machines Corporation Designer's intent tolerance bands for proximity correction and checking
TWI463344B (zh) * 2005-10-24 2014-12-01 Cadence Design Systems Inc 積體電路時序、雜訊、及功率分析技術
US7503028B2 (en) * 2006-01-10 2009-03-10 International Business Machines Corporation Multilayer OPC for design aware manufacturing
US7921383B1 (en) * 2006-01-11 2011-04-05 Olambda, Inc Photolithographic process simulation including efficient result computation for multiple process variation values
US7640522B2 (en) * 2006-01-14 2009-12-29 Tela Innovations, Inc. Method and system for placing layout objects in a standard-cell layout
KR100706813B1 (ko) * 2006-02-13 2007-04-12 삼성전자주식회사 반도체 장치의 패턴 배치 방법
WO2007100558A2 (en) * 2006-02-17 2007-09-07 Mentor Graphics Corporation Modeling for semiconductor fabrication process effects
US7712068B2 (en) 2006-02-17 2010-05-04 Zhuoxiang Ren Computation of electrical properties of an IC layout
US8015510B2 (en) * 2006-02-17 2011-09-06 Mentor Graphics Corporation Interconnection modeling for semiconductor fabrication process effects
US8245180B2 (en) * 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7932545B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US7943967B2 (en) 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8214778B2 (en) 2007-08-02 2012-07-03 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8300798B1 (en) 2006-04-03 2012-10-30 Wai Wu Intelligent communication routing system and method
US7487476B2 (en) * 2006-04-11 2009-02-03 International Business Machines Corporation Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool
US8136067B2 (en) * 2006-05-15 2012-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of design for manufacturing
US7754400B2 (en) 2006-05-26 2010-07-13 Sony Corporation Method for determining an acceptable reticle tolerance for a reticle used to produce an integrated circuit layout
US7503020B2 (en) * 2006-06-19 2009-03-10 International Business Machines Corporation IC layout optimization to improve yield
US8448096B1 (en) * 2006-06-30 2013-05-21 Cadence Design Systems, Inc. Method and system for parallel processing of IC design layouts
US7493590B1 (en) * 2006-07-11 2009-02-17 Kla-Tencor Technologies Corporation Process window optical proximity correction
JP4256408B2 (ja) * 2006-07-20 2009-04-22 株式会社東芝 不良確率の算出方法、パターン作成方法及び半導体装置の製造方法
JP4762827B2 (ja) * 2006-08-22 2011-08-31 富士フイルム株式会社 電子アルバム生成装置、電子アルバム生成方法、および、そのプログラム
US20080168410A1 (en) 2006-10-09 2008-07-10 Mentor Graphics Corporation Properties In Electronic Design Automation
US7770142B1 (en) * 2006-10-30 2010-08-03 Cadence Design Systems, Inc. Modeling power management for an integrated circuit
US8056022B2 (en) 2006-11-09 2011-11-08 Mentor Graphics Corporation Analysis optimizer
US7966585B2 (en) 2006-12-13 2011-06-21 Mentor Graphics Corporation Selective shielding for multiple exposure masks
US20090281778A1 (en) * 2006-12-21 2009-11-12 Nxp, B.V. Method and system for identifying weak points in an integrated circuit design
US7827519B2 (en) 2006-12-29 2010-11-02 Cadence Design Systems, Inc. Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs
US7962866B2 (en) 2006-12-29 2011-06-14 Cadence Design Systems, Inc. Method, system, and computer program product for determining three-dimensional feature characteristics in electronic designs
US7721237B2 (en) * 2006-12-29 2010-05-18 Cadence Design Systems, Inc. Method, system, and computer program product for timing closure in electronic designs
US8798966B1 (en) * 2007-01-03 2014-08-05 Kla-Tencor Corporation Measuring critical dimensions of a semiconductor structure
WO2008081227A1 (en) * 2007-01-05 2008-07-10 Freescale Semiconductor, Inc. Method and apparatus for designing an integrated circuit
US7802226B2 (en) * 2007-01-08 2010-09-21 Mentor Graphics Corporation Data preparation for multiple mask printing
US7799487B2 (en) 2007-02-09 2010-09-21 Ayman Yehia Hamouda Dual metric OPC
US7739650B2 (en) 2007-02-09 2010-06-15 Juan Andres Torres Robles Pre-bias optical proximity correction
US7979829B2 (en) 2007-02-20 2011-07-12 Tela Innovations, Inc. Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US7689948B1 (en) 2007-02-24 2010-03-30 Cadence Design Systems, Inc. System and method for model-based scoring and yield prediction
US7707528B1 (en) * 2007-02-24 2010-04-27 Cadence Design Systems, Inc. System and method for performing verification based upon both rules and models
US7725845B1 (en) 2007-02-24 2010-05-25 Cadence Design Systems, Inc. System and method for layout optimization using model-based verification
US7574682B2 (en) 2007-02-28 2009-08-11 Freescale Semiconductor, Inc. Yield analysis and improvement using electrical sensitivity extraction
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
JP2008258361A (ja) * 2007-04-04 2008-10-23 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
EP2153376B1 (en) * 2007-05-23 2011-10-19 Nxp B.V. Process-window aware detection and correction of lithographic printing issues at mask level
US8713483B2 (en) 2007-06-05 2014-04-29 Mentor Graphics Corporation IC layout parsing for multiple masks
US8122392B2 (en) * 2007-06-27 2012-02-21 Cadence Design Systems, Inc. Robust design using manufacturability models
US8645896B1 (en) * 2007-06-28 2014-02-04 Dcg Systems Inc Method to transfer failure analysis-specific data between design houses and fab's/FA labs
US7647569B2 (en) * 2007-08-01 2010-01-12 Micron Technology, Inc. Systems, methods, and computer-readable media for adjusting layout database hierarchies for more efficient database processing and storage
US7805699B2 (en) * 2007-10-11 2010-09-28 Mentor Graphics Corporation Shape-based photolithographic model calibration
US7966586B2 (en) * 2007-12-07 2011-06-21 Cadence Design Systems, Inc. Intelligent pattern signature based on lithography effects
US7904853B1 (en) 2007-12-27 2011-03-08 Cadence Design Systems, Inc. Pattern signature
US8358828B2 (en) * 2007-12-28 2013-01-22 Cadence Design Systems, Inc. Interpolation of irregular data in a finite-dimensional metric space in lithographic simulation
US7979815B2 (en) * 2008-01-08 2011-07-12 International Business Machines Corporation Compact model methodology for PC landing pad lithographic rounding impact on device performance
US8296691B2 (en) * 2008-01-08 2012-10-23 International Business Machines Corporation Methodology for improving device performance prediction from effects of active area corner rounding
US7984395B2 (en) * 2008-01-17 2011-07-19 Synopsys, Inc. Hierarchical compression for metal one logic layer
US20090187867A1 (en) * 2008-01-22 2009-07-23 Lawrence Jay A Techniques for Verifying Error Detection of a Design Rule Checking Runset
US7861195B2 (en) * 2008-01-30 2010-12-28 Advanced Mirco Devices, Inc. Process for design of semiconductor circuits
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8381152B2 (en) 2008-06-05 2013-02-19 Cadence Design Systems, Inc. Method and system for model-based design and layout of an integrated circuit
US7761178B2 (en) * 2008-06-18 2010-07-20 Tokyo Electron Limited Automated process control using an optical metrology system optimized with design goals
US8060843B2 (en) * 2008-06-18 2011-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Verification of 3D integrated circuits
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US7992114B1 (en) * 2008-08-19 2011-08-02 Magma Design Automation, Inc. Timing analysis using statistical on-chip variation
US8136062B2 (en) 2008-08-28 2012-03-13 International Business Machines Corporation Hierarchy reassembler for 1×N VLSI design
US8132134B2 (en) 2008-08-28 2012-03-06 International Business Machines Corporation Closed-loop 1×N VLSI design system
US8122399B2 (en) 2008-08-28 2012-02-21 International Business Machines Corporation Compiler for closed-loop 1×N VLSI design
US8156458B2 (en) * 2008-08-29 2012-04-10 International Business Machines Corporation Uniquification and parent-child constructs for 1xN VLSI design
US7966598B2 (en) * 2008-08-29 2011-06-21 International Business Machines Corporation Top level hierarchy wiring via 1×N compiler
US8141016B2 (en) * 2008-08-29 2012-03-20 International Business Machines Corporation Integrated design for manufacturing for 1×N VLSI design
US8146023B1 (en) * 2008-10-02 2012-03-27 Kla-Tenor Corporation Integrated circuit fabrication process convergence
US8051401B2 (en) * 2008-10-15 2011-11-01 Arm Limited Post-routing power supply modification for an integrated circuit
US20100107130A1 (en) * 2008-10-23 2010-04-29 International Business Machines Corporation 1xn block builder for 1xn vlsi design
JP2010160787A (ja) * 2008-12-11 2010-07-22 Jedat Inc パラメータ情報作成システム、歩留まり算出システム、プログラム及び記録媒体
US8032848B2 (en) * 2009-01-29 2011-10-04 Synopsys, Inc. Performing abstraction-refinement using a lower-bound-distance to verify the functionality of a circuit design
US20110145772A1 (en) * 2009-05-14 2011-06-16 Pikus Fedor G Modular Platform For Integrated Circuit Design Analysis And Verification
WO2011017552A1 (en) * 2009-08-05 2011-02-10 Kovio, Inc. Print compatible designs and layout schemes for printed electronics
JP5293488B2 (ja) * 2009-08-05 2013-09-18 富士通セミコンダクター株式会社 設計支援プログラム、設計支援装置、および設計支援方法
US8367430B2 (en) * 2009-10-07 2013-02-05 GlobalFoundries, Inc. Shape characterization with elliptic fourier descriptor for contact or any closed structures on the chip
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8448110B2 (en) * 2009-11-24 2013-05-21 International Business Machines Corporation Method to reduce delay variation by sensitivity cancellation
TWI464433B (zh) * 2009-11-25 2014-12-11 Hon Hai Prec Ind Co Ltd 印刷電路板信號線分類排查系統及方法
US8551283B2 (en) 2010-02-02 2013-10-08 Apple Inc. Offset control for assembling an electronic device housing
US20120011480A1 (en) * 2010-05-25 2012-01-12 Sridhar Srinivasan Logic-Driven Layout Verification
US8594963B2 (en) * 2010-09-01 2013-11-26 Macronix International Co., Ltd. In-line inspection yield prediction system
US8438526B2 (en) * 2010-09-23 2013-05-07 Texas Instruments Incorporated Method for minimizing transistor and analog component variation in CMOS processes through design rule restrictions
US20120110531A1 (en) * 2010-10-28 2012-05-03 Qualcomm Incorporated Defect and yield prediction for segments of an integrated circuit
US8381141B2 (en) * 2010-10-28 2013-02-19 International Business Machines Corporation Method and system for comparing lithographic processing conditions and or data preparation processes
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8677297B2 (en) 2010-12-03 2014-03-18 Synopsys, Inc. Low-overhead multi-patterning design rule check
US8448097B2 (en) * 2010-12-03 2013-05-21 Synopsys, Inc. High performance DRC checking algorithm for derived layer based rules
US8352887B2 (en) 2010-12-03 2013-01-08 Synopsys, Inc. High performance design rule checking technique
US8453103B2 (en) 2010-12-03 2013-05-28 Synopsys, Inc. Real time DRC assistance for manual layout editing
US8448120B2 (en) * 2011-05-09 2013-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. RC extraction for single patterning spacer technique
US8832621B1 (en) 2011-11-28 2014-09-09 Cadence Design Systems, Inc. Topology design using squish patterns
US8589844B2 (en) * 2012-02-09 2013-11-19 GlobalFoundries, Inc. Methods for analyzing design rules
US8806391B2 (en) 2012-07-31 2014-08-12 United Microelectronics Corp. Method of optical proximity correction according to complexity of mask pattern
US9158883B2 (en) 2012-08-08 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. System for designing a semiconductor device, device made, and method of using the system
US8584066B1 (en) * 2012-09-04 2013-11-12 GlobalFoundries, Inc. System and method for generating a wire model
US8739076B2 (en) * 2012-09-11 2014-05-27 Synopsys, Inc. Method and apparatus for process window modeling
US9330223B2 (en) 2012-09-28 2016-05-03 International Business Machines Corporation Optical rule checking for detecting at risk structures for overlay issues
US9171112B2 (en) 2012-12-07 2015-10-27 Synopsys, Inc. Semiconductor hold time fixing
US8975195B2 (en) * 2013-02-01 2015-03-10 GlobalFoundries, Inc. Methods for optical proximity correction in the design and fabrication of integrated circuits
US9122160B2 (en) * 2013-03-15 2015-09-01 Globalfoundries Singapore Pte. Ltd. Method and apparatus for performing optical proximity and photomask correction
US9081919B2 (en) * 2013-03-15 2015-07-14 Globalfoundries Singapore Pte. Ltd. Design-for-manufacturing—design-enabled-manufacturing (DFM-DEM) proactive integrated manufacturing flow
WO2014204577A1 (en) * 2013-06-21 2014-12-24 California Institute Of Technology Determination of electronic circuit robustness
US9064078B2 (en) * 2013-07-30 2015-06-23 Globalfoundries Inc. Methods and systems for designing and manufacturing optical lithography masks
WO2015058147A1 (en) 2013-10-17 2015-04-23 Plethora Corporation Method for quoting part production
EP3058496A4 (en) * 2013-10-17 2017-07-12 Plethora Corporation Method for implementing design-for-manufacturability checks
US9286431B2 (en) * 2013-10-31 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Oxide definition (OD) gradient reduced semiconductor device and method of making
KR102175464B1 (ko) 2014-04-08 2020-11-06 삼성전자주식회사 반도체 집적 회로
US10185799B2 (en) 2014-04-22 2019-01-22 Mentor Graphics Corporation Verification of photonic integrated circuits
US9311442B2 (en) * 2014-04-25 2016-04-12 Globalfoundries Inc. Net-voltage-aware optical proximity correction (OPC)
US9311443B2 (en) * 2014-06-17 2016-04-12 Globalfoundries Inc. Correcting for stress induced pattern shifts in semiconductor manufacturing
US10310386B2 (en) 2014-07-14 2019-06-04 Asml Netherlands B.V. Optimization of assist features and source
US10444734B2 (en) 2014-08-22 2019-10-15 Mentor Graphics Corporation Manufacture of non-rectilinear features
US9740092B2 (en) * 2014-08-25 2017-08-22 Globalfoundries Inc. Model-based generation of dummy features
US10387596B2 (en) 2014-08-26 2019-08-20 International Business Machines Corporation Multi-dimension variable predictive modeling for yield analysis acceleration
US10452793B2 (en) * 2014-08-26 2019-10-22 International Business Machines Corporation Multi-dimension variable predictive modeling for analysis acceleration
CN107111237B (zh) 2014-10-02 2020-02-28 Asml荷兰有限公司 辅助特征的基于规则的部署
US9659123B2 (en) 2014-10-17 2017-05-23 21, Inc. Systems and methods for flexibly optimizing processing circuit efficiency
US20160112200A1 (en) 2014-10-17 2016-04-21 21, Inc. Cryptographic hashing circuitry having improved scheduling efficiency
US9594867B2 (en) * 2014-10-30 2017-03-14 Synopsys, Inc. DRC-based hotspot detection considering edge tolerance and incomplete specification
US9466604B2 (en) * 2014-11-13 2016-10-11 Globalfoundries Inc. Metal segments as landing pads and local interconnects in an IC device
US9378315B1 (en) * 2014-12-11 2016-06-28 Excelio Technology (Shenzhen) Co., Ltd. Method for semiconductor process corner sweep simulation based on value selection function
KR20160078032A (ko) * 2014-12-24 2016-07-04 삼성전자주식회사 전자 설계 자동화를 위한 장치 및 방법
US10699971B2 (en) * 2015-08-17 2020-06-30 Qoniac Gmbh Method for processing of a further layer on a semiconductor wafer
US10008422B2 (en) * 2015-08-17 2018-06-26 Qoniac Gmbh Method for assessing the usability of an exposed and developed semiconductor wafer
US9721054B2 (en) * 2015-12-11 2017-08-01 International Business Machines Corporation Building a corner model of interconnect wire resistance
US10083272B2 (en) * 2016-08-12 2018-09-25 International Business Machines Corporation Integrated circuit design layout optimizer based on process variation and failure mechanism
CN106611088B (zh) * 2016-12-28 2019-10-08 北京华大九天软件有限公司 一种库单元时延功耗状态完整性的检查方法
US11086229B2 (en) 2017-05-05 2021-08-10 Asml Netherlands B.V. Method to predict yield of a device manufacturing process
US10402524B2 (en) * 2017-05-08 2019-09-03 Globalfoundries Inc. Prediction of process-sensitive geometries with machine learning
US10394116B2 (en) 2017-09-06 2019-08-27 International Business Machines Corporation Semiconductor fabrication design rule loophole checking for design for manufacturability optimization
US10628544B2 (en) 2017-09-25 2020-04-21 International Business Machines Corporation Optimizing integrated circuit designs based on interactions between multiple integration design rules
US10599805B2 (en) 2017-12-01 2020-03-24 International Business Machines Corporation Superconducting quantum circuits layout design verification
US10592814B2 (en) 2017-12-01 2020-03-17 International Business Machines Corporation Automatic design flow from schematic to layout for superconducting multi-qubit systems
WO2019152366A1 (en) * 2018-01-31 2019-08-08 Coventor, Inc. System and method for 2d to 3d compact model creation for a mems device
US10621295B2 (en) 2018-04-10 2020-04-14 International Business Machines Corporation Incorporation of process variation contours in design rule and risk estimation aspects of design for manufacturability to increase fabrication yield
US10714366B2 (en) * 2018-04-12 2020-07-14 Kla-Tencor Corp. Shape metric based scoring of wafer locations
CN108829999B (zh) * 2018-06-26 2022-03-01 重庆科技学院 一种强非均质性致密储层水平井分段压裂布缝优化方法
US11188687B2 (en) * 2018-11-09 2021-11-30 The Boeing Company Rule compliance checking and design generation with rule access security
KR102596609B1 (ko) 2018-11-16 2023-10-31 삼성전자주식회사 반도체 장치의 제조 방법 및 레이아웃 디자인 시스템
CN119024650A (zh) 2018-11-30 2024-11-26 Asml荷兰有限公司 用于基于可制造性确定图案形成装置图案的方法
CN110069810B (zh) * 2019-03-11 2023-04-07 北京百度网讯科技有限公司 电池故障预测方法、装置、设备和可读存储介质
TWI739101B (zh) * 2019-05-07 2021-09-11 瑞昱半導體股份有限公司 Ic設計資料庫產生方法以及ic設計方法
US10908598B1 (en) 2019-05-30 2021-02-02 Xilinx, Inc. Integrated circuits designed for multiple sets of criteria
US10796069B1 (en) 2019-06-06 2020-10-06 International Business Machines Corporation Bump connection placement in quantum devices in a flip chip configuration
KR102802057B1 (ko) * 2019-11-15 2025-04-28 어플라이드 머티어리얼스, 인코포레이티드 설계 파일 내에서의 계층적 구조 정보의 보존
US11294290B2 (en) 2019-12-02 2022-04-05 Samsung Electronics Co., Ltd. Reticle fabrication method and semiconductor device fabrication method including the same
US11574103B2 (en) * 2020-01-31 2023-02-07 International Business Machines Corporation Addressing layout retargeting shortfalls
US11126769B2 (en) * 2020-02-04 2021-09-21 Applied Materials, Inc. Unified material-to-systems simulation, design, and verification for semiconductor design and manufacturing
JP7506870B2 (ja) * 2020-04-08 2024-06-27 日本コントロールシステム株式会社 マスク情報調整装置、マスクデータ調整方法、プログラム
WO2021216771A1 (en) * 2020-04-24 2021-10-28 Coventor, Inc. System and method for performing local cdu modeling and control in a virtual fabrication environment
US11657207B2 (en) * 2020-07-28 2023-05-23 Synopsys, Inc. Wafer sensitivity determination and communication
EP4001902A1 (en) * 2020-11-23 2022-05-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Method and system for simulating an optical image of a photonic and/or electronic device
CN112507648B (zh) * 2020-11-30 2022-01-04 深圳比特微电子科技有限公司 版图设计的方法和集成电路、运算芯片和计算设备
WO2022187089A1 (en) * 2021-03-03 2022-09-09 Rambus Inc. Module authentication
US20220350950A1 (en) * 2021-04-30 2022-11-03 Synopsys, Inc. Layout versus schematic (lvs) device extraction using pattern matching
CN116819906B (zh) * 2023-08-25 2023-11-28 深圳国微福芯技术有限公司 设计规则检查方法、光学临近修正方法
CN119067040B (zh) * 2024-09-27 2025-04-01 杭州行芯科技有限公司 一种对芯片电路设计进行性能评估的方法、电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07175204A (ja) * 1993-11-08 1995-07-14 Sony Corp フォトマスク、フォトマスクの製造方法、露光方法及び半導体装置の製造方法
JP2001350250A (ja) * 2000-06-05 2001-12-21 Mitsubishi Electric Corp パターン歪み補正装置、パターン歪み補正方法、およびパターン歪み補正プログラムを記録した記録媒体
JP2002131882A (ja) * 2000-10-26 2002-05-09 Toshiba Corp マスクパターン補正方法、マスクパターン補正装置、マスクパターン補正プログラムを格納した記録媒体、及び半導体装置の製造方法

Family Cites Families (113)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532650A (en) 1983-05-12 1985-07-30 Kla Instruments Corporation Photomask inspection apparatus and method using corner comparator defect detection algorithm
FR2590376A1 (fr) 1985-11-21 1987-05-22 Dumant Jean Marc Procede de masquage et masque utilise
JPH04344979A (ja) 1991-05-22 1992-12-01 Mitsubishi Electric Corp パターンレイアウト検証装置
US5396584A (en) 1992-05-29 1995-03-07 Destiny Technology Corporation Multi-bit image edge enhancement method and apparatus
US5519628A (en) 1993-02-19 1996-05-21 International Business Machines Corporation System and method for formulating subsets of a hierarchical circuit design
JP2531114B2 (ja) 1993-10-29 1996-09-04 日本電気株式会社 光強度分布解析方法
JPH08297692A (ja) 1994-09-16 1996-11-12 Mitsubishi Electric Corp 光近接補正装置及び方法並びにパタン形成方法
US5646870A (en) 1995-02-13 1997-07-08 Advanced Micro Devices, Inc. Method for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers
JP3409493B2 (ja) 1995-03-13 2003-05-26 ソニー株式会社 マスクパターンの補正方法および補正装置
JP3934719B2 (ja) 1995-12-22 2007-06-20 株式会社東芝 光近接効果補正方法
US5723233A (en) 1996-02-27 1998-03-03 Lsi Logic Corporation Optical proximity correction method and apparatus
US6269472B1 (en) 1996-02-27 2001-07-31 Lsi Logic Corporation Optical proximity correction method and apparatus
US5663891A (en) 1996-04-03 1997-09-02 Cadence Design Systems, Inc. Optimization of multiple performance criteria of integrated circuits by expanding a constraint graph with subgraphs derived from multiple PWL convex cost functions
JP3551660B2 (ja) 1996-10-29 2004-08-11 ソニー株式会社 露光パターンの補正方法および露光パターンの補正装置および露光方法
KR100257710B1 (ko) 1996-12-27 2000-06-01 김영환 리소그라피 공정의 시물레이션 방법
US6016357A (en) 1997-06-16 2000-01-18 International Business Machines Corporation Feedback method to repair phase shift masks
US5886191A (en) * 1997-08-18 1999-03-23 Dupont Pharmaceuticals Company Amidinoindoles, amidinoazoles, and analogs thereof
KR20010024116A (ko) 1997-09-17 2001-03-26 뉴메리컬 테크날러쥐스 인코포레이티드 데이터 계층 레이아웃 교정 및 검증 방법과, 그 장치들
US6578188B1 (en) * 1997-09-17 2003-06-10 Numerical Technologies, Inc. Method and apparatus for a network-based mask defect printability analysis system
WO1999014638A1 (en) 1997-09-17 1999-03-25 Numerical Technologies, Inc. Design rule checking system and method
WO1999014637A1 (en) 1997-09-17 1999-03-25 Numerical Technologies, Inc. Data hierarchy layout correction and verification method and apparatus
US6470489B1 (en) 1997-09-17 2002-10-22 Numerical Technologies, Inc. Design rule checking system and method
US6243855B1 (en) 1997-09-30 2001-06-05 Kabushiki Kaisha Toshiba Mask data design method
US6033814A (en) 1998-02-26 2000-03-07 Micron Technology, Inc. Method for multiple process parameter matching
US6499003B2 (en) 1998-03-03 2002-12-24 Lsi Logic Corporation Method and apparatus for application of proximity correction with unitary segmentation
US6324674B2 (en) 1998-04-17 2001-11-27 Lsi Logic Corporation Method and apparatus for parallel simultaneous global and detail routing
US6128067A (en) 1998-04-28 2000-10-03 Kabushiki Kaisha Toshiba Correcting method and correcting system for mask pattern
JP3223965B2 (ja) 1998-07-10 2001-10-29 日本電気株式会社 化学増幅型レジスト形状の計算方法及び記録媒体
US6226781B1 (en) 1998-08-12 2001-05-01 Advanced Micro Devices, Inc. Modifying a design layer of an integrated circuit using overlying and underlying design layers
US6120952A (en) 1998-10-01 2000-09-19 Micron Technology, Inc. Methods of reducing proximity effects in lithographic processes
US6263299B1 (en) 1999-01-19 2001-07-17 Lsi Logic Corporation Geometric aerial image simulation
US6301697B1 (en) 1999-04-30 2001-10-09 Nicolas B. Cobb Streamlined IC mask layout optical and process correction through correction reuse
US6467076B1 (en) 1999-04-30 2002-10-15 Nicolas Bailey Cobb Method and apparatus for submicron IC design
US6249904B1 (en) 1999-04-30 2001-06-19 Nicolas Bailey Cobb Method and apparatus for submicron IC design using edge fragment tagging to correct edge placement distortion
US6187483B1 (en) 1999-05-28 2001-02-13 Advanced Micro Devices, Inc. Mask quality measurements by fourier space analysis
US6317859B1 (en) 1999-06-09 2001-11-13 International Business Machines Corporation Method and system for determining critical area for circuit layouts
US6238824B1 (en) 1999-08-31 2001-05-29 Micron Technology, Inc. Method for designing and making photolithographic reticle, reticle, and photolithographic process
US6080527A (en) 1999-11-18 2000-06-27 United Microelectronics Corp. Optical proximity correction of L and T shaped patterns on negative photoresist
US6643616B1 (en) 1999-12-07 2003-11-04 Yuri Granik Integrated device structure prediction based on model curvature
US6778695B1 (en) 1999-12-23 2004-08-17 Franklin M. Schellenberg Design-based reticle defect prioritization
US6584609B1 (en) 2000-02-28 2003-06-24 Numerical Technologies, Inc. Method and apparatus for mixed-mode optical proximity correction
WO2001097096A1 (en) 2000-06-13 2001-12-20 Mentor Graphics Corporation Integrated verification and manufacturability tool
US7412676B2 (en) 2000-06-13 2008-08-12 Nicolas B Cobb Integrated OPC verification tool
US6425113B1 (en) 2000-06-13 2002-07-23 Leigh C. Anderson Integrated verification and manufacturability tool
US6430737B1 (en) 2000-07-10 2002-08-06 Mentor Graphics Corp. Convergence technique for model-based optical and process correction
US6782516B2 (en) 2000-08-07 2004-08-24 Dupont Photomasks, Inc. System and method for eliminating design rule violations during construction of a mask layout block
US6634018B2 (en) * 2000-08-24 2003-10-14 Texas Instruments Incorporated Optical proximity correction
US6815129B1 (en) 2000-09-26 2004-11-09 Euv Llc Compensation of flare-induced CD changes EUVL
US6453457B1 (en) 2000-09-29 2002-09-17 Numerical Technologies, Inc. Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layout
US6792590B1 (en) 2000-09-29 2004-09-14 Numerical Technologies, Inc. Dissection of edges with projection points in a fabrication layout for correcting proximity effects
US6665856B1 (en) 2000-12-01 2003-12-16 Numerical Technologies, Inc. Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects
TW466586B (en) 2001-01-17 2001-12-01 United Microelectronics Corp Unlanded process
US7392168B2 (en) 2001-03-13 2008-06-24 Yuri Granik Method of compensating for etch effects in photolithographic processing
US6873720B2 (en) * 2001-03-20 2005-03-29 Synopsys, Inc. System and method of providing mask defect printability analysis
US6574784B1 (en) 2001-06-14 2003-06-03 George P. Lippincott Short edge management in rule based OPC
US6649309B2 (en) 2001-07-03 2003-11-18 International Business Machines Corporation Method for correcting optical proximity effects in a lithographic process using the radius of curvature of shapes on a mask
JP2003031468A (ja) 2001-07-13 2003-01-31 Canon Inc 半導体露光装置の管理システム及び管理方法
US20030061583A1 (en) 2001-09-14 2003-03-27 Numerical Technologies, Inc. Shape and look-up table based design rule checking (DRC) for physical verification of integrated circuit layouts
US6749972B2 (en) 2002-01-15 2004-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Optical proximity correction common process window maximization over varying feature pitch
US6668367B2 (en) 2002-01-24 2003-12-23 Nicolas B. Cobb Selective promotion for resolution enhancement techniques
US7293249B2 (en) 2002-01-31 2007-11-06 Juan Andres Torres Robles Contrast based resolution enhancement for photolithographic processing
US7013439B2 (en) 2002-01-31 2006-03-14 Juan Andres Torres Robles Contrast based resolution enhancing technology
US6887633B2 (en) 2002-02-08 2005-05-03 Chih-Hsien Nail Tang Resolution enhancing technology using phase assignment bridges
JP4152647B2 (ja) 2002-03-06 2008-09-17 富士通株式会社 近接効果補正方法及びプログラム
US6745372B2 (en) 2002-04-05 2004-06-01 Numerical Technologies, Inc. Method and apparatus for facilitating process-compliant layout optimization
US6954911B2 (en) 2002-05-01 2005-10-11 Synopsys, Inc. Method and system for simulating resist and etch edges
AU2003274370A1 (en) * 2002-06-07 2003-12-22 Praesagus, Inc. Characterization adn reduction of variation for integrated circuits
EP1523696B1 (en) 2002-07-15 2016-12-21 KLA-Tencor Corporation Defect inspection methods that include acquiring aerial images of a reticle for different lithographic process variables
US6973633B2 (en) 2002-07-24 2005-12-06 George Lippincott Caching of lithography and etch simulation results
JP4365566B2 (ja) 2002-07-31 2009-11-18 富士通マイクロエレクトロニクス株式会社 光強度シミュレーション方法及びフォトマスクの設計方法
US7172838B2 (en) 2002-09-27 2007-02-06 Wilhelm Maurer Chromeless phase mask layout generation
US6832360B2 (en) 2002-09-30 2004-12-14 Sun Microsystems, Inc. Pure fill via area extraction in a multi-wide object class design layout
US6857109B2 (en) 2002-10-18 2005-02-15 George P. Lippincott Short edge smoothing for enhanced scatter bar placement
US7313508B2 (en) * 2002-12-27 2007-12-25 Lsi Corporation Process window compliant corrections of design layout
US6928634B2 (en) 2003-01-02 2005-08-09 Yuri Granik Matrix optical process correction
US6718526B1 (en) 2003-02-07 2004-04-06 Kla-Tencor Corporation Spatial signature analysis
US6989229B2 (en) 2003-03-27 2006-01-24 Freescale Semiconductor, Inc. Non-resolving mask tiling method for flare reduction
US20050234684A1 (en) 2004-04-19 2005-10-20 Mentor Graphics Corp. Design for manufacturability
US20050015740A1 (en) 2003-07-18 2005-01-20 Mentor Graphics Corp. Design for manufacturability
TWI237746B (en) 2003-07-23 2005-08-11 Nanya Technology Corp Optical proximity correction method
JP4202214B2 (ja) 2003-09-01 2008-12-24 富士通マイクロエレクトロニクス株式会社 シミュレーション方法及び装置
US7155689B2 (en) 2003-10-07 2006-12-26 Magma Design Automation, Inc. Design-manufacturing interface via a unified model
US7010776B2 (en) 2003-10-27 2006-03-07 International Business Machines Corporation Extending the range of lithographic simulation integrals
US7073162B2 (en) 2003-10-31 2006-07-04 Mentor Graphics Corporation Site control for OPC
US7269817B2 (en) * 2004-02-10 2007-09-11 International Business Machines Corporation Lithographic process window optimization under complex constraints on edge placement
US7523429B2 (en) 2004-02-20 2009-04-21 Takumi Technology Corporation System for designing integrated circuits with enhanced manufacturability
US7861207B2 (en) 2004-02-25 2010-12-28 Mentor Graphics Corporation Fragmentation point and simulation site adjustment for resolution enhancement techniques
US7487490B2 (en) 2004-03-30 2009-02-03 Youping Zhang System for simplifying layout processing
US7269804B2 (en) * 2004-04-02 2007-09-11 Advanced Micro Devices, Inc. System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
US7194725B1 (en) 2004-04-02 2007-03-20 Advanced Micro Devices, Inc. System and method for design rule creation and selection
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
EP1747520B1 (en) 2004-05-07 2018-10-24 Mentor Graphics Corporation Integrated circuit layout design methodology with process variation bands
WO2005111796A2 (en) 2004-05-09 2005-11-24 Mentor Graphics Corporation Defect location identification for microdevice manufacturing and test
US7240305B2 (en) 2004-06-02 2007-07-03 Lippincott George P OPC conflict identification and edge priority system
JP4709511B2 (ja) 2004-08-18 2011-06-22 株式会社東芝 マスクパターン補正方法、マスクパターン補正プログラム、フォトマスクの作製方法及び半導体装置の製造方法
JP4904034B2 (ja) 2004-09-14 2012-03-28 ケーエルエー−テンカー コーポレイション レチクル・レイアウト・データを評価するための方法、システム及び搬送媒体
US7197722B2 (en) 2004-09-30 2007-03-27 Intel Corporation Optimization of sample plan for overlay
US7281224B2 (en) 2004-10-26 2007-10-09 Synopsys, Inc. Wide geometry recognition by using circle-tangent variable spacing model
JP2006189724A (ja) 2005-01-07 2006-07-20 Toshiba Corp パターン抽出システム、測定ポイント抽出方法、パターン抽出方法及びパターン抽出プログラム
US7459248B2 (en) 2005-02-24 2008-12-02 James Word Performing OPC on structures with virtual edges
US7493587B2 (en) 2005-03-02 2009-02-17 James Word Chromeless phase shifting mask for integrated circuits using interior region
US8037429B2 (en) 2005-03-02 2011-10-11 Mentor Graphics Corporation Model-based SRAF insertion
US8176445B1 (en) 2005-04-15 2012-05-08 Qi-De Qian Method and system for optimizing integrated circuit layout
US7434199B2 (en) 2005-09-27 2008-10-07 Nicolas Bailey Cobb Dense OPC
US8015510B2 (en) 2006-02-17 2011-09-06 Mentor Graphics Corporation Interconnection modeling for semiconductor fabrication process effects
US7378202B2 (en) 2006-02-21 2008-05-27 Mentor Graphics Corporation Grid-based resist simulation
US7703067B2 (en) 2006-03-31 2010-04-20 Synopsys, Inc. Range pattern definition of susceptibility of layout regions to fabrication issues
US8056022B2 (en) 2006-11-09 2011-11-08 Mentor Graphics Corporation Analysis optimizer
US7966585B2 (en) 2006-12-13 2011-06-21 Mentor Graphics Corporation Selective shielding for multiple exposure masks
US7802226B2 (en) 2007-01-08 2010-09-21 Mentor Graphics Corporation Data preparation for multiple mask printing
US7739650B2 (en) 2007-02-09 2010-06-15 Juan Andres Torres Robles Pre-bias optical proximity correction
US8122392B2 (en) * 2007-06-27 2012-02-21 Cadence Design Systems, Inc. Robust design using manufacturability models
US9053283B2 (en) * 2013-03-12 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for layout verification for polysilicon cell edge structures in finFET standard cells using filters

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07175204A (ja) * 1993-11-08 1995-07-14 Sony Corp フォトマスク、フォトマスクの製造方法、露光方法及び半導体装置の製造方法
JP2001350250A (ja) * 2000-06-05 2001-12-21 Mitsubishi Electric Corp パターン歪み補正装置、パターン歪み補正方法、およびパターン歪み補正プログラムを記録した記録媒体
JP2002131882A (ja) * 2000-10-26 2002-05-09 Toshiba Corp マスクパターン補正方法、マスクパターン補正装置、マスクパターン補正プログラムを格納した記録媒体、及び半導体装置の製造方法

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4755655B2 (ja) * 2005-01-21 2011-08-24 インターナショナル・ビジネス・マシーンズ・コーポレーション 差分交互位相シフト・マスクの最適化
JP2009141352A (ja) * 2007-12-05 2009-06-25 Brion Technologies Inc リソグラフィプロセスウィンドウをシミュレートするための方法及びシステム
US8200468B2 (en) 2007-12-05 2012-06-12 Asml Netherlands B.V. Methods and system for lithography process window simulation
US9390206B2 (en) 2007-12-05 2016-07-12 Asml Netherlands B.V. Methods and systems for lithography process window simulation
US8527255B2 (en) 2007-12-05 2013-09-03 Asml Netherlands B.V. Methods and systems for lithography process window simulation
JP2010026076A (ja) * 2008-07-16 2010-02-04 Renesas Technology Corp リソグラフィシミュレーション装置、ならびにリソグラフィシミュレーションプログラムおよびそれを使用した半導体装置設計製造方法
JP2012511168A (ja) * 2008-12-05 2012-05-17 マイクロニック マイデータ アーベー マイクロリソグラフ印刷における勾配を援用した画像再サンプリング
US9245871B2 (en) 2009-10-07 2016-01-26 Qualcomm Incorporated Vertically stackable dies having chip identifier structures
US8698321B2 (en) 2009-10-07 2014-04-15 Qualcomm Incorporated Vertically stackable dies having chip identifier structures
JP2013507773A (ja) * 2009-10-07 2013-03-04 クアルコム，インコーポレイテッド チップ識別構造体を有する垂直積層可能なダイ
US9411647B2 (en) 2010-01-22 2016-08-09 Qualcomm Incorporated Hierarchical routing and interface selection for multi-processor multimode network devices
US20220128899A1 (en) * 2020-10-22 2022-04-28 D2S, Inc. Methods and systems to determine shapes for semiconductor or flat panel display fabrication
US12372864B2 (en) * 2020-10-22 2025-07-29 D2S, Inc. Methods and systems to determine shapes for semiconductor or flat panel display fabrication
US12387029B2 (en) 2021-07-23 2025-08-12 D2S, Inc. Computing parasitic values for semiconductor designs
US12488175B2 (en) 2021-07-23 2025-12-02 D2S, Inc. Methods and systems to determine parasitics for semiconductor or flat panel display fabrication
US12475283B2 (en) 2022-01-19 2025-11-18 D2S, Inc. Generating and display an animation of a predicted overlap shape in an IC design
US12499301B2 (en) 2022-08-16 2025-12-16 D2S, Inc. Computing parasitic values for semiconductor designs

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