US10628544B2 - Optimizing integrated circuit designs based on interactions between multiple integration design rules - Google Patents
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Definitions
- the present invention relates generally to the field of integrated circuit design and, more particularly, to optimizing integrated circuit designs based on interactions between multiple integration design rules.
- Design for manufacturing refers to various “design rules” that are implemented during the design of integrated circuits (IC(s)) to improve the manufacturability of the ICs. More specifically, design rules are rules that are intended to ensure that ICs can be manufactured with economical yields and ensure that ICs possess sufficient reliability in operation. Design rules are often set by semiconductor manufacturers (i.e., “foundries”) based on manufacturing process constraints. In particular, the trend towards smaller and smaller nodes has challenged foundries to overcome the limitations of various photolithographic, chemical, and mechanical processes with respect to the accuracy and the precision of feature dimensions and positioning.
- diffraction effects and variations in mask placement, depth of focus, and light intensity can affect the accuracy and precision with which shapes (i.e., IC components) can be patterned on wafers.
- IC designs that do not account for such effects can result in higher rates of manufacturing defects occurring due, for example, to pinched, broken, or shorted components.
- foundries often specify design rules that control various dimensional parameters of IC designs by mandating, among other things, minimum space checks, minimum width checks, minimum area overlap checks, and minimum area variability checks on IC designs prior to accepting an IC design for fabrication. As process nodes have become smaller and smaller, foundries have generally implemented design rules of increasing complexity.
- a method for optimizing integrated circuit (IC) designs based on interactions between multiple integration design rules includes: identifying, within an IC design, a plurality of IC features having design shapes; for each IC feature, determining a total risk value based, at least in part, on one or more integration design rules; ordering, based on the total risk value of each IC feature, the IC features from an IC feature having a highest total risk value to an IC feature having a lowest total risk value; identifying, beginning with the IC feature having the highest total risk value, a threshold count of IC features from the ordered IC features, wherein IC features within the threshold count of IC features represent a plurality of high-risk IC features; clipping the IC design around the high-risk features to produce a clipped area; simulating an overall failure rate of IC features within the clipped area; determining that the overall failure rate exceeds a threshold overall failure rate, and in response, calculating a predicted failure rate for each design
- a computer program product for optimizing integrated circuit (IC) designs based on interactions between multiple integration design rules.
- the computer program product comprises a computer readable storage medium and program instructions stored on the computer readable storage medium.
- the program instructions include: program instructions to identify, within an IC design, a plurality of IC features having design shapes; program instructions to, for each IC feature, determine a total risk value based, at least in part, on one or more integration design rules; program instructions to order, based on the total risk value of each IC feature, the IC features from an IC feature having a highest total risk value to an IC feature having a lowest total risk value; program instructions to identify, beginning with the IC feature having the highest total risk value, a threshold count of IC features from the ordered IC features, wherein IC features within the threshold count of IC features represent a plurality of high-risk IC features; program instruction to clip the IC design around the high-risk features to produce a clipped area; program instructions to simulate an overall
- a computer system for optimizing integrated circuit (IC) designs based on interactions between multiple integration design rules includes one or more computer processors, one or more computer readable storage media, and program instructions stored on the computer readable storage media for execution by at least one of the one or more processors.
- the program instructions include: program instructions to identify, within an IC design, a plurality of IC features having design shapes; program instructions to, for each IC feature, determine a total risk value based, at least in part, on one or more integration design rules; program instructions to order, based on the total risk value of each IC feature, the IC features from an IC feature having a highest total risk value to an IC feature having a lowest total risk value; program instructions to identify, beginning with the IC feature having the highest total risk value, a threshold count of IC features from the ordered IC features, wherein IC features within the threshold count of IC features represent a plurality of high-risk IC features; program instruction to clip the IC design around the high-risk features to produce a clipped area; program instructions to simulate an overall failure rate of IC features within the clipped area; program instructions to calculate a predicted failure rate for each design rule that applies to IC features within the clipped area in response to determining that the overall failure rate exceeds a threshold overall failure rate; program instructions to identify
- FIG. 1 is a functional block diagram illustrating a computing environment, in accordance with an embodiment of the present invention.
- FIG. 2 is an abstract representation of IC features to which various integration design rules apply, in accordance with an embodiment of the present invention.
- FIG. 3A is an abstract representation of IC features to which various integration design rules apply, in accordance with an embodiment of the present invention.
- FIG. 3B is a table depicting values used to characterize risk with respect to one of the IC features depicted in FIG. 3A , in accordance with an embodiment of the present invention.
- FIG. 4A is a flowchart depicting operations for optimizing IC design by, at least in part, predicting disadvantageous interactions between integration design rules, on a computing device within the computing environment of FIG. 1 , in accordance with an embodiment of the present invention.
- FIG. 4B is a flowchart depicting operations for, in addition to the operations depicted in FIG. 4A , optimizing IC design by, at least in part, predicting disadvantageous interactions between integration design rules, on a computing device within the computing environment of FIG. 1 , in accordance with an embodiment of the present invention.
- FIG. 5 is a block diagram of components of a computing device, in accordance with an embodiment of the present invention.
- restrictive design rules RDR(s)
- process design rules process design rules
- integration design rules integration design rules
- Restrictive design rules are design rules that seek to improve the manufacturability of IC designs by standardizing IC features (i.e., IC design shapes). Restrictive design rules standardize IC design by specifying, alone or in any combination, specific feature dimensions, specific pitch lengths (i.e., the distance between identical features), and specific feature orientations.
- Process design rules are design rules that specify minimum feature dimensions (e.g., lengths, widths, and thicknesses) to improve yields by minimizing the occurrence of defects (e.g., pinched, broken, or shorted interconnects) due to variations in the manufacturing process. Variations in the manufacturing process can result in feature dimensions that depart from the dimensions specified by the IC design and/or design rules. Process design rules are chosen such that variations in the manufacturing process do not result in features having dimensions less than the dimensions that are likely to increase the rate of manufacturing defects and thus reduce yields.
- minimum feature dimensions e.g., lengths, widths, and thicknesses
- defects e.g., pinched, broken, or shorted interconnects
- Integration design rules are design rules involving dimensional parameters with respect to two or more design layers. Integration design rules can represent design considerations with respect to restrictive design rules, process design rules, or a combination of restrictive design rules and process design rules between multiple layers.
- the concept of “layers” results from the series of photolithographic masks that are typically used to pattern features onto an IC wafer.
- An interlayer integration design rule can, for example, specify a minimum “overlap” (e.g., in terms of area) between features in adjacent layers (i.e., sequential masks; e.g., the overlap of a contact and a transistor gate) or specify a minimum separation between features patterned in different layers (e.g., transistors and adjacent vias).
- integration design rules are calculated based on wafer failure mechanism and manufacturing process information such as critical dimension uniformity, positioning errors with respect to scanners and/or steppers (i.e., “overlay” errors), and expected differences between IC design dimensions and “on-wafer” dimensions (i.e., “bias”), among other things.
- Embodiments of the present invention recognize that “rule slack,” or “RuleSlack,” generally decreases as IC node sizes decrease because variations in the IC fabrication process become larger as a percentage of IC design and “on-wafer” dimensions (e.g., feature dimensions and spacing between features).
- multiple patterning e.g., double, triple, and quadruple patterning
- increases the probability of overlay errors i.e., positioning errors with respect to scanners and/or steppers
- embodiments of the present invention recognize that, while designing an IC feature with minimum rule slack (i.e., at a minimum design rule) may not disadvantageously effect yields and reliability based on an analysis of the individual design rule, (i) interactions between design rules are complex and (ii) designing IC features at multiple minimum design rules and/or a minimum integration design rule can produce effects that combine to unacceptably increase the risk of failures and correspondingly decrease yields and reliability. For example, increasing an IC dimensions to improve an IC design with respect to a first design rules may increase the likelihood of failures with respect to a second design rule. Additionally, embodiments of the present invention recognize that, even in situations where an IC design does not violate any individual integration design rule, interactions between integration design rules (i.e., multi-rule interactions) can increase risk.
- rule slack refers to a measure of advantageous “redundancy” that a specific design dimensions can be reduced before violating an applicable design rule. Additionally, “actual rule slack” refers to the “redundancy” that a specific design dimension can be reduced before resulting in lower yields or lower reliability due to on-wafer failures. Persons having ordinary skill in the art will understand that “actual rule slack” is not known during the design and design verification phase of IC production.
- Embodiments of the present invention provide a technique for analyzing interactions between multiple integration design rules in order to identify high-risk IC regions and optimize IC designs by selectively increasingly rule slack with respect to individual integration design rules within the high-risk IC regions.
- FIG. 1 is a functional block diagram illustrating a computing environment, in accordance with an embodiment of the present invention.
- FIG. 1 is a functional block diagram illustrating computing environment 100 .
- Computing environment 100 includes foundry system 110 and IC design system 130 , which are communicatively connected over network 120 .
- Foundry system 110 includes design rules 112 ;
- IC design system 130 includes IC model verification logic 132 and IC model data 134 .
- foundry system 110 is a computing device that can be a standalone device, a server, a laptop computer, a tablet computer, a netbook computer, a personal computer (PC), or a desktop computer.
- foundry system 110 represents a computing system utilizing clustered computers and components to act as a single pool of seamless resources.
- foundry system 110 can be any computing device or a combination of devices with access to IC design system 130 and the capability to store or access design rules 112 .
- Foundry system 110 may include internal and external hardware components, as depicted and described in further detail with respect to FIG. 5 .
- foundry system 110 represents the information technology infrastructure of an IC foundry.
- foundry system 110 stores one or more design rules but communicates the one or more design rules to IC design system 130 via a method other than network 120 (e.g., physically sending a computer readable storage device to IC design system 130 on which design rules 112 are stored).
- foundry system 110 can utilize any one method of communication or any combination of methods of communication explicitly and/or implicitly described herein to communicate design rules 112 to IC design system 130 .
- Design rules 112 represents a data repository that may be written to and read by one or both of foundry system 110 and IC design system 130 .
- Design rules 112 can store one or more design rules.
- design rules 112 can store one or more restrictive design rules, one or more process design rules, one or more integration design rules, and any combination of the aforementioned types of IC design rules.
- foundry system 110 can include any number of data repositories to store any information with respect to the fabrication of ICs.
- design rules 112 may be written to and read by programs and entities outside of computing environment 100 in order to populate the repository, or any repository that is associated with foundry system 110 , with information relating to the fabrication of ICs.
- Network 120 communicatively connects foundry system 110 and IC design system 130 to facilitate the transfer of information between the two systems.
- Network 120 can be, for example, a local area network (LAN), a wide area network (WAN) such as the Internet, or a combination of the two, and may include wired, wireless, fiber optic or any other connection known in the art.
- LAN local area network
- WAN wide area network
- network 120 can be any combination of connections and protocols that will support communications between foundry system 110 and IC design system 130 , in accordance with various embodiments of the present invention.
- IC design system 130 is a computing device that can be a standalone device, a server, a laptop computer, a tablet computer, a netbook computer, a personal computer (PC), or a desktop computer.
- IC design system 130 represents a computing system utilizing clustered computers and components to act as a single pool of seamless resources.
- IC design system can be any computing device or a combination of devices with access to that is capable of executing IC model verification logic 132 and with access to IC model data 134 .
- IC designs system 130 can include internal and external hardware components, as depicted and described in further detail with respect to FIG. 5 .
- IC model verification logic 132 and IC model data 134 are stored on IC design system 130 .
- IC model data 134 represents a data repository that may be written to and read by computer programs executing on one or both of foundry system 110 and IC design system 130 (e.g., IC model verification logic 132 ).
- IC model verification logic 132 and IC model data 134 can reside on another computing device, provided that each can access and is accessible by each other.
- one or both of IC model verification logic 132 and IC model data 134 can be stored externally and accessed through a communication network, such as network 120 .
- IC model data 134 can be written to and read by programs and entities outside of computing environment 100 in order to populate the repository, or any repository associated with IC design system 130 , with data representing one or more IC designs, one or more IC design rules, and any other information relating to IC fabrication and design.
- IC model verification logic 132 operates to, among other things, evaluate various integration design rules to identify high-risk IC regions and optimize IC designs by selectively increasingly rule slack with respect to individual integration design rules within the high-risk IC regions, as will be described in greater detail with respect to subsequent figures.
- FIG. 2 is an abstract representation of IC features to which various integration design rules apply, in accordance with an embodiment of the present invention. More specifically, FIG. 2 depicts representative IC region 200 .
- representative IC region 200 is a simplified depiction of various IC features to facilitate discussion of various aspects of embodiments of the present invention.
- representative IC region 200 includes interconnect 210 , vias 220 , caches 230 , and transistor contacts 240 .
- one more IC design rules can apply to each of the features depicted in representative IC region 200 such that the IC design rules determine, to a certain extent, the shapes and/or dimensions of corresponding IC features.
- representative IC region 200 depicts multiple “layers” and/or “patterns” on an IC and that, in general, each type of feature depicted in representative IC region 200 is patterned (i.e., shaped) and deposited utilizing respective mask(s) and various other fabrication processes (e.g., depositing photoresists, etching, and various forms of planarization). Accordingly, representative IC region 200 depicts a region of an IC in which multiple integration design rules apply.
- a first integration design rule may dictate a minimum “enclosure” with respect to vias 220 and interconnect 210 (i.e., a minimum dimensional margin between the edges of vias 220 and the edges of interconnect 210 ).
- a second integration design rule may dictate a minimum “spacing” between caches 230 and interconnect 210 and a third design rule may dictate a minimum “spacing” between transistor contacts 240 and interconnect 210 .
- FIG. 2 does not depict an exhaustive list of design rules to which embodiments of the present invention apply.
- IC model verification logic 132 can also analyze various other types of IC design rules (e.g., integration design rules applicable to source, drain, and gate regions of transistors and source, drain, and gate contacts, among others).
- IC design rules e.g., integration design rules applicable to source, drain, and gate regions of transistors and source, drain, and gate contacts, among others.
- FIG. 3A is an abstract representation of IC features to which various integration design rules apply, in accordance with an embodiment of the present invention. More specifically, FIG. 3A depicts representative IC region 300 , which is a yet more simplified depiction of various IC features than representative IC region 200 depicted in FIG. 2 .
- Representative IC region 300 is a simplified depiction of various IC features to facilitate discussion of various aspects of embodiments of the present invention.
- Representative IC region 300 includes IC feature 305 (i.e., the feature identified as “A”), IC feature 310 (i.e., the feature identified as “B”), IC feature 315 (i.e., the feature identified as “C”), and IC feature 320 (i.e., the feature identified as “D”).
- a first integration design rule, integration design rule 330 A represents a distance between IC feature 305 and IC feature 310 .
- a second integration design rule, integration design rule 330 B represents a distance between IC feature 305 and IC feature 315 .
- a third integration design rule, integration design rule 330 C represent a distance between IC feature 305 and IC feature 320 .
- Integration design rules 330 A, 330 B, and 330 C are collectively referred to as integration design rules 330 herein. Integration design rules 330 represent integration design rules with respect to IC feature 305 .
- FIG. 3 does not depict an exhaustive list of design rules to which embodiments of the present invention apply and is merely intended to provide a point of reference to facilitate a discussion of the calculation of the “RuleRiskSum” for IC feature 305 , as discussed subsequently with respect to FIG. 3B .
- FIG. 3B is a table depicting values used to characterize risk with respect to one of the IC features depicted in FIG. 3A , in accordance with an embodiment of the present invention. More specifically, FIG. 3A depicts values that characterize integration design rules 330 and from which IC model verification logic 132 can calculate a “RuleSlack” and a “RuleRisk” for each integration design rule and a “RuleRiskSum” with respect to IC feature 305 , as described herein.
- table 350 includes: a column (i.e., column 352 ) listing each integration design rule that applies to IC feature 305 (i.e., feature “A”; integration design rule 330 A, “rule A/B,” integration design rule 330 B, “rule A/C,” and integration design rule 330 C, “rule A/D”); a column listing a design value for each integration design rule (i.e., “DesignValue,” column 354 ); a column listing a minimum rule value for each integration design rule (i.e., “RuleValue,” column 356 ); a column listing a “rule slack” for each integration design rule (i.e., “RuleSlack,” column 358 ); and a column listing a “rule risk” for each integration design rule (i.e., “RuleRisk,” column 360 ).
- a column i.e., column 352
- each integration design rule that applies to IC feature 305 i.e., feature “
- Table 350 also includes a “max risk” (i.e., “MaxRisk”) value and a “rule-risk sum” value (i.e., “RuleRiskSum”) for the IC feature being analyzed (i.e., IC feature 305 in the embodiment depicted in FIG. 3B ).
- a “max risk” i.e., “MaxRisk”
- a “rule-risk sum” value i.e., “RuleRiskSum”
- integration design rule values i.e., values in column 356
- the value for “MaxRisk” are determined based on explicit or implicit requirements of one or more foundries in which fabrication is desired (e.g., the “RuleValues” and “MaxRisk” value may be based on information from design rules 112 on foundry system 110 ).
- the “MaxRisk” value can vary based on an intended design node, specific fabrication processes used by a foundry, desired yield, desired reliability, failure mode analyses, and/or various other factors and combinations of factors known to such persons.
- “MaxRisk” is an artificial value that is set with the objective of capping the risk associated with the application of one or more design rules to an IC design.
- a selected “MaxRisk” value is based, at least in part, on anticipated deviations from design values due to various factors in IC production (e.g., overlay values, bias values, etc.).
- a “MaxRisk” value may be set such that the “MaxRisk” value represents a dimensional value at three or four standard deviations (i.e., 3 ⁇ or 4 ⁇ ) from one or more design values.
- the “MaxRisk” value is 6 nanometers (nm).
- Embodiments of the present invention utilize expression 1 to calculate “design rule slack” (i.e., “RuleSlack,” the values listed in column 358 of table 350 ).
- design rule slack represents a margin between a design rule value and the corresponding value specified by an IC design. While introducing the concept of design rule slack to IC design analysis and verification is advantageous for characterizing the anticipated properties of an IC design, design rule slack generally differs from actual rule slack for two reasons. A first reason is that, in general, a design rule value is set to cover a range of design scenarios in which the design rule value is selected based on a worst-case design scenario.
- actual rule slack (i.e., some “redundancy”) can exist, even when a design value is set at the minimum design rule value, with respect to a non-worst-case design scenario.
- a second reason that design rule slack can differ from actual rule slack is that errors due to variations in the fabrication process (e.g., critical dimension uniformity, overlay, and bias) are unknown during the design, analysis, and verification phases of the IC design process. For at least these reasons, actual rule slack is generally unknown during the initial design, analysis, and verifications phases of the IC design process.
- “RuleSlack” for “rule A/B” is calculated by subtracting 8 nm, the “RuleValue” for “rule A/B”, from 8 nm, the “DesignValue” for the separation of IC feature 305 and IC feature 310 , to yield a “RuleSlack” of 0 nm.
- Embodiments of the present invention utilize expression 2 to calculate a “rule risk” (i.e., “RuleRisk,” the values listed in column 360 of table 350 ).
- rule risk characterizes risk with respect to an integration design rule value and a specific value of a dimensional relationship with respect to two of more IC features specified by an IC design.
- Embodiments of the present invention recognize that some design rules are considered more important than others. Foundries, for example, may place greater importance on design rules relating to features and processes that are known to be more susceptible to dimensional variations during fabrication than others. Similarly, foundries may place greater importance on design rules that address certain failure mechanisms over design rules that address other failure mechanisms (e.g., design rules to protect against shorting versus enclosure rules). Additionally, IC designers may identify IC regions and circuitry that have greater importance than other IC regions and circuitry, and thus, IC designers may also specify that certain design rules are more important than others. In circumstances where integration design rules are not of equal importance relative to one another, embodiments of the present invention provide the ability to weight integration design rules relative to one another.
- FIG. 4A is a flowchart depicting operations for optimizing an IC design by, at least in part, predicting disadvantageous interactions between integration design rules, on a computing device within the computing environment of FIG. 1 , in accordance with an embodiment of the present invention. More specifically, FIG. 4 is a flowchart depicting operations 400 of IC model verification logic 132 on IC design system 130 within computing environment 100 . Similarly, FIG. 4B is a flowchart depicting additional operations that comprise operations 400 of IC model verification logic 132 that can be executed, in addition to the operations depicted in FIG. 4A , to optimize an IC design by, at least in part, predicting disadvantageous interactions between integration design rules, on a computing device within the computing environment of FIG. 1 , in accordance with an embodiment of the present invention.
- IC model verification logic 132 selects a specific IC feature to analyze with respect to the application of one or more applicable design rules. Accordingly, in operation 402 , IC model verification logic 132 selects an integration design rule to analyze with respect to the specific IC feature selected in operation 401 .
- IC model verification logic 132 can select IC feature 305 in operation 401 and select integration design rule 330 A to analyze with respect to IC feature 305 in operation 402 .
- integration design rule 330 A is analyzed based on the distance between IC feature 305 and IC feature 310 because IC feature 310 is an IC feature to which the selected integration rule applies in addition to IC feature 305 .
- IC feature 310 is “implicated” by the analysis of the selected integration design rule “as a function of” IC feature 305 , but IC model verification logic 132 does not analyze the selected integration design rule “as a function of” IC feature 310 in this particular iteration of operations 401 through 416 but may analyze the selected integration design rule for an iteration of operations 401 through 416 in which IC model verification logic 132 selects IC feature 310 in operation 401 .
- IC model verification logic 132 calculates a “RuleSlack” based on a “RuleValue” for the selected integration design rule and a corresponding “DesignValue” in operation 404 .
- IC model verification logic 132 calculates a “RuleRisk” utilizing (i) expressions 2 and 3 for the selected integration design rule and (ii) a “MaxRisk”.
- the “RuleRisk” value can be weighted, utilizing expression 7, to reflect the relative importance of various integration design rules and/or IC features.
- the “RuleRisk” value is based on the identity of the specific IC feature in this application of the selected integration design rule, the “RuleRisk” value, and similarly, any “RuleRiskSum” value derived, at least in part, from the “RuleRisk” value, are considered to be values determined “as a function of” the specific IC feature.
- IC model verification logic 132 determines that the “RuleRisk” value is equal to zero, because the “RuleSlack” value is equal to or greater than the “MaxRisk” value (decision 408 , YES branch), IC model verification logic 132 , in operation 410 , dumps the “RuleSlack” and “RuleRisk” values calculated with respect to the selected integration design rule and the selected IC feature (i.e., IC model verification logic 132 will not add the “RuleRisk” associated with the selected integration design rule when calculate the “RuleRiskSum” for the selected IC feature). In the embodiment depicted in FIG.
- IC model verification logic 132 determines that it has analyzed all integration design rules that are applicable to the selected IC feature (decision 414 , YES branch), IC model verification logic 132 calculates a “RuleRiskSum” for the selected IC Feature (operation 416 ).
- the “RuleRisk” values used to calculate the “RuleRiskSum” values can be weighted based on the relative importance of integration design rules and/or IC features.
- IC model verification logic 132 is executed to analyze a complete IC model. In other embodiments of the present invention, iterations of IC model verification logic 132 are executed to analyze and optimize an IC model based on respective “domains” (i.e., each iteration of IC model verification logic 132 analyzes and optimizes a respective physical region of the IC model).
- design rule checking is computational intensive, and therefore, it is advantageous to divide an IC model into a plurality of domains and distribute design rule checking tasks (i.e., iterations of IC model verification logic 132 ) across multiple logical processing units. Each iteration of IC model verification logic 132 executes the applicable logical tasks depicted in FIG.
- IC model verification logic 132 determines that it has analyzed not analyzed all IC features within a respective domain or within the IC model (decision 417 , NO branch), IC model verification logic selects another IC feature (i.e., another iteration of operation 401 ).
- IC model verification logic 132 determines that it has analyzed all IC features within a respective domain or within the IC model (decision 417 , YES branch), IC model verification logic 132 merges all of the layouts generated in various iterations of operation 412 , as described with respect to operation 418 in FIG. 4B .
- the merged layouts represent applications of integration design rules for which the calculated “RuleRisk” values are greater than zero.
- IC model verification logic 132 orders (i.e., sorts) IC features based on the calculated “RuleRiskSum” values (operation 420 ) from high to low. In embodiments like the one depicted in FIG. 4A , IC model verification logic 132 identifies “high-risk” IC features (operation 422 ) by identifying the IC features having the highest “RuleRiskSum” values up to a threshold count of IC features.
- IC features having “RuleRiskSum” values equal to zero are dumped in operation 420 .
- IC features having “RuleRiskSum” values equal to zero are dumped prior to operation 420 (e.g., immediately subsequent to operation 416 ).
- IC model verification logic 132 identifies any IC feature having a “RuleRiskSum” value greater than a threshold “RuleRiskSum” value as a “high-risk” IC feature that may benefit from further design optimization (operation 422 ).
- a threshold “RuleRiskSum” value can be selected based on (i) available computer processing resources and/or time and/or (ii) “RuleRiskSum” values that are known or expected to correlate with decrease IC yields and/or reliability.
- IC model verification logic 132 “clips” the IC design around the respective “high-risk” IC features (i.e., models a portion of the IC design; operation 424 ).
- the “clipped” area represents an area of the IC design defined by “high-risk” IC features and the “nearest neighbor” features in each direction to the “high-risk” IC features.
- the “clipped” area can represent an area of the IC design beyond that defined by the “nearest neighbor” features in each direction; in such embodiments, the “clipped” area can be determined based on integration design rules involving the “high-risk” IC component, predicted failure mechanisms, and other factors that can effect one or more of yield, reliability, and risk.
- IC model verification logic 132 simulates an overall failure rate (operation 426 ).
- the simulation in operation 426 incorporates all design rules involving IC features within the “clipped” area (e.g., integration rules for which “RuleRisk” equals zero, design rules with respect to IC features for which “RuleRiskSum” equals zero, and/or one or more RDRs and/or process design rules). In other embodiments of the present invention, the simulation in operation 426 incorporates only the integration design rules involving IC features within the merged layouts. Within the “clipped” area, IC model verification logic 132 determines if the overall failure rate is less than a threshold overall failure rate (decision 428 ).
- a value for the threshold failure rate can be chosen based on parameters established by the foundry (e.g., a threshold failure rate of 4 ⁇ -5 ⁇ ). If IC model verification logic 132 determines that the overall failure rate exceeds the threshold overall failure rate within the “clipped” area (decision 428 , YES branch), IC model verification logic 132 terminates with respect to processes involving the “clipped” area.
- IC model verification logic 132 determines that the overall failure rate does not exceed the threshold overall failure rate for the “clipped” area (decision 428 , NO branch), IC model verification logic 132 calculates a predicted failure rate for all design rules within the “clipped” area (operation 430 in FIG. 4B ).
- simulation in operation 426 incorporates all design rules within the “clipped” area (e.g., integration rules for which “RuleRisk” equals zero, design rules with respect to IC features for which “RuleRiskSum” equals zero, and/or one or more RDRs and/or process design rules), data that IC model verification logic 132 can utilize the data obtained via the simulation of the “clipped” area in operation 426 to calculate a predicted failure rate with respect to each rule (operation 430 ).
- design rules within the “clipped” area e.g., integration rules for which “RuleRisk” equals zero, design rules with respect to IC features for which “RuleRiskSum” equals zero, and/or one or more RDRs and/or process design rules
- IC model verification logic 132 simulates and calculates a predicted failure rate for each design rule within the clipped area (e.g., including integration rules for which “RuleRisk” equals zero, design rules with respect to IC features for which “RuleRiskSum” equals zero, and/or one or more RDRs and/or process design rules). Based on the predicted failure rate for each design rule, IC model verification logic 132 orders the design rules (operation 432 ) and identifies “high-risk” design rules for which the predicted failure rate exceeds a threshold failure rate for the clipped area.
- a predicted failure rate for each design rule within the clipped area e.g., including integration rules for which “RuleRisk” equals zero, design rules with respect to IC features for which “RuleRiskSum” equals zero, and/or one or more RDRs and/or process design rules.
- IC model verification logic 132 orders the design rules (operation 432 ) and identifies “high-risk” design rules for which the predicted failure rate
- the threshold failure rate for the clipped area is the same as the threshold overall failure rate or as close to the threshold overall failure rate as possible.
- the threshold failure rate within one or more clipped areas can be greater than or less than the threshold overall failure rate based on IC features within the clipped area, the relative importance of a domain in which the “clipped” area is located, design considerations required by the foundry, or various other factors that will be apparent to persons having ordinary skill in the art.
- IC model verification logic 132 modifies the IC design with respect to IC features associated with the “high-risk” rules in order to increase “RuleSlack,” or reduce the predicted failure rate by any other means, for “high-risk” design rules (operation 436 ).
- increasing “RuleSlack” for “Rule A/B” would involve increasing the separation between IC feature 305 and IC feature 310 (i.e., feature “A” and feature “B”) by repositioning one or both or IC feature 305 and IC feature 310 and/or reducing the an appropriate dimension of one or both of IC feature 305 and IC feature 310 .
- modifications to the IC design are made via one or more automated processes. In other embodiments, modification to the IC design are made manually. In yet other embodiments, modifications to various features of the IC design can be made by one or both of an automated process or a manual process. Because increasing RuleSlack and/or reducing the predicted failure rate of one design rules by other means can affect other design rules, IC model verification logic simulates the overall failure rate in the “clipped area” based on the modified IC design (operation 426 , as depicted in FIG. 4A ). With respect to modified IC designs, IC model verification logic 132 simulates all design rules within in the “clipped area” regardless of whether or not the initial simulation of the “clipped” area simulated all such design rules. Accordingly, IC model verification logic 132 can advantageously optimize the IC design within the “clipped area” via one or more iterations of operations 426 , 430 , 432 , 434 , and 436 .
- the optimized IC design can be used to fabricate one or more ICs (e.g., by foundry system 110 ).
- yields and reliability may be advantageously increased relative a non-optimized IC design.
- the non-optimized IC design may exhibit lower yields and/or reliability due to complex interactions between integration design rules and/or effects that combine to unacceptably increase the risk of failures and correspondingly decrease yields and reliability when IC features are designed for multiple minimum design rules and/or a minimum integration design rule.
- FIG. 5 is a block diagram of components of a computing device, generally designated 500 , in accordance with an embodiment of the present invention.
- computing system 500 is representative of IC design system 130 within computing environment 100 , in which case IC design system 130 includes IC model verification logic 132 .
- FIG. 5 provides only an illustration of one implementation and does not imply any limitations with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made.
- Computing system 500 includes processor(s) 502 , cache 506 , memory 504 , persistent storage 510 , input/output (I/O) interface(s) 512 , communications unit 514 , and communications fabric 508 .
- Communications fabric 508 provides communications between cache 506 , memory 504 , persistent storage 510 , communications unit 514 , and input/output (I/O) interface(s) 512 .
- Communications fabric 508 can be implemented with any architecture designed for passing data and/or control information between processors (such as microprocessors, communications and network processors, etc.), system memory, peripheral devices, and any other hardware components within a system.
- processors such as microprocessors, communications and network processors, etc.
- Communications fabric 508 can be implemented with one or more buses or a crossbar switch.
- Memory 504 and persistent storage 510 are computer readable storage media.
- memory 504 includes random access memory (RAM).
- RAM random access memory
- memory 504 can include any suitable volatile or non-volatile computer readable storage media.
- Cache 506 is a fast memory that enhances the performance of processor(s) 502 by holding recently accessed data, and data near recently accessed data, from memory 504 .
- persistent storage 510 includes a magnetic hard disk drive.
- persistent storage 510 can include a solid state hard drive, a semiconductor storage device, read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, or any other computer readable storage media that is capable of storing program instructions or digital information.
- the media used by persistent storage 510 may also be removable.
- a removable hard drive may be used for persistent storage 510 .
- Other examples include optical and magnetic disks, thumb drives, and smart cards that are inserted into a drive for transfer onto another computer readable storage medium that is also part of persistent storage 510 .
- Communications unit 514 in these examples, provides for communications with other data processing systems or devices.
- communications unit 514 includes one or more network interface cards.
- Communications unit 514 may provide communications through the use of either or both physical and wireless communications links.
- Program instructions and data used to practice embodiments of the present invention may be downloaded to persistent storage 510 through communications unit 514 .
- I/O interface(s) 512 allows for input and output of data with other devices that may be connected to computer system 500 .
- I/O interface(s) 512 may provide a connection to external device(s) 516 such as a keyboard, keypad, a touch screen, and/or some other suitable input device.
- External device(s) 516 can also include portable computer readable storage media such as, for example, thumb drives, portable optical or magnetic disks, and memory cards.
- Software and data used to practice embodiments of the present invention can be stored on such portable computer readable storage media and can be loaded onto persistent storage 510 via I/O interface(s) 512 .
- I/O interface(s) 512 also connect to display 518 .
- Display 518 provides a mechanism to display or present data to a user and may be, for example, a computer monitor.
- the present invention may be a system, a method, and/or a computer program product at any possible technical detail level of integration
- the computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention
- the computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device.
- the computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.
- a non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.
- RAM random access memory
- ROM read-only memory
- EPROM or Flash memory erasable programmable read-only memory
- SRAM static random access memory
- CD-ROM compact disc read-only memory
- DVD digital versatile disk
- memory stick a floppy disk
- a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon
- a computer readable storage medium is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
- Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network.
- the network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers.
- a network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
- Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages.
- the computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
- the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
- electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
- These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
- These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
- the computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
- each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s).
- the functions noted in the blocks may occur out of the order noted in the Figures.
- two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
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Abstract
Description
RuleSlack(x n)=DesignValue(x n)−DesignRule(x n), Expression 1
wherein(i) “xn” represents a specific application of an integration design rule with respect to an IC feature for which IC model verification logic 132 is characterizing risk (i.e., calculating a “RuleRiskSum(a),” as subsequently described), (ii) “DesignValue(xn)” is a dimensional value specified by an IC design with respect to “xn”, and (iii) “DesignRule(xn)” is a dimensional value specified by the integration design rule represented by “xn”. In table 350, for example, “RuleSlack” for “rule A/B” is calculated by subtracting 8 nm, the “RuleValue” for “rule A/B”, from 8 nm, the “DesignValue” for the separation of
RuleRisk(x n)=MaxRisk−RuleSlack(x n),
wherein:
RuleRisk(x n)=0 if MaxRisk≤RuleSlack(x n), Expression 3
and wherein (i) “MaxRisk” is an artificial value that is set with the objective of capping the risk associated with the application of one or more design rules to an IC design and (ii) “RuleSlack(xn)” is the design rule slack with respect to “xn”. In table 350, for example, “RuleRisk” for “rule A/B” is calculated by subtracting 0 nm, the “RuleSlack” for “rule A/B”, from 6 nm, the “MaxRisk” value, to yield a “RuleRisk” of 6. In the embodiment depicted in
RuleRiskSum(y)=Σn=1 m RuleRisk(x n)
wherein (i) “y” represents an IC feature for which IC model verification logic 132 is characterizing risk (e.g., IC feature 305), (ii) “RuleRisk(xn)” represents risk associated with the dimensional value specified by the IC design for a specific application of an integration design rule, “xn” (e.g., “RuleRisk” for “rule A/B” or “RuleRisk” for “rule A/C” or “RuleRisk” for “rule A/D”), and (iii) represents each specific application of an integration design rule to IC feature “y”. In
RuleRiskSum(A)=RuleRisk(A/B)+RuleRisk(A/C)+RuleRisk(A/D), Expression 5
wherein “A”, “B”,“C”, and “D” respectively denote IC features 305, 310, 315, and 320, and wherein “A/B”,“A/C”, and “A/D” each represent a specific applications of a respective integration design rule. In other words, “RuleRiskSum(A)” is obtained by summing the values listed in
RuleRisk(x n)=λn(MaxRisk−Rule Slack(x n)),
wherein “λn,” is a weighting coefficient based, at least in part, on the type of integration design rule corresponding to “xn,” and/or one or more qualities of the IC features to which the design rule is applied (e.g., one or more of the identify of “y”, the identity of any other IC feature to which the “DesignValue” applies, and/or a location of the IC features on the IC). In other embodiments, weighting integration design rules is achieved by weighting “RuleRisk(xn)” utilizing a modified version of
RuleRiskSum(y)=Σn=1 mλnRuleRisk(x n).
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US10769006B2 (en) | 2018-07-31 | 2020-09-08 | Cisco Technology, Inc. | Ensemble risk assessment method for networked devices |
US11188687B2 (en) * | 2018-11-09 | 2021-11-30 | The Boeing Company | Rule compliance checking and design generation with rule access security |
US11042688B1 (en) * | 2020-05-27 | 2021-06-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of certifying safety levels of semiconductor memories in integrated circuits |
CN112818629B (en) * | 2020-12-31 | 2023-06-02 | 广东省大湾区集成电路与系统应用研究院 | Planar transistor design method and planar transistor |
Citations (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5984510A (en) * | 1996-11-01 | 1999-11-16 | Motorola Inc. | Automatic synthesis of standard cell layouts |
US6189132B1 (en) * | 1998-04-09 | 2001-02-13 | International Business Machines Corporation | Design rule correction system and method |
US6480137B2 (en) * | 2001-02-28 | 2002-11-12 | Texas Instruments Incorporated | Method of generating matched capacitor arrays |
US6735749B2 (en) * | 2002-03-21 | 2004-05-11 | Sun Microsystems, Inc. | (Design rule check)/(electrical rule check) algorithms using a system resolution |
US20050251771A1 (en) | 2004-05-07 | 2005-11-10 | Mentor Graphics Corporation | Integrated circuit layout design methodology with process variation bands |
US6973637B2 (en) * | 2003-05-12 | 2005-12-06 | Agere Systems Inc. | Process for the selective control of feature size in lithographic processing |
US7155689B2 (en) | 2003-10-07 | 2006-12-26 | Magma Design Automation, Inc. | Design-manufacturing interface via a unified model |
US20070011637A1 (en) * | 2005-06-06 | 2007-01-11 | Alexander Seidl | Method and system for performing local geometrical operation on a hierarchical layout of a semiconductor device |
US20070022400A1 (en) * | 2005-07-19 | 2007-01-25 | Matsushita Electric Industrial Co., Ltd. | Method, program, and apparatus for designing layout of semiconductor integrated circuit |
US20070118824A1 (en) * | 2005-11-23 | 2007-05-24 | Samsung Electronics Co., Ltd. | Methods, systems, and computer program products for improving yield in integrated circuit device fabrication and related devices |
US7284231B2 (en) * | 2004-12-21 | 2007-10-16 | Freescale Semiconductor, Inc. | Layout modification using multilayer-based constraints |
US20090055789A1 (en) * | 2005-07-26 | 2009-02-26 | Mcilrath Lisa G | Methods and systems for computer aided design of 3d integrated circuits |
US7506277B1 (en) | 2005-07-28 | 2009-03-17 | Cadence Design Systems, Inc. | Method and mechanism for implementing DFM aware cells for an electronic design |
US7681170B2 (en) * | 2006-02-09 | 2010-03-16 | Qualcomm Incorporated | Method and apparatus for insertion of filling forms within a design layout |
US7689951B2 (en) | 2004-08-31 | 2010-03-30 | Freescale Semiconductor, Inc. | Design rule checking system and method, for checking compliance of an integrated circuit design with a plurality of design rules |
US7689948B1 (en) | 2007-02-24 | 2010-03-30 | Cadence Design Systems, Inc. | System and method for model-based scoring and yield prediction |
US7707528B1 (en) | 2007-02-24 | 2010-04-27 | Cadence Design Systems, Inc. | System and method for performing verification based upon both rules and models |
US20100109005A1 (en) * | 2008-10-31 | 2010-05-06 | Michael Grillberger | Semiconductor device comprising a distributed interconnected sensor structure for die internal monitoring purposes |
US7724028B1 (en) * | 2008-04-11 | 2010-05-25 | Xilinx, Inc. | Clocking for a hardwired core embedded in a host integrated circuit device |
US7735053B2 (en) * | 2006-06-29 | 2010-06-08 | Sharp Kabushiki Kaisha | Correction method and correction system for design data or mask data, validation method and validation system for design data or mask data, yield estimation method for semiconductor integrated circuit, method for improving design rule, mask production method, and semiconductor integrated circuit production method |
US7802210B2 (en) * | 2006-01-23 | 2010-09-21 | Samsung Electronics Co., Ltd. | Methods and systems for analyzing layouts of semiconductor integrated circuit devices |
US7818694B2 (en) | 2006-06-19 | 2010-10-19 | International Business Machines Corporation | IC layout optimization to improve yield |
US7873929B2 (en) * | 2006-08-14 | 2011-01-18 | The Regents Of The University Of California | Method, apparatus and system for designing an integrated circuit including generating at least one auxiliary pattern for cell-based optical proximity correction |
USRE42294E1 (en) * | 2000-06-30 | 2011-04-12 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit designing method and system using a design rule modification |
US7962886B1 (en) * | 2006-12-08 | 2011-06-14 | Cadence Design Systems, Inc. | Method and system for generating design constraints |
US7987442B2 (en) * | 2004-09-06 | 2011-07-26 | Mentor Graphics Corporation | Fault dictionaries for integrated circuit yield and quality analysis methods and systems |
US8001512B1 (en) * | 2007-06-26 | 2011-08-16 | Cadence Design Systems, Inc. | Method and system for implementing context simulation |
US8095894B2 (en) | 1999-03-04 | 2012-01-10 | Panasonic Corporation | Changing a design rule for forming LSI pattern based on evaluating effectiveness of optical proximity corrected patterns |
US8103982B2 (en) | 2005-05-20 | 2012-01-24 | Cadence Design Systems, Inc. | System and method for statistical design rule checking |
US8173491B2 (en) * | 2008-12-18 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Standard cell architecture and methods with variable design rules |
US8453103B2 (en) * | 2010-12-03 | 2013-05-28 | Synopsys, Inc. | Real time DRC assistance for manual layout editing |
US8464189B2 (en) * | 2004-10-29 | 2013-06-11 | International Business Machines Corporation | Technology migration for integrated circuits with radical design restrictions |
US8473874B1 (en) * | 2011-08-22 | 2013-06-25 | Cadence Design Systems, Inc. | Method and apparatus for automatically fixing double patterning loop violations |
US8490038B1 (en) | 2012-08-27 | 2013-07-16 | Cadence Dsign Systems, Inc. | System and method for automatic placement of contact cuts and similar structures in integrated circuit layouts |
US8510699B1 (en) * | 2012-03-09 | 2013-08-13 | International Business Machines Corporation | Performance driven layout optimization using morphing of a basis set of representative layouts |
US8516402B1 (en) * | 2011-08-22 | 2013-08-20 | Cadence Design Systems, Inc. | Method and apparatus for automatically fixing double patterning loop violations |
US8612919B2 (en) * | 2006-11-20 | 2013-12-17 | Mentor Graphics Corporation | Model-based design verification |
US20140045334A1 (en) * | 2012-08-09 | 2014-02-13 | Jin Choi | Methods of Providing Photolithography Patterns Using Feature Parameters, Systems and Computer Program Products Implementing the Same |
US8656323B2 (en) | 2011-02-22 | 2014-02-18 | Kla-Tencor Corporation | Based device risk assessment |
US8683392B2 (en) * | 2011-07-21 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double patterning methodology |
US8707223B2 (en) * | 2011-09-19 | 2014-04-22 | Texas Instruments Incorporated | Method for ensuring DPT compliance with autorouted metal layers |
US8735050B2 (en) * | 2012-08-06 | 2014-05-27 | GlobalFoundries, Inc. | Integrated circuits and methods for fabricating integrated circuits using double patterning processes |
US8751974B2 (en) * | 2009-09-29 | 2014-06-10 | The Regents Of The University Of California | Layout decomposition for double patterning lithography |
US8898617B2 (en) * | 2007-06-27 | 2014-11-25 | Cadence Design Systems, Inc. | Robust design using manufacturability models |
US8966424B2 (en) * | 2007-03-07 | 2015-02-24 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US9122832B2 (en) * | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US20150302129A1 (en) * | 2014-04-17 | 2015-10-22 | Qualcomm Incorporated | Mask assignment technique for m1 metal layer in triple-patterning lithography |
US20150356232A1 (en) * | 2014-06-06 | 2015-12-10 | Synopsys, Inc. | Method and System for Generating a Circuit Design, Method for Calibration of an Inspection Apparatus and Method for Process Control and Yield Management |
US20160035615A1 (en) * | 2014-07-31 | 2016-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods Of Manufacturing A Semiconductor Device |
US9489479B2 (en) | 2012-05-04 | 2016-11-08 | Asml Netherlands B.V. | Rule and lithographic process co-optimization |
US20170039308A1 (en) | 2015-08-03 | 2017-02-09 | Synopsys, Inc. | Pre-Silicon Design Rule Evaluation |
US9627370B1 (en) * | 2016-04-04 | 2017-04-18 | Pdf Solutions, Inc. | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells |
US20170228491A1 (en) * | 2016-02-10 | 2017-08-10 | Globalfoundries Inc. | Rule and process assumption co-optimization using feature-specific layout-based statistical analyses |
US20180107781A1 (en) | 2015-04-15 | 2018-04-19 | Sage Design Automation Ltd. | Automatic Generation of Test Layouts for Verifying a DRC Deck |
US20180157784A1 (en) * | 2016-04-04 | 2018-06-07 | Kla-Tencor Corporation | Process Compatibility Improvement by Fill Factor Modulation |
US20180211947A1 (en) * | 2017-01-23 | 2018-07-26 | International Business Machines Corporation | Standard cell architecture with at least one gate contact over an active area |
US20180232478A1 (en) * | 2016-01-11 | 2018-08-16 | Kla-Tencor Corporation | Hot Spot and Process Window Monitoring |
US10083272B2 (en) * | 2016-08-12 | 2018-09-25 | International Business Machines Corporation | Integrated circuit design layout optimizer based on process variation and failure mechanism |
US10096530B1 (en) * | 2017-06-28 | 2018-10-09 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells |
US20190072845A1 (en) * | 2017-09-06 | 2019-03-07 | International Business Machines Corporation | Semiconductor fabrication design rule loophole checking for design for manufacturability optimization |
US10228320B1 (en) * | 2014-08-08 | 2019-03-12 | KLA—Tencor Corporation | Achieving a small pattern placement error in metrology targets |
US20190095551A1 (en) | 2017-09-25 | 2019-03-28 | International Business Machines Corporation | Optimizing integrated circuit designs based on interactions between multiple integration design rules |
US20190311071A1 (en) | 2018-04-10 | 2019-10-10 | International Business Machines Corporation | Incorporation of process variation contours in design rule and risk estimation aspects of design for manufacturability to increase fabrication yield |
-
2017
- 2017-09-25 US US15/714,086 patent/US10628544B2/en not_active Expired - Fee Related
- 2017-11-17 US US15/816,210 patent/US10592627B2/en not_active Expired - Fee Related
Patent Citations (66)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5984510A (en) * | 1996-11-01 | 1999-11-16 | Motorola Inc. | Automatic synthesis of standard cell layouts |
US6189132B1 (en) * | 1998-04-09 | 2001-02-13 | International Business Machines Corporation | Design rule correction system and method |
US8095894B2 (en) | 1999-03-04 | 2012-01-10 | Panasonic Corporation | Changing a design rule for forming LSI pattern based on evaluating effectiveness of optical proximity corrected patterns |
USRE42294E1 (en) * | 2000-06-30 | 2011-04-12 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit designing method and system using a design rule modification |
US6480137B2 (en) * | 2001-02-28 | 2002-11-12 | Texas Instruments Incorporated | Method of generating matched capacitor arrays |
US6735749B2 (en) * | 2002-03-21 | 2004-05-11 | Sun Microsystems, Inc. | (Design rule check)/(electrical rule check) algorithms using a system resolution |
US6973637B2 (en) * | 2003-05-12 | 2005-12-06 | Agere Systems Inc. | Process for the selective control of feature size in lithographic processing |
US7155689B2 (en) | 2003-10-07 | 2006-12-26 | Magma Design Automation, Inc. | Design-manufacturing interface via a unified model |
US20050251771A1 (en) | 2004-05-07 | 2005-11-10 | Mentor Graphics Corporation | Integrated circuit layout design methodology with process variation bands |
US8799830B2 (en) | 2004-05-07 | 2014-08-05 | Mentor Graphics Corporation | Integrated circuit layout design methodology with process variation bands |
US7689951B2 (en) | 2004-08-31 | 2010-03-30 | Freescale Semiconductor, Inc. | Design rule checking system and method, for checking compliance of an integrated circuit design with a plurality of design rules |
US7987442B2 (en) * | 2004-09-06 | 2011-07-26 | Mentor Graphics Corporation | Fault dictionaries for integrated circuit yield and quality analysis methods and systems |
US8464189B2 (en) * | 2004-10-29 | 2013-06-11 | International Business Machines Corporation | Technology migration for integrated circuits with radical design restrictions |
US7284231B2 (en) * | 2004-12-21 | 2007-10-16 | Freescale Semiconductor, Inc. | Layout modification using multilayer-based constraints |
US8103982B2 (en) | 2005-05-20 | 2012-01-24 | Cadence Design Systems, Inc. | System and method for statistical design rule checking |
US20070011637A1 (en) * | 2005-06-06 | 2007-01-11 | Alexander Seidl | Method and system for performing local geometrical operation on a hierarchical layout of a semiconductor device |
US20070022400A1 (en) * | 2005-07-19 | 2007-01-25 | Matsushita Electric Industrial Co., Ltd. | Method, program, and apparatus for designing layout of semiconductor integrated circuit |
US20090055789A1 (en) * | 2005-07-26 | 2009-02-26 | Mcilrath Lisa G | Methods and systems for computer aided design of 3d integrated circuits |
US7506277B1 (en) | 2005-07-28 | 2009-03-17 | Cadence Design Systems, Inc. | Method and mechanism for implementing DFM aware cells for an electronic design |
US20070118824A1 (en) * | 2005-11-23 | 2007-05-24 | Samsung Electronics Co., Ltd. | Methods, systems, and computer program products for improving yield in integrated circuit device fabrication and related devices |
US7802210B2 (en) * | 2006-01-23 | 2010-09-21 | Samsung Electronics Co., Ltd. | Methods and systems for analyzing layouts of semiconductor integrated circuit devices |
US7681170B2 (en) * | 2006-02-09 | 2010-03-16 | Qualcomm Incorporated | Method and apparatus for insertion of filling forms within a design layout |
US7818694B2 (en) | 2006-06-19 | 2010-10-19 | International Business Machines Corporation | IC layout optimization to improve yield |
US7735053B2 (en) * | 2006-06-29 | 2010-06-08 | Sharp Kabushiki Kaisha | Correction method and correction system for design data or mask data, validation method and validation system for design data or mask data, yield estimation method for semiconductor integrated circuit, method for improving design rule, mask production method, and semiconductor integrated circuit production method |
US7873929B2 (en) * | 2006-08-14 | 2011-01-18 | The Regents Of The University Of California | Method, apparatus and system for designing an integrated circuit including generating at least one auxiliary pattern for cell-based optical proximity correction |
US8612919B2 (en) * | 2006-11-20 | 2013-12-17 | Mentor Graphics Corporation | Model-based design verification |
US7962886B1 (en) * | 2006-12-08 | 2011-06-14 | Cadence Design Systems, Inc. | Method and system for generating design constraints |
US7689948B1 (en) | 2007-02-24 | 2010-03-30 | Cadence Design Systems, Inc. | System and method for model-based scoring and yield prediction |
US7707528B1 (en) | 2007-02-24 | 2010-04-27 | Cadence Design Systems, Inc. | System and method for performing verification based upon both rules and models |
US8966424B2 (en) * | 2007-03-07 | 2015-02-24 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US8001512B1 (en) * | 2007-06-26 | 2011-08-16 | Cadence Design Systems, Inc. | Method and system for implementing context simulation |
US8898617B2 (en) * | 2007-06-27 | 2014-11-25 | Cadence Design Systems, Inc. | Robust design using manufacturability models |
US7724028B1 (en) * | 2008-04-11 | 2010-05-25 | Xilinx, Inc. | Clocking for a hardwired core embedded in a host integrated circuit device |
US9122832B2 (en) * | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US20100109005A1 (en) * | 2008-10-31 | 2010-05-06 | Michael Grillberger | Semiconductor device comprising a distributed interconnected sensor structure for die internal monitoring purposes |
US8173491B2 (en) * | 2008-12-18 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Standard cell architecture and methods with variable design rules |
US8751974B2 (en) * | 2009-09-29 | 2014-06-10 | The Regents Of The University Of California | Layout decomposition for double patterning lithography |
US8453103B2 (en) * | 2010-12-03 | 2013-05-28 | Synopsys, Inc. | Real time DRC assistance for manual layout editing |
US8656323B2 (en) | 2011-02-22 | 2014-02-18 | Kla-Tencor Corporation | Based device risk assessment |
US8683392B2 (en) * | 2011-07-21 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Double patterning methodology |
US8473874B1 (en) * | 2011-08-22 | 2013-06-25 | Cadence Design Systems, Inc. | Method and apparatus for automatically fixing double patterning loop violations |
US8516402B1 (en) * | 2011-08-22 | 2013-08-20 | Cadence Design Systems, Inc. | Method and apparatus for automatically fixing double patterning loop violations |
US8707223B2 (en) * | 2011-09-19 | 2014-04-22 | Texas Instruments Incorporated | Method for ensuring DPT compliance with autorouted metal layers |
US8510699B1 (en) * | 2012-03-09 | 2013-08-13 | International Business Machines Corporation | Performance driven layout optimization using morphing of a basis set of representative layouts |
US9489479B2 (en) | 2012-05-04 | 2016-11-08 | Asml Netherlands B.V. | Rule and lithographic process co-optimization |
US8735050B2 (en) * | 2012-08-06 | 2014-05-27 | GlobalFoundries, Inc. | Integrated circuits and methods for fabricating integrated circuits using double patterning processes |
US20140045334A1 (en) * | 2012-08-09 | 2014-02-13 | Jin Choi | Methods of Providing Photolithography Patterns Using Feature Parameters, Systems and Computer Program Products Implementing the Same |
US8490038B1 (en) | 2012-08-27 | 2013-07-16 | Cadence Dsign Systems, Inc. | System and method for automatic placement of contact cuts and similar structures in integrated circuit layouts |
US20150302129A1 (en) * | 2014-04-17 | 2015-10-22 | Qualcomm Incorporated | Mask assignment technique for m1 metal layer in triple-patterning lithography |
US20150356232A1 (en) * | 2014-06-06 | 2015-12-10 | Synopsys, Inc. | Method and System for Generating a Circuit Design, Method for Calibration of an Inspection Apparatus and Method for Process Control and Yield Management |
US20160035615A1 (en) * | 2014-07-31 | 2016-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods Of Manufacturing A Semiconductor Device |
US10228320B1 (en) * | 2014-08-08 | 2019-03-12 | KLA—Tencor Corporation | Achieving a small pattern placement error in metrology targets |
US20180107781A1 (en) | 2015-04-15 | 2018-04-19 | Sage Design Automation Ltd. | Automatic Generation of Test Layouts for Verifying a DRC Deck |
US20170039308A1 (en) | 2015-08-03 | 2017-02-09 | Synopsys, Inc. | Pre-Silicon Design Rule Evaluation |
US20180232478A1 (en) * | 2016-01-11 | 2018-08-16 | Kla-Tencor Corporation | Hot Spot and Process Window Monitoring |
US20170228491A1 (en) * | 2016-02-10 | 2017-08-10 | Globalfoundries Inc. | Rule and process assumption co-optimization using feature-specific layout-based statistical analyses |
US20180157784A1 (en) * | 2016-04-04 | 2018-06-07 | Kla-Tencor Corporation | Process Compatibility Improvement by Fill Factor Modulation |
US9627370B1 (en) * | 2016-04-04 | 2017-04-18 | Pdf Solutions, Inc. | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells |
US10083272B2 (en) * | 2016-08-12 | 2018-09-25 | International Business Machines Corporation | Integrated circuit design layout optimizer based on process variation and failure mechanism |
US20180211947A1 (en) * | 2017-01-23 | 2018-07-26 | International Business Machines Corporation | Standard cell architecture with at least one gate contact over an active area |
US20180211948A1 (en) * | 2017-01-23 | 2018-07-26 | International Business Machines Corporation | Standard cell architecture with at least one gate contact over an active area |
US10096530B1 (en) * | 2017-06-28 | 2018-10-09 | Pdf Solutions, Inc. | Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells |
US20190072845A1 (en) * | 2017-09-06 | 2019-03-07 | International Business Machines Corporation | Semiconductor fabrication design rule loophole checking for design for manufacturability optimization |
US20190072846A1 (en) * | 2017-09-06 | 2019-03-07 | International Business Machines Corporation | Semiconductor fabrication design rule loophole checking for design for manufacturability optimization |
US20190095551A1 (en) | 2017-09-25 | 2019-03-28 | International Business Machines Corporation | Optimizing integrated circuit designs based on interactions between multiple integration design rules |
US20190311071A1 (en) | 2018-04-10 | 2019-10-10 | International Business Machines Corporation | Incorporation of process variation contours in design rule and risk estimation aspects of design for manufacturability to increase fabrication yield |
Non-Patent Citations (4)
Title |
---|
Appendix P, List of IBM Patents or Patent Applications Treated as Related, 2 pages, dated Nov. 29, 2017. |
Chidambarrao et al., "Optimizing Integrated Circuit Designs Based on Interactions Between Multiple Integration Design Rules", U.S. Appl. No. 15/816,210, filed Nov. 17, 2017, 35 pages. |
Clevenger et al., "Integrated Circuit Design Layout Optimizer Based on Process Variation and Failure Mechanism", U.S. Appl. No. 15/235,273, filed Aug. 12, 2016, 35 pages. |
Mukherjee et al., "Leveraging pre-silicon data to diagnose out-of-specification failures in mixed-signal circuits", DAC '14, Jun. 1-5, 2014, San Francisco, CA, USA, Copyright 2014 ACM, 6 pages. |
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