JP2007511892A5 - - Google Patents

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Publication number
JP2007511892A5
JP2007511892A5 JP2006521913A JP2006521913A JP2007511892A5 JP 2007511892 A5 JP2007511892 A5 JP 2007511892A5 JP 2006521913 A JP2006521913 A JP 2006521913A JP 2006521913 A JP2006521913 A JP 2006521913A JP 2007511892 A5 JP2007511892 A5 JP 2007511892A5
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JP
Japan
Prior art keywords
silicon
layer
containing layer
deposited
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006521913A
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English (en)
Japanese (ja)
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JP2007511892A (ja
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Publication date
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Priority claimed from PCT/US2004/023503 external-priority patent/WO2005013326A2/en
Publication of JP2007511892A publication Critical patent/JP2007511892A/ja
Publication of JP2007511892A5 publication Critical patent/JP2007511892A5/ja
Pending legal-status Critical Current

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JP2006521913A 2003-07-30 2004-07-21 緩和シリコンゲルマニウム層のエピタキシャル成長 Pending JP2007511892A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US49102903P 2003-07-30 2003-07-30
PCT/US2004/023503 WO2005013326A2 (en) 2003-07-30 2004-07-21 Epitaxial growth of relaxed silicon germanium layers

Publications (2)

Publication Number Publication Date
JP2007511892A JP2007511892A (ja) 2007-05-10
JP2007511892A5 true JP2007511892A5 (enExample) 2007-08-09

Family

ID=34115457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006521913A Pending JP2007511892A (ja) 2003-07-30 2004-07-21 緩和シリコンゲルマニウム層のエピタキシャル成長

Country Status (6)

Country Link
US (2) US7514372B2 (enExample)
EP (1) EP1649495A2 (enExample)
JP (1) JP2007511892A (enExample)
KR (1) KR20060039915A (enExample)
TW (1) TWI382456B (enExample)
WO (1) WO2005013326A2 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US7598515B2 (en) * 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US7531828B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7612366B2 (en) * 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US7901968B2 (en) * 2006-03-23 2011-03-08 Asm America, Inc. Heteroepitaxial deposition over an oxidized surface
US7785995B2 (en) * 2006-05-09 2010-08-31 Asm America, Inc. Semiconductor buffer structures
EP2021533A4 (en) * 2006-05-15 2010-01-06 Arise Technologies Corp TIEFTEMPERATUR DOTIER PROCEDURE FOR SILICONE WATER DEVICES
US7608526B2 (en) * 2006-07-24 2009-10-27 Asm America, Inc. Strained layers within semiconductor buffer structures
KR101233105B1 (ko) 2008-08-27 2013-02-15 소이텍 선택되거나 제어된 격자 파라미터들을 갖는 반도체 물질층들을 이용하여 반도체 구조물들 또는 소자들을 제조하는 방법
US8039371B2 (en) * 2009-07-01 2011-10-18 International Business Machines Corporation Reduced defect semiconductor-on-insulator hetero-structures
SG2014014146A (en) * 2009-11-18 2014-07-30 Soitec Silicon On Insulator Methods of fabricating semiconductor structures and devices using glass bonding layers, and semiconductor structures and devices formed by such methods
FR2968678B1 (fr) 2010-12-08 2015-11-20 Soitec Silicon On Insulator Procédés pour former des matériaux a base de nitrure du groupe iii et structures formées par ces procédés
FR2968830B1 (fr) 2010-12-08 2014-03-21 Soitec Silicon On Insulator Couches matricielles ameliorees pour le depot heteroepitaxial de materiaux semiconducteurs de nitrure iii en utilisant des procedes hvpe
US9023721B2 (en) 2010-11-23 2015-05-05 Soitec Methods of forming bulk III-nitride materials on metal-nitride growth template layers, and structures formed by such methods
US9127345B2 (en) 2012-03-06 2015-09-08 Asm America, Inc. Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent
US9171715B2 (en) 2012-09-05 2015-10-27 Asm Ip Holding B.V. Atomic layer deposition of GeO2
US9218963B2 (en) 2013-12-19 2015-12-22 Asm Ip Holding B.V. Cyclical deposition of germanium
US9536746B2 (en) * 2014-03-13 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Recess and epitaxial layer to improve transistor performance
US9343303B2 (en) 2014-03-20 2016-05-17 Samsung Electronics Co., Ltd. Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices
EP3221885B1 (en) * 2014-11-18 2019-10-23 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
US10431695B2 (en) 2017-12-20 2019-10-01 Micron Technology, Inc. Transistors comprising at lease one of GaP, GaN, and GaAs
US10825816B2 (en) 2017-12-28 2020-11-03 Micron Technology, Inc. Recessed access devices and DRAM constructions
US10734527B2 (en) 2018-02-06 2020-08-04 Micron Technology, Inc. Transistors comprising a pair of source/drain regions having a channel there-between
US12543516B2 (en) * 2022-02-02 2026-02-03 Asm Ip Holding B.V. Methods of forming silicon germanium structures
CN119487611A (zh) * 2022-07-01 2025-02-18 微传科技有限公司 利用外延工序的半导体器件制造方法及用于其的制造装置

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256550A (en) * 1988-11-29 1993-10-26 Hewlett-Packard Company Fabricating a semiconductor device with strained Si1-x Gex layer
US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US5221413A (en) * 1991-04-24 1993-06-22 At&T Bell Laboratories Method for making low defect density semiconductor heterostructure and devices made thereby
JP2877108B2 (ja) * 1996-12-04 1999-03-31 日本電気株式会社 半導体装置およびその製造方法
JP2953567B2 (ja) 1997-02-06 1999-09-27 日本電気株式会社 半導体装置の製造方法
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
EP1016129B2 (en) * 1997-06-24 2009-06-10 Massachusetts Institute Of Technology Controlling threading dislocation densities using graded layers and planarization
WO2000004357A1 (en) * 1998-07-15 2000-01-27 Smithsonian Astrophysical Observatory Epitaxial germanium temperature sensor
FR2783254B1 (fr) 1998-09-10 2000-11-10 France Telecom Procede d'obtention d'une couche de germanium monocristallin sur un substrat de silicium monocristallin,et produits obtenus
US6350993B1 (en) * 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
JP2004507084A (ja) * 2000-08-16 2004-03-04 マサチューセッツ　インスティテュート　オブ　テクノロジー グレーデッドエピタキシャル成長を用いた半導体品の製造プロセス
US6995076B2 (en) * 2000-09-05 2006-02-07 The Regents Of The University Of California Relaxed SiGe films by surfactant mediation
KR100385857B1 (ko) * 2000-12-27 2003-06-02 한국전자통신연구원 SiGe MODFET 소자 제조방법
WO2002080244A2 (en) 2001-02-12 2002-10-10 Asm America, Inc. Improved process for deposition of semiconductor films
US6593625B2 (en) * 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6855649B2 (en) * 2001-06-12 2005-02-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6844213B2 (en) * 2001-06-14 2005-01-18 Integrated Sensing Systems Process of forming a microneedle and microneedle formed thereby
JP2003007621A (ja) * 2001-06-21 2003-01-10 Nikko Materials Co Ltd ＧａＮ系化合物半導体結晶の製造方法
US7052622B2 (en) * 2001-10-17 2006-05-30 Applied Materials, Inc. Method for measuring etch rates during a release process
US6875279B2 (en) 2001-11-16 2005-04-05 International Business Machines Corporation Single reactor, multi-pressure chemical vapor deposition for semiconductor devices
JP3970011B2 (ja) * 2001-12-11 2007-09-05 シャープ株式会社 半導体装置及びその製造方法
US20030124818A1 (en) 2001-12-28 2003-07-03 Applied Materials, Inc. Method and apparatus for forming silicon containing films
US6723622B2 (en) 2002-02-21 2004-04-20 Intel Corporation Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer
EP1502285A2 (en) 2002-05-07 2005-02-02 ASM America, Inc. Silicon-on-insulator structures and methods
WO2004001857A1 (en) 2002-06-19 2003-12-31 Massachusetts Institute Of Technology Ge photodetectors
US7238595B2 (en) 2003-03-13 2007-07-03 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US7132338B2 (en) 2003-10-10 2006-11-07 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process

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