JP2007294488A - 半導体装置、電子部品、及び半導体装置の製造方法 - Google Patents

半導体装置、電子部品、及び半導体装置の製造方法 Download PDF

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Publication number
JP2007294488A
JP2007294488A JP2006117074A JP2006117074A JP2007294488A JP 2007294488 A JP2007294488 A JP 2007294488A JP 2006117074 A JP2006117074 A JP 2006117074A JP 2006117074 A JP2006117074 A JP 2006117074A JP 2007294488 A JP2007294488 A JP 2007294488A
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JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
external connection
semiconductor
connection terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006117074A
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English (en)
Japanese (ja)
Other versions
JP2007294488A5 (https=
Inventor
Hidenori Takayanagi
秀則 高柳
Yukiharu Takeuchi
之治 竹内
Hironori Toyazaki
宏規 戸矢▲崎▼
Toshio Gomyo
利雄 五明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2006117074A priority Critical patent/JP2007294488A/ja
Priority to KR1020070037328A priority patent/KR20070104236A/ko
Priority to US11/736,926 priority patent/US8525355B2/en
Publication of JP2007294488A publication Critical patent/JP2007294488A/ja
Publication of JP2007294488A5 publication Critical patent/JP2007294488A5/ja
Priority to US13/368,900 priority patent/US20120133056A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07502—Connecting or disconnecting of bond wires using an auxiliary member
    • H10W72/07504—Connecting or disconnecting of bond wires using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2006117074A 2006-04-20 2006-04-20 半導体装置、電子部品、及び半導体装置の製造方法 Pending JP2007294488A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2006117074A JP2007294488A (ja) 2006-04-20 2006-04-20 半導体装置、電子部品、及び半導体装置の製造方法
KR1020070037328A KR20070104236A (ko) 2006-04-20 2007-04-17 반도체 장치, 전자 장치, 및 반도체 장치의 제조 방법
US11/736,926 US8525355B2 (en) 2006-04-20 2007-04-18 Semiconductor device, electronic apparatus and semiconductor device fabricating method
US13/368,900 US20120133056A1 (en) 2006-04-20 2012-02-08 Semiconductor device, electronic apparatus and semiconductor device fabricating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006117074A JP2007294488A (ja) 2006-04-20 2006-04-20 半導体装置、電子部品、及び半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2007294488A true JP2007294488A (ja) 2007-11-08
JP2007294488A5 JP2007294488A5 (https=) 2009-04-09

Family

ID=38618728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006117074A Pending JP2007294488A (ja) 2006-04-20 2006-04-20 半導体装置、電子部品、及び半導体装置の製造方法

Country Status (3)

Country Link
US (2) US8525355B2 (https=)
JP (1) JP2007294488A (https=)
KR (1) KR20070104236A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8664757B2 (en) 2010-07-12 2014-03-04 Samsung Electronics Co., Ltd. High density chip stacked package, package-on-package and method of fabricating the same

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KR100886717B1 (ko) * 2007-10-16 2009-03-04 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
US8014166B2 (en) * 2008-09-06 2011-09-06 Broadpak Corporation Stacking integrated circuits containing serializer and deserializer blocks using through silicon via
JP5918664B2 (ja) * 2012-09-10 2016-05-18 株式会社東芝 積層型半導体装置の製造方法
US9368422B2 (en) * 2012-12-20 2016-06-14 Nvidia Corporation Absorbing excess under-fill flow with a solder trench
JP2018101699A (ja) * 2016-12-20 2018-06-28 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、固体撮像装置の製造方法および電子機器
US20200118991A1 (en) * 2018-10-15 2020-04-16 Intel Corporation Pre-patterned fine-pitch bond pad interposer

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JP2001196526A (ja) * 2000-01-06 2001-07-19 Seiko Epson Corp マルチベアチップ実装体、マルチチップパッケージ、半導体装置、ならびに電子機器
JP2003303919A (ja) * 2002-04-10 2003-10-24 Hitachi Ltd 半導体装置及びその製造方法
JP2004031946A (ja) * 2003-06-05 2004-01-29 Nec Electronics Corp 半導体装置及びその製造方法
WO2004034433A2 (en) * 2002-10-08 2004-04-22 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
JP2004179622A (ja) * 2002-11-15 2004-06-24 Renesas Technology Corp 半導体装置の製造方法
JP2005268533A (ja) * 2004-03-18 2005-09-29 Shinko Electric Ind Co Ltd 積層型半導体装置

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FR2439478A1 (fr) * 1978-10-19 1980-05-16 Cii Honeywell Bull Boitier plat pour dispositifs a circuits integres
JP3007833B2 (ja) 1995-12-12 2000-02-07 富士通株式会社 半導体装置及びその製造方法及びリードフレーム及びその製造方法
CN1202983A (zh) * 1995-11-28 1998-12-23 株式会社日立制作所 半导体器件及其制造方法以及装配基板
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
JP3638771B2 (ja) * 1997-12-22 2005-04-13 沖電気工業株式会社 半導体装置
WO2000078887A1 (en) * 1999-06-18 2000-12-28 Hitachi Chemical Company, Ltd. Adhesive, adhesive member, circuit substrate for semiconductor mounting having adhesive member, and semiconductor device containing the same
US6605875B2 (en) * 1999-12-30 2003-08-12 Intel Corporation Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size
US20020125568A1 (en) * 2000-01-14 2002-09-12 Tongbi Jiang Method Of Fabricating Chip-Scale Packages And Resulting Structures
JP3752949B2 (ja) * 2000-02-28 2006-03-08 日立化成工業株式会社 配線基板及び半導体装置
JP2002040095A (ja) 2000-07-26 2002-02-06 Nec Corp 半導体装置及びその実装方法
US6468471B1 (en) * 2000-11-10 2002-10-22 Gary K. Loda System for, and method of, irradiating opposite sides of articles with optimal amounts of cumulative irradiation
US6753613B2 (en) * 2002-03-13 2004-06-22 Intel Corporation Stacked dice standoffs
US7560821B2 (en) 2005-03-24 2009-07-14 Sumitomo Bakelite Company, Ltd Area mount type semiconductor device, and die bonding resin composition and encapsulating resin composition used for the same

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Publication number Priority date Publication date Assignee Title
JP2001196526A (ja) * 2000-01-06 2001-07-19 Seiko Epson Corp マルチベアチップ実装体、マルチチップパッケージ、半導体装置、ならびに電子機器
JP2003303919A (ja) * 2002-04-10 2003-10-24 Hitachi Ltd 半導体装置及びその製造方法
WO2004034433A2 (en) * 2002-10-08 2004-04-22 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
JP2004179622A (ja) * 2002-11-15 2004-06-24 Renesas Technology Corp 半導体装置の製造方法
JP2004031946A (ja) * 2003-06-05 2004-01-29 Nec Electronics Corp 半導体装置及びその製造方法
JP2005268533A (ja) * 2004-03-18 2005-09-29 Shinko Electric Ind Co Ltd 積層型半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8664757B2 (en) 2010-07-12 2014-03-04 Samsung Electronics Co., Ltd. High density chip stacked package, package-on-package and method of fabricating the same

Also Published As

Publication number Publication date
US20120133056A1 (en) 2012-05-31
US8525355B2 (en) 2013-09-03
KR20070104236A (ko) 2007-10-25
US20070246842A1 (en) 2007-10-25

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