KR20070104236A - 반도체 장치, 전자 장치, 및 반도체 장치의 제조 방법 - Google Patents

반도체 장치, 전자 장치, 및 반도체 장치의 제조 방법 Download PDF

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Publication number
KR20070104236A
KR20070104236A KR1020070037328A KR20070037328A KR20070104236A KR 20070104236 A KR20070104236 A KR 20070104236A KR 1020070037328 A KR1020070037328 A KR 1020070037328A KR 20070037328 A KR20070037328 A KR 20070037328A KR 20070104236 A KR20070104236 A KR 20070104236A
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KR
South Korea
Prior art keywords
semiconductor chip
external connection
semiconductor device
semiconductor
connection terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020070037328A
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English (en)
Korean (ko)
Inventor
히데노리 다카야나기
유키하루 다케우치
히로키 도야자키
도시오 고묘
Original Assignee
신꼬오덴기 고교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 신꼬오덴기 고교 가부시키가이샤 filed Critical 신꼬오덴기 고교 가부시키가이샤
Publication of KR20070104236A publication Critical patent/KR20070104236A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07502—Connecting or disconnecting of bond wires using an auxiliary member
    • H10W72/07504—Connecting or disconnecting of bond wires using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
KR1020070037328A 2006-04-20 2007-04-17 반도체 장치, 전자 장치, 및 반도체 장치의 제조 방법 Withdrawn KR20070104236A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2006-00117074 2006-04-20
JP2006117074A JP2007294488A (ja) 2006-04-20 2006-04-20 半導体装置、電子部品、及び半導体装置の製造方法

Publications (1)

Publication Number Publication Date
KR20070104236A true KR20070104236A (ko) 2007-10-25

Family

ID=38618728

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070037328A Withdrawn KR20070104236A (ko) 2006-04-20 2007-04-17 반도체 장치, 전자 장치, 및 반도체 장치의 제조 방법

Country Status (3)

Country Link
US (2) US8525355B2 (https=)
JP (1) JP2007294488A (https=)
KR (1) KR20070104236A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100886717B1 (ko) * 2007-10-16 2009-03-04 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
US8664757B2 (en) 2010-07-12 2014-03-04 Samsung Electronics Co., Ltd. High density chip stacked package, package-on-package and method of fabricating the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8014166B2 (en) * 2008-09-06 2011-09-06 Broadpak Corporation Stacking integrated circuits containing serializer and deserializer blocks using through silicon via
JP5918664B2 (ja) * 2012-09-10 2016-05-18 株式会社東芝 積層型半導体装置の製造方法
US9368422B2 (en) * 2012-12-20 2016-06-14 Nvidia Corporation Absorbing excess under-fill flow with a solder trench
JP2018101699A (ja) * 2016-12-20 2018-06-28 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、固体撮像装置の製造方法および電子機器
US20200118991A1 (en) * 2018-10-15 2020-04-16 Intel Corporation Pre-patterned fine-pitch bond pad interposer

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FR2439478A1 (fr) * 1978-10-19 1980-05-16 Cii Honeywell Bull Boitier plat pour dispositifs a circuits integres
JP3007833B2 (ja) 1995-12-12 2000-02-07 富士通株式会社 半導体装置及びその製造方法及びリードフレーム及びその製造方法
CN1202983A (zh) * 1995-11-28 1998-12-23 株式会社日立制作所 半导体器件及其制造方法以及装配基板
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
JP3638771B2 (ja) * 1997-12-22 2005-04-13 沖電気工業株式会社 半導体装置
WO2000078887A1 (en) * 1999-06-18 2000-12-28 Hitachi Chemical Company, Ltd. Adhesive, adhesive member, circuit substrate for semiconductor mounting having adhesive member, and semiconductor device containing the same
US6605875B2 (en) * 1999-12-30 2003-08-12 Intel Corporation Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size
JP3832170B2 (ja) * 2000-01-06 2006-10-11 セイコーエプソン株式会社 マルチベアチップ実装体
US20020125568A1 (en) * 2000-01-14 2002-09-12 Tongbi Jiang Method Of Fabricating Chip-Scale Packages And Resulting Structures
JP3752949B2 (ja) * 2000-02-28 2006-03-08 日立化成工業株式会社 配線基板及び半導体装置
JP2002040095A (ja) 2000-07-26 2002-02-06 Nec Corp 半導体装置及びその実装方法
US6468471B1 (en) * 2000-11-10 2002-10-22 Gary K. Loda System for, and method of, irradiating opposite sides of articles with optimal amounts of cumulative irradiation
US6753613B2 (en) * 2002-03-13 2004-06-22 Intel Corporation Stacked dice standoffs
JP2003303919A (ja) * 2002-04-10 2003-10-24 Hitachi Ltd 半導体装置及びその製造方法
US7045887B2 (en) * 2002-10-08 2006-05-16 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
JP4159431B2 (ja) * 2002-11-15 2008-10-01 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2004031946A (ja) * 2003-06-05 2004-01-29 Nec Electronics Corp 半導体装置及びその製造方法
JP2005268533A (ja) * 2004-03-18 2005-09-29 Shinko Electric Ind Co Ltd 積層型半導体装置
US7560821B2 (en) 2005-03-24 2009-07-14 Sumitomo Bakelite Company, Ltd Area mount type semiconductor device, and die bonding resin composition and encapsulating resin composition used for the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100886717B1 (ko) * 2007-10-16 2009-03-04 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
US7705468B2 (en) 2007-10-16 2010-04-27 Hynix Semiconductor Inc. Stacked semiconductor package that prevents damage to semiconductor chip when wire-bonding and method for manufacturing the same
US8664757B2 (en) 2010-07-12 2014-03-04 Samsung Electronics Co., Ltd. High density chip stacked package, package-on-package and method of fabricating the same

Also Published As

Publication number Publication date
US20120133056A1 (en) 2012-05-31
US8525355B2 (en) 2013-09-03
US20070246842A1 (en) 2007-10-25
JP2007294488A (ja) 2007-11-08

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St.27 status event code: A-0-1-A10-A12-nap-PA0109

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St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

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