JP2007027563A - 高周波スイッチ回路を有する高周波装置 - Google Patents
高周波スイッチ回路を有する高周波装置 Download PDFInfo
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Abstract
【解決手段】 スイッチ回路11を構成する電界効果トランジスタFETが形成される化合物半導体基板1が絶縁部2を介して配置され、基板11に所要の正電位の電圧を印加することによって、歪みの低減を図ることができた。
【選択図】 図1
Description
このようなGaAsなどの化合物半導体を用いた高周波集積回路装置は、一般に、低電圧駆動においてすぐれた高周波特性を有するものではあるが、さらに、いわゆる第3世代携帯電話(3G)対応の同時送受信のスイッチ回路にあっては、ますます低電圧化、高性能化の要求が高まっている昨今の状況下における高周波特性向上、特に低歪化の要求が、更にきびしくなっている。
スイッチICとしては種々の提案がなされている(例えば非特許文献1参照)。
第1及び第2のFET1およびFET2のゲートは、それぞれ抵抗R1およびR2を介して、制御信号導入端子CTL1およびCTL2に接続され、第1および第2のFET1およびFET2のソース・ドレイン間電流通路の接続中点が、抵抗R3を介して直流バイアス端子Biasに接続される。
この場合、導電性ダイパッド101上にスイッチMMIC102がマウントされ、このMMIC102の所要電極が、第1および第2の高周波入力または出力がなされる高周波入出力端子I/O1およびI/O2に、例えばリードワイヤ104によって接続され、そして、このスイッチMMIC102、導電性ダイパッド101、高周波入出力端子I/O1およびI/O2を樹脂モールド105により覆われたパッケージICを構成している。またこのパッケージICは配線基板100上に配置され、導電性ダイパッド101、および入出力端子I/O1およびI/O2は、電気的に、配線基板100上に接続されている。
ダイパッド101は、金属層によって構成された導電体であり、接地(GND)されている。
IEEE GaAs IC Symposium 1995 pp132-135H Uda,"A Very High Isolation GaAs SPDT Switch IC Seald in an Ultra-compact Plastic Package"
ところが、この化合物半導体による高周波スイッチ回路において、上述した昨今要求される厳しい低歪化を安定して充分に達成することができない。
本発明は、このような不都合を回避した高周波スイッチ回路を有する高周波装置を提供するものである。
本発明は、このような不都合を回避したスイッチ回路を有する高周波装置を提供するものである。
本発明は、上述したスイッチ回路を有する高周波回路にあって、前記半導体基板に印加する前記正電位の電圧が、正の固定電位であることを特徴とする。
本発明によるスイッチ回路を有する高周波装置にあって、各前記化合物半導体基板がGaAs系基板であることを特徴とする。
これは、次のようなことによるものと考えられる。
すなわち、化合物半導体によるスイッチ回路における低歪化の阻害は、現状の化合物半導体の製造技術では、例えば低いレベルの不純物濃度の制御や、材料組成プロファイル制御が充分になされないことから、この電界効果トランジスタの製造が、生産ロットごとに微妙に変化することにより、化合物半導体基板の電位が、実際にはGND電位等のバイアス電位が与えられていない不安定状態では、チャネル直下の不要なトラップの残存や、空乏化領域の制御が困難であり、これが歪み発生の要因となっていると考えられる。
また、このトラップによる電荷の捕獲、または放出の時定数が大きい場合、高周波回路の高速な制御に支障を与えることになる。
また、空乏化領域は、不要な容量成分となり、高周波特性を劣化させる要因となる。
本発明においては、基板を絶縁部で電気的に分離し、積極的に電圧を印加したことにより、トラップの影響、空乏領域の抑制によって、歪みの低減化、高周波特性の向上を図ることができるものである。
図1は、本発明装置の一形態例の構成図で、図2はその要部の模式的断面図である。
本発明は、例えばGaAsによる化合物半導体基板1に、例えばHEMT(High Electron Mobility Transistor)、あるいは接合型電界効果トランジスタ等によるFET1を含むスイッチ回路11が形成される。この形態例においては、スイッチ回路11と、これを制御するロジック回路12が形成される。
GaAs化合物半導体1の裏面すなわち電界効果トランジスタが形成された一主面とは反対側の他の主面に、絶縁部2が配置される。この実施の形態例えは、絶縁部2は、例えばガラス・エポキシ樹脂によるFRT4(Flame Retardant Type4)から成る絶縁性のパッケージ基板20によって構成されている。
GaAs半導体基板1には、例えば図12で示したスイッチ回路と同様の回路構成によるスイッチ回路11と、これを駆動するロジック回路12とが形成された高周波装置が形成されている。
この抵抗Rは、例えば化合物半導体基板1上に形成された表面絶縁層34上に、電源接続端子33を設け、これに電源端子Vddをリードワイヤ等によって接続し、この電源接続端子33と、基板電圧印加電極30との間に、化合物半導体基板1に回路素子として形成した抵抗素子Rを介在させる構成とすることができる。
第1及び第2のFET1およびFET2のゲートは、それぞれ抵抗R1およびR2を介して、ロジック回路12から制御信号が供給される制御信号導入端子CTL1およびCTL2に接続され、第1および第2のFET1およびFET2のソース・ドレイン間電流通路の接続中点が、抵抗R3を介して直流バイアス端子に接続される。
制御信号導入端子CTL1およびCTL2にそれぞれ所要の制御信号を供給し、バイアス端子Biasに所要のバイアス電圧を供給するようになされる。
電界効果トランジスタは、図2に第1の電界効果トランジスタFET1を代表的に示すように、例えば低不純物濃度のチャネル形成領域4上に例えばp型のゲート領域5を例えばイオン注入して形成し、チャネル領域4を挟んでその両側にn型のソースないしドレイン3を同様に、例えばイオン注入によって形成する。
絶縁パッケージ基板20上には、化合物半導体基板1等を覆って、樹脂モールドパッケージ40が形成される。
すなわち、ロジック回路12から、例えば2Vのバイアス電圧が抵抗R3を介してスイッチ回路11に印加される。このスイッチ回路11をオンとするときは、例えば端子CTL1から高い電圧例えば3Vを印加すると第1のFET1のゲートバイアス(対ドレイン、ソース)は1Vとなり、FET1はオンとなる。一方、例えば端子CTL2から低い電圧例えば0Vを印加するとて第2のFET2のゲートバイアス(対ドレイン、ソース)は−2Vとなり、FET2はオフとなり、端子I/O1およびI/O2間がオン、すなわちスイッチ回路がオンとなる。
これは、電界効果トランジスタにおける空乏領域の低減化による容量の低下、例えばトラップによる不安定な電荷の捕獲、放出の改善によるものと考えられる。
この場合、第1および第2の電極31および32間に抵抗Rを介在させるとか、第1の電極31と電源接続端子33との間に上述した抵抗Rを接続することができる。
これら第1および第2の電極31および32の電気的接続は、図3で示すように、化合物半導体基板1を貫通するビアホール50を通じて電気的に接続することができる。
あるいは相互にリードワイヤによって接続することもできるものである。
図3の構成において、第2の電極32は、化合物半導体基板1の少なくとも電界効果トランジスタFET例えばFET1およびFET2の形成部下に相当する位置を含んで形成する。しかしながら、余りこの第2の電極32の面積が大きくなると寄生容量が大きくなり、高周波特性への影響が生じるおそれがあることから、第2の電極32の面積は、化合物半導体基板1の面積の50%以下であることが望ましいことが分かった
この例では、リードフレームによる金属板60を設け、そのダイパッド部61上に、例えば図2で示した化合物半導体基板1の裏面を直接的に銀ペースト等の導電材62によって電気的に結合し、樹脂モールドパッケージ40を絶縁部2とした場合である。この場合において、ダイパッド61、上述した抵抗Rを介してVddと接続する構成とすることができる。
なお、図3および図4において、図1および図2と対応する部分には同一符号を付して重複説明を省略する。
すなわち、この場合、図5、図6、図7で示すように、例えばサブストレイト1S上に、アンドープのAlGaAsによるバッファ層71、n型の第1の不純物ドーピング層72、チャネル層73、n型の第2の不純物ドーピング層74低不純物濃度層75が順次エピタキシャル成長されて成る。そして接合ゲートを構成するp型のゲート領域76が、例えばZnをイオン注入することによって形成される。
そして、このゲート領域76を挟んでその両側にn型の高濃度の例えばGaAs層によるソースないしはドレインのコンタクト層78が形成され、この上に電極79がコンタクトされてHEMTによるFETが形成される。
この基板電圧印加電極30のコンタクト部には、チャネル(チャネル形成領域)と同導電型の不純物導入領域もしくはゲートと同導電型の不純物導入領域77に基板電圧印加電極30をコンタクトする。
これら不純物導入領域77は、例えばHEMT等のFETのゲート領域76あるいはソースないしはドレインのコンタクト層78の形成と同時に形成することができる。
これは、スイッチ特性として、アイソレーションの改善が図られることになる。
いま、図10に示すように、入出力端子I/O1およびI/O2間のDP3T(Dual Pole 3 Throw)スイッチ回路に、高周波RF2,RF1の入力信号を導入した場合について、図11に周波数に対する2次および3次混変調歪みを、基板印加電圧を印加した本発明例と、しない従来例と基板を対比して示した。これによれば本発明によるときは、相互変調歪みの改善が図られることが分かる。
上述したように、本発明によれば、例えば3D対応の高周波装置において、きわめてきびしく要求される高周波特性、とくに歪み低減を行うことができることがわかる・
なお、本発明は上述した例に限られるものではない。
Claims (18)
- 化合物半導体基板と、
第1の高周波入出力端子と、第2の高周波入出力端子と、制御信号導入端子と、電源端子と、接地端子とを有し、
前記化合物半導体基板の活性領域の前記化合物半導体基板の一主面側に電界効果トランジスタが形成され、該電界効果トランジスタを含むスイッチ回路が構成され、
前記化合物半導体基板の他の主面側に絶縁部が配置され、
前記化合物半導体基板に、前記電源端子から所要の正電位の電圧を印加する基板電圧印加電極が設けられて成ることを特徴とするスイッチ回路を有する高周波装置。 - 前記半導体基板に印加する前記正電位の電圧が、正の固定電位であることを特徴とする請求項1に記載の高周波スイッチ回路を有する高周波装置。
- 前記電源端子と、前記基板電圧印加電極との間に、抵抗が接続されて前記半導体基板に所要の正電位印加がされるようにしたことを特徴とする請求項1に記載の高周波スイッチ回路を有する高周波装置。
- 前記化合物半導体基板の半導体回路素子の非形成部の非活性領域がイオン注入によって構成されたことを特徴とする請求項1に記載のスイッチ回路を有する高周波装置。
- 前記化合物半導体基板の半導体回路素子の非形成部の非活性領域が、エッチングされた領域によって形成されたことを特徴とする請求項1に記載のスイッチ回路を有する高周波装置。
- 前記基板電圧印加電極が、前記電界効果トランジスタが形成された活性領域とは、非活性領域により分離された活性領域上に形成されたことを特徴とする請求項1に記載のスイッチ回路を有する高周波装置。
- 前記正電位の電圧を印加する基板電圧印加電極が、前記化合物半導体基板の半導体回路素子の非形成部の非活性領域上に形成されたことを特徴とする請求項1に記載のスイッチ回路を有する高周波装置。
- 前記正電位の電圧を印加する基板電圧印加電極が、前記化合物半導体基板の半導体回路素子の非形成部の非活性領域上に形成された前記電界効果トランジスタのチャンネルの導電型と同導電型の不純物導入領域上にコンタクトされたことを特徴とする請求項1に記載のスイッチ回路を有する高周波回路装置。
- 前記基板電圧印加電極が、前記化合物半導体基板の半導体回路素子の非形成部の非活性領域上に形成された前記電界効果トランジスタのゲートの導電型と同導電型の不純物導入領域上にコンタクトされたことを特徴とする請求項1に記載のスイッチ回路を有する高周波回路装置。
- 前記基板電圧印加電極が、相互に電気的に接続された第1の電極と第2の電極とを有し、第1の電極が前記電源端子に接続されて成ることを特徴とする請求項1に記載のスイッチ回路を有する高周波装置。
- 前記第1の電極と前記第2の電極との間に抵抗を介在させたことを特徴とする請求項10に記載のスイッチ回路を有する高周波装置。
- 前記第2の電極が前記化合物半導体基板の前記他の主面側に配置され、該第2の電極
の面積が、前記化合物半導体の面積の50%以下に選定されて成ることを特徴とする請求項10に記載のスイッチ回路を有する高周波装置。 - 前記第1の電極と前記第2の電極とが、前記化合物半導体基板の前記一主面と他の主面とに形成され、これら第1の電極と第2の電極とが、前記半導体基板を貫通するビアホールを通じて電気的に接続されたことを特徴とする請求項10に記載のスイッチ回路を有する高周波装置。
- 前記第1の電極と前記第2の電極とが、前記化合物半導体基板の前記一主面と他の主面とに形成され、これら第1の電極と第2の電極とが、リードワイヤによって電気的に接続されたことを特徴とする請求項10に記載のスイッチ回路を有する高周波装置。
- 前記電源端子および第2の電極間に抵抗が接続されたことを特徴とする請求項10に記載のスイッチ回路を有する高周波装置。
- 前記化合物半導体基板と前記絶縁部との間に、金属板が介在されるように、該金属板に上記化合物半導体基板が取着され、
前記金属板が、前記基板電圧印加電極とされたことを特徴とする請求項1に記載のスイッチ回路を有する高周波装置。 - 請求項1に記載のスイッチ回路を有する高周波装置にあって、
CMOSロジック回路が形成されシリコン(Si)半導体基板と、
前記ロジック回路への制御信号入力端子と、前記ロジック回路からの前記スイッチ回路への制御信号出力端子とを有することを特徴とするスイッチ回路を有する高周波装置。 - 前記化合物半導体基板がGaAs系基板であることを特徴とする請求項1に記載のスイッチ回路を有する高周波装置。
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JP4810904B2 (ja) | 2011-11-09 |
US20070018204A1 (en) | 2007-01-25 |
US20150325590A1 (en) | 2015-11-12 |
US8598629B2 (en) | 2013-12-03 |
US9105564B2 (en) | 2015-08-11 |
CN1901196B (zh) | 2011-06-08 |
US20160307857A1 (en) | 2016-10-20 |
US9406696B2 (en) | 2016-08-02 |
CN1901196A (zh) | 2007-01-24 |
US9824986B2 (en) | 2017-11-21 |
US20140035065A1 (en) | 2014-02-06 |
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