CN1901196A - 具有高频开关电路的高频装置 - Google Patents

具有高频开关电路的高频装置 Download PDF

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CN1901196A
CN1901196A CNA2006101061811A CN200610106181A CN1901196A CN 1901196 A CN1901196 A CN 1901196A CN A2006101061811 A CNA2006101061811 A CN A2006101061811A CN 200610106181 A CN200610106181 A CN 200610106181A CN 1901196 A CN1901196 A CN 1901196A
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electrode
switching circuit
semiconductor substrate
frequency device
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CN1901196B (zh
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小浜一正
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Sony Corp
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Abstract

一种具有高频开关电路的高频装置，在化合物半导体的高频开关电路中，实现了具有高频开关电路的高频装置的低失真化。形成有构成开关电路(11)的场效应晶体管FET的化合物半导体基板(1)经由绝缘部(2)设置，通过对基板(11)施加需要的正电位的电压，可以实现失真的降低。

Description

具有高频开关电路的高频装置
技术区域
本发明涉及具有适用于例如蜂窝式电话的高频开关电路的高频装置。
背景技术
例如在蜂窝式电话中，利用800MHz～2.3GHz的带域的高频信号进行通信。在这样使用的频率比较高的情况下，增大送信电力的功率放大器(PA)或增大接收信号的所谓的低噪音放大器、切换信号的开关电路重视高频特性，目前多利用电子移动度高的GaAs等的化合物半导体以取代一般的IV族半导体的例如Si半导体。利用这样的GaAs等的化合物半导体的高频集成电路装置，一般地在低电压驱动中具有良好的高频特性，但是在所谓的第3代移动电话(3G)对应的同时接收发送信息的开关电路越来越要求低电压化、高性能化的目前的情况下，高频特性的提高、特别地低失真化变得更加严格。
作为例如蜂窝式电话中的天线切换等的开关电路，因为上述的理由，多利用开关MMIC(Monolithic Microwave Integrated Circrit)，该开关MMIC利用了GaAs化合物半导体的场效应晶体管FET。在该天线开关电路中，对低电压驱动、例如2.6V驱动的低损失、低失真等的特性上的要求很严格。作为开关IC提出有各种各样的方案(参照例如非专利文献1)。
图12是利用例如GaAs化合物半导体的结合栅型场效应晶体管(J-FET)的最基本的开关电路的构成图。该情况下，在共通的GaAs基板上分别具有J-FET的第一FET1以及第二FET2，这些第一FET1以及第二FET2的源极以及漏极间电流通路从属地连接，第一FET1的电流通路的两端经由电容C1以及C2与第一输出输入端子I/O1以及第二输出输入端子I/O2连接，第二FET2的电流通路的另一端经由电容C3与接地端子GND连接，由此与外部直流地被遮断。第一FET1以及第二FET2的栅极经由各电阻R1以及R2与控制信号导入端子CTL1以及CTL2连接，第一FET1以及第二FET2的源极-漏极间电流通路的连接中点经由电阻R3与直流偏致端子Bias连接。
在该开关电路11中，例如2V的偏致电压经由电阻R3从逻辑电路施加到开关电路。在将该开关电路接通时，例如从端子CTL1施加高电压例如3V时，第一FET1的栅极偏致(对漏极、源极)成为1V，FET1变为接通。例如从端子CTL2施加低电压例如0V时，第二FET2的栅极偏致(对漏极、源极)成为-2V，FET2变为截止，端子I/O1以及I/O2间变为接通、即开关电路变为接通。
相反地，例如端子CTL1为例如低电压0V时，第一FET1的栅极偏致(对漏极、源极)成为-2V，FET1变为截止。例如在向端子CTL2上施加高电压例如3V时，第二FET2的栅极偏致(对漏极、源极)成为1V，FET2变为接通，其结果，端子I/O1以及I/O2间开放，通过高频地短路信号路径来进一步地确保隔离。
图13是具有上述开关电路的一般的开关MMIC的高频装置的安装状态的概略剖面图。该情况下，导电性管芯垫101上安装有开关MMIC102，该开关MMIC102的所要电极通过例如引线104与进行高频输入或输出的第一高频输入输出端子I/O1以及第二高频输入输出端子I/O2连接，构成通过树脂模105覆盖该开关MMIC102、导电性管芯垫101、高频输入输出端子I/O1以及I/O2的封装IC。另外，该封装IC设置在配线基板100上，导电性管芯垫101、以及输入输出端子I/O1以及I/O2电连接在配线基板100上。管芯垫101是金属层构成的导电体，并且接地(GND)。
图14是构成开关MMIC102的例如GaAs的结合栅型场效应晶体管J-FET的主要部分的概略剖面图。在该情况GaAs体构成的GaAs基板上形成有构成沟道形成区域107的低杂质浓度的半导体层，夹着该半导体层的沟道形成区域形成例如N型的高杂质浓度的源极区域108D以及漏极区域10S。D、S以及G分别是在漏极、源极以及栅极区域上的覆盖有电阻而形成的漏极、源极、以及栅极电极。
这样，沟道形成区域107的正下方，即与栅极区域109相反的一侧上，通过半绝缘性的GaAs基板106的存在而尽力防止信号的泄漏。
非专利文献1：IEEE GaAs IC Symposium 1995 pp132-135H Uda，”A VeryHigh Isolation GaAs SPDT Switch IC Seald in an Ultra-compact PlasticPackage”
发明内容
如上所述，以移动电话为代表的消费者(コンシュ一マ)用途等中，大量地使用有GaAs系化合物半导体的高频MMIC，期待生产性好，具有优良的高频性能的GaAs高频IC。但是，在该化合物半导体的高频开关电路中，不能充分稳定地达到上述目前要求的严格的失真化。本发明提供一种具有避免这样的不良情况的高频开关电路的高频装置。本发明提供一种具有避免这样的不良情况的开关电路的高频装置。
本发明的具有开关电路的高频装置包括：化合物半导体基板、第一高频输入输出端子、第二高频输入输出端子、控制信号导入端子、电源端子以及接地端子，其特征在于：在上述化合物半导体基板的有源区域的上述化合物半导体基板的一主面侧上形成有场效应晶体管，构成有含有该场效应晶体管的开关电路，在上述化合物半导体基板的另一主面侧上设置有绝缘部，在上述化合物半导体基板上，设置有从上述电源端子施加需要的正电位的电压的基板电压施加电极。本发明是具有上述开关电路的高频路电路，其特征在于：施加在上述半导体基板上的上述正电位的电压为正的固定电位。
通过上述本发明装置，在构成开关电路的化合物半导体基板的背面设置绝缘部，在与其它部件电分离的状态下，由于施加了正电位的电压，所以可以稳定地进行场效应晶体管的下部的耗尽区域的抑制和控制。
本发明是具有上述开关电路的高频电路，其特征在于：在上述电源端子和上述基板电压施加电极之间，与电阻连接且对上述半导体基板施加需要的正电位。
另外，本发明是具有上述开关电路的高频电路，其特征在于：在上述化合物半导体基板和上述绝缘部之间设置有金属板，该金属板上安装有上述化合物半导体基板，上述金属板作为上述基板电压施加电极。
另外，本发明的具有开关电路的高频装置，其特征在于：形成CMOS逻辑电路，具有的硅(Si)半导体基板、向上述逻辑电路输入控制信号的控制信号输入端子、从上述逻辑电路向上述开关电路输出控制信号的控制信号输出端子。本发明的具有开关电路的高频装置，其特征在于：各上述化合物半导体基板为GaAs系基板。
在上述的本发明构成中，在化合物半导体基板的背面设置绝缘部，通过对基板施加正的电位的电压，与现有技术中不施加正的电压的不稳定的开关电路相比，可以补偿制造工序中的控制性的不匀，极大地降低失真。这是由于下面的原因。即，化合物半导体的开关电路中的失真化的阻害，在现有的化合物半导体的制造技术中，由于例如低水平的杂质浓度的控制或材料组成轮廓控制不充分，所以该场效应晶体管的制造在各生产批次上产生微小的变化，所以化合物半导体基板的电位，在没有供给实际上的GND电位等的偏致电位的不稳定的状态下，很难进行对沟道下的不需要的陷阱的残存或耗尽化区域进行控制，这些成为失真产生的原因。另外，该陷阱的电荷的捕获或放出的时间常数大的情况下，会妨碍高频电路的高速的控制。另外，耗尽化区域成为不需要的容量部分，成为使高频特性恶化的原因。本发明中，通过将基板通过绝缘部电分离，积极地施加电压，通过陷阱的影响、耗尽区域的抑制，可以实现失真的降低化、高频特性的提高。
附图说明
图1是本发明装置的一例的构成图；
图2是本发明装置的一例的主要部分的模式的剖面图；
图3是本发明装置的其它的例子的主要部分的模式的剖面图；
图4是本发明装置的又一其它例子的主要部分的模式的剖面图；
图5是本发明装置的其它例子的主要部分的模式的剖面图；
图6是本发明装置的其它例子的主要部分的模式的剖面图；
图7是本发明装置的其它例子的主要部分的模式的剖面图；
图8是本发明装置的又一其它例子的主要部分的模式的平面图；
图9是表示本发明的场效应晶体管的截止容量的基板施加电压的依存性的图；
图10是本发明装置以及现有技术装置的失真测定的说明图；
图11是本发明装置以及现有技术装置的失真测定结果的表图；
图12是高频开关电路的电路图；
图13是现有技术的开关MMIC的概略剖面图；
图14是构成现有技术的开关电路的场效应晶体管部的概略剖面图。
标号说明
1：化合物半导体基板
1S：基片
2：绝缘部
3：源极至漏极区域
4：沟道区域
5：栅极区域
11：开关电路
12：逻辑电路
20：封装基板
30：基板电压施加电极
31：第一电极
32：第二电极
33：连接电极端子
34：绝缘层
40：树脂模制封装
50：通孔
60：金属板(导线框)
61：管芯垫
71：缓冲层
72：第一杂质掺杂层
73：沟道层
74：第二杂质掺杂层
75：低杂质浓度层
76：栅极区域
77：杂质导入区域
78：接触层
79：电极
100：配线基板
101：导电性管芯垫
102：开关MMIC
103：端于
104：引线
105：树脂封装
106：GaAs化合物半导体基板
108：源极区域
108D：漏极区域
109：栅极区域
具体实施方式
图示了具有实施本发明的开关电路的高频装置的实施方式，但本发明并不局限于该实施方式。图1是本发明装置的一实施例的构成图，图2是其主要部分的模式的剖面图。本发明在例如GaAs的化合物半导体基板1上形成例如HEMT(High Electron Mobility Transistor)或含有接合型场效应晶体管等的FET1的开关电路11。在该实施例中，形成开关电路11和对其控制的逻辑电路12。
在与GaAs化合物半导体1的背面即形成场效应晶体管的一主面相反侧的另一主面上，设置有绝缘部2。该实施方式中，绝缘部2由例如玻璃·环氧树脂的FRT4(Flame Retardant Type4)组成的绝缘性封装基板20构成。
在封装基板20上，形成有例如开关电路11的第一输入输出端子I/O1以及第二输入输出端子I/O2、接地端子GND，设置有相对于逻辑电路12的控制信号导入端子CTL1以及CTL2和电源端子Vdd。在GaAs半导体基板1上，形成有高频装置，该高频装置由例如图12所示的开关电路和同样的电路构成的开关电路11以及对其驱动的逻辑电路12形成。
本发明中，在化合物基板1上，与进行需要的正电位的电压施加的基板施加电极30接触，从电源端子Vdd施加需要的正的电位的电压。该情况下，优选通过介由电源端子Vdd和基板电压施加电极30之间的电阻R遮断交流成分对基板施加电极30施加电压。该电阻R可以是如下的结构：在形成有化合物半导体基板1上的表面绝缘层34上，设置电源连接端子33，通过引线等将电源端子Vdd与其连接，在该电源连接端子33和基板电压施加电极30之间设置作为电路元件的形成在化合物半导体基板1上的电阻元件R。
开关电路11与上述相同地，在共同的化合物基板1例如GaAs基板上分别具有例如HEMT或J-FET等的第一FET1以及第二FET2。这些第一FET1以及第二FET2在这些源极以及漏极间与电流通路连接，第一FET1的电流通路的两端经由电容C1以及C2与第一输入输出端子I/O1以及第二输入输出端子I/O2连接，第二FET2的电流通路的另一端经由电容C3与接地端子GND连接，由此与外部进行直流地遮断。第一FET1以及第二FET2的栅极分别经由电阻R1以及R2，与被供给来自逻辑电路12的控制信号的控制信号导入端子CTL1以及CTL2连接，第一FET1以及第二FET2的源极·漏极间电流通路的连接中点经由电阻R3与直流偏致端子连接。
逻辑电路12从被施加电源电压的电源端子Vdd提供电压，从控制信号端子CTLa以及CTLb被施加控制信号，对开关电路11的控制信号端子CTLa以及CTLb分别供给需要的控制信号，对偏致端子Bias供给需要的偏致电压。
上述的开关电路11以及逻辑电路12的各个电路元件形成在化合物半导体基板1的有源区域1a的化合物半导体基板的一主面侧。该有源区域1a通过需要的离子注入区域而形成。场效应晶体管如图2中的第一场效应晶体管FET1为代表所示，在例如低杂质浓度的沟道形成区域4上例如注入离子形成例如p型栅极区域5，隔着沟道区域4在其两侧同样地例如注入离子形成n型的源极至漏极3。在绝缘封装基板20上覆盖有化合物半导体基板1等，形成树脂膜制封装40。
该构成的开关电路11通过来自逻辑电路12的信号控制，进行与图12说明的动作相同的动作。即例如2V的偏致电压经由电阻R3从逻辑电路12施加在开关电路11上。接通该开关电路11时，若从例如端子CTL1施加高电压例如3V，则第一FET1的栅极偏致(对漏极、源极)变为1V，FET1接通。若从例如端子CTL2施加低电压例如0V时，则第二FET2的栅极偏致(对漏极、源极)变为-2V，FET2截止，端子I/O1以及I/O2间接通，即，开关电路接通。
相反地，例如若使端子CTL1为低压的例如0V，则第一FET1的栅极偏致(对漏极、源极)变为-2V，FET1截止。例如在端子CTL2上施加高电压例如3V时，第二FET2的栅极偏致(对漏极、源极)变为1V，FET2接通，其结果，端子I/O1以及I/O2间开放，信号路径被高频地短路，由此，进一步确保了绝缘。
在本发明中，如上所述，在化合物半导体基板1上设置有基板电压施加电极30，对该化合物半导体基板1施加例如固定的正电位的偏致电压，由此构成具有改善失真的开关电路的高频装置。这被认为是由于场效应晶体管中的耗尽区域的降低化而导致的电容降低，并且由例如陷阱而导致的的不稳定的电荷捕获、释放的改善。
在图2所示的实施例中，将基板电压施加电极30设置在形成有化合物半导体基板1的FET等电路元件的主面侧的情况下，如例如图3表示的本发明的具有开关电路高频装置的主要部分的模式的剖面图，通过相互电连接的第一电极31以及第二电极32构成基板电压施加电极30。该情况下，可以在第一电极31以及第二电极32之间设置电阻R，使第一电极31和电源连接端子33之间连接上述电阻R。
第一电极31如图3所示，设置在形成有化合物半导体基板1的FET等电路元件的一主面侧上，在与其相反的另一主面侧上设置有第二电极32，通过第二电极32，可以对化合物半导体基板1施加正的电位电压。这些第一电极31以及第二电极32的电连接，如图3所示，可以通过贯通化合物半导体基板1的通孔50电连接。或可以通过引线相互连接。
在图3的构成中，第二电极32形成为含有相当于化合物半导体基板1的至少场效应晶体管FET例如FET1以及FET2的形成部下的位置。但是，该第二电极32的面积过度地增大时寄生电容将变大，有可能对高频特性产生影响，所以第二电极32的面积希望在化合物半导体基板1的面积的50％以下。
另外，图4是本发明装置的另一实施例的模式的剖面图，在该实施例中，在介于化合物半导体基板和绝缘部2之间设有金属板。在该例中，设置有引框形成的金属板60，在该管芯垫部61上，将例如图2所示的化合物半导体基板1的背面通过银糊剂等的导电材料62直接地进行电结合，将树脂膜制封装40作为绝缘部2。该情况下，可以经由上述电阻R将管芯垫61与Vdd连接。另外，在图3以及图4中，对图1以及图2对应的部分付与相同的标号并省略其说明。
图5、图6、图7是例示场效应晶体管(FET)和基板电压施加电压30的配置关系的模式的剖面图。在它们中，例示了FET为接合栅型的pHEMT的情况。即，该情况下，在例如半绝缘(SI)GaAs基片1S上构成化合物半导体基板1，该化合物半导体基板1是通过构成pHEMT的半导体层外延成长而得到的。即，该情况下，如图5、图6、图7所示，例如在基片1S上，不掺杂AlGaAs的缓冲层71、N型第一杂质掺杂层72、沟道层73、n型第二杂质掺杂层74低杂质浓度层75顺次外延成长构成。构成接合栅极的p型栅极区域76通过例如将Zn离子注入而形成。隔着该栅极区域76在其两侧形成n型高浓度的例如GaAs层的源极至漏极的接触层78，其上形成有与电极79接触并由HEMT形成的FET。
在形成该FET等的电路元件的有源区域1a以外，在包围有源区域1a或分离多个的有源区域间而在它们之间的位置上形成有例如进行硼B的离子注入而高电阻化的无源区域1b。
如图5或图7所示，在该无源区域1b上，或者如图6的模式的剖面图所示，在通过例如无源区域1b与形成有FET的有源区域1a分离的其它有源区域1a上，可以接触基板电压施加电极30。在该基板电压施加电极30的接触部上，使基板电压施加电极30与和沟道(沟道形成区域)同导电型的杂质导入区域或和栅极同导电型的杂质导入区域77接触。
该构成时，确保失真特性和绝缘性更加稳定和良好。这是由于正的电位的电压良好地施加在FET的背面侧上。这些杂质导入区域77可以在例如HEMT等的FET的栅极区域76或源极至漏极的接触层78形成的同时形成。
在上述例子中，通过离子注入形成无源区域1b，但例如根据通过FET结构的不同，也可以通过离子注入在高电阻半导体层上形成有源区域1a。
在上述各例子中，将开关电路11和逻辑电路12形成为共通的化合物半导体1，但例如图8模式的平面图所示，也可以如下地形成高频装置：例如在GaAs化合物半导体基板1上只形成开关电路11，设置与化合物半导体基板1不同的例如IV族元素半导体的Si基板71，在其上形成逻辑电路，通过引线等以需要的关系将它们连接。在图8中，对与图1对应的部分付与相同的标号且省略重复说明。
图9，在图1的构成中，对场效应晶体管FET1截止时的截止电容的化合物半导体基板1的基板施加电压即基板的偏致施加电压依存性的测定结果构思的图。该情况下，通过3V的电压施加可以降低10％的截止电容。这作为开关特性实现了绝缘的改善。
另外，图3所示的构成是DPDT(Dual Pole Dual Throw)开关的高频装置，该情况下，很大地实现了相互调制失真IMD2、IMD3的改善。现在，如图10所示，在输入输出端子I/O1以及I/O2间的DP3T(Dual Pole 3 Throw)开关电路上导入高频RF2、RF1的输入信号的情况下，对比施加基板施加电压的本发明例和不施加的现有技术例的基板，而表示了相对于图11的频率的2阶以及3阶混合调制失真。由此通过本发明，实现了相互调制失真的改善。如上所述，通过本发明，在例如3D对应的高频装置中，可以满足非常严格地要求的高频特性，特别地可以降低失真。另外，本发明不仅局限于上述例子。

Claims (18)

1.一种具有开关电路的高频装置，其具有：化合物半导体基板、第一高频输入输出端子、第二高频输入输出端子、控制信号导入端子、电源端子以及接地端子，其特征在于：在上述化合物半导体基板的有源区域的上述化合物半导体基板的一主面侧上形成有场效应晶体管，构成有含有该场效应晶体管的开关电路，在上述化合物半导体基板的另一主面侧上设置有绝缘部，并且设置有从上述电源端子向上述化合物半导体基板施加需要的正电位的电压的基板电压施加电极。
2.如权利要求1所述的具有开关电路的高频装置，其特征在于：向上述半导体基板施加的上述正电位的电压为正的固定电位。
3.如权利要求1所述的具有开关电路的高频装置，其特征在于：在上述电源端子和上述基板电压施加电极之间连接有电阻，向上述半导体基板上施加需要的正电位。
4.如权利要求1所述的具有开关电路的高频装置，其特征在于：上述化合物半导体基板的半导体电路元件的非形成部的无源区域通过离子注入而构成。
5.如权利要求1所述的具有开关电路的高频装置，其特征在于：上述化合物半导体基板的半导体电路元件的非形成部的非活性区域通过蚀刻的区域而形成。
6.如权利要求1所述的具有开关电路的高频装置，其特征在于：上述基板电压施加电极形成在通过无源区域与形成有上述场效应晶体管的有源区域分离的有源区域上。
7.如权利要求1所述的具有开关电路的高频装置，其特征在于：施加上述正电位的电压的基板电压施加电极形成在上述化合物半导体基板的半导体电路元件的非形成部的无源区域上。
8.如权利要求1所述的具有开关电路的高频装置，其特征在于：施加上述正电位的电压的基板电压施加电极与和上述场效应晶体管的沟道的导电型相同导电型的杂质导入区域接触，上述场效应晶体管形成在上述化合物半导体基板的半导体电路元件的非形成部的无源区域上。
9.如权利要求1所述的具有开关电路的高频装置，其特征在于：上述基板电压施加电极与和上述场效应晶体管的栅极的导电型相同导电型的杂质导入区域接触，上述场效应晶体管形成在上述化合物半导体基板的半导体电路元件的非形成部的无源区域上。
10.如权利要求1所述的具有开关电路的高频装置，其特征在于：上述基板电压施加电极具有彼此电连接的第一电极和第二电极，第一电极与上述电源端子连接而构成。
11.如权利要求10所述的具有开关电路的高频装置，其特征在于：上述第一电极和上述第二电极之间设置有电阻。
12.如权利要求10所述的具有开关电路的高频装置，其特征在于：上述第二电极设置在上述化合物半导体基板的上述另一主面侧，该第二电极的面积选定为上述化合物半导体的面积的50％以下而构成。
13.如权利要求10所述的具有开关电路的高频装置，其特征在于：上述第一电极和第二电极形成在上述化合物半导体基板的上述一主面和另一主面上，这些第一电极和第二电极通过贯通上述半导体基板的通孔电连接。
14.如权利要求10所述的具有开关电路的高频装置，其特征在于：上述第一电极和第二电极形成在上述化合物半导体基板的上述一主面和另一主面上，这些第一电极和第二电极通过引线电连接。
15.如权利要求10所述的具有开关电路的高频装置，其特征在于：上述电源端子以及第二电极间连接有电阻。
16.如权利要求1所述的具有开关电路的高频装置，其特征在于：在上述化合物半导体基板和上述绝缘部之间夹着金属板而将上述化合物半导体基板安装在该金属板上，上述金属板作为上述基板电压施加电极。
17.如权利要求1所述的具有开关电路的高频装置，其特征在于：形成有CMOS逻辑电路，具有：硅(Si)半导体基板；向上述逻辑电路输入控制信号的控制信号输入端子；从上述逻辑电路向上述开关电路输出控制信号的控制信号输入端子。
18.如权利要求1所述的具有开关电路的高频装置，其特征在于：上述化合物半导体基板为GaAs系基板。
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