CN1291492C - 半导体开关电路装置及其制造方法 - Google Patents

半导体开关电路装置及其制造方法 Download PDF

Info

Publication number
CN1291492C
CN1291492C CNB031104886A CN03110488A CN1291492C CN 1291492 C CN1291492 C CN 1291492C CN B031104886 A CNB031104886 A CN B031104886A CN 03110488 A CN03110488 A CN 03110488A CN 1291492 C CN1291492 C CN 1291492C
Authority
CN
China
Prior art keywords
fet
circuit device
metal level
switched circuit
pillar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB031104886A
Other languages
English (en)
Other versions
CN1455458A (zh
Inventor
浅野哲郎
榊原干人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1455458A publication Critical patent/CN1455458A/zh
Application granted granted Critical
Publication of CN1291492C publication Critical patent/CN1291492C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48666—Titanium (Ti) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48669—Platinum (Pt) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01031—Gallium [Ga]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

一种半导体开关电路装置及其制造方法。在以往的化合物半导体开关电路装置中，高频信号会通过模制树脂而泄漏，从而引起隔离恶化。本发明的半导体开关电路装置在FET的周围设置支柱，在FET上设置由支柱支承的屏蔽金属。由于FET和屏蔽金属的间隔距离小，故当进行通常的树脂模制时，树脂不会进入该空间，FET之上形成中空。也就是说，FET和树脂由屏蔽金属屏蔽，FET的IN-OUT之间由介电常数高的空气屏蔽，所以可防止高频信号的泄漏。

Description

半导体开关电路装置及其制造方法
技术领域
本发明涉及一种用于高频率开关用途中的半导体开关电路装置及其制造方法，特别是涉及提高高频绝缘的半导体开关电路装置及其制造方法。
背景技术
在手提电话等移动通信设备中，常使用GHz频带微波，在天线的切换电路或发送接收信号的切换电路等中，常使用用于切换这些高频信号的开关元件(例如，(日本)特开平9-181642号)。作为这个元件，由于要处理高频，常使用使用了砷化镓(GaAS)的场效应晶体管(以下称FET)，随之，把前述开关电路自身集成的单片微波集成电路(MMIC)的开发正在进行。此处，作为半导体开关电路装置，以化合物半导体开关电路装置为例进行说明。
图10(A)是显示GaAs MESFET的剖面图。在非掺杂GaAs衬底1的表面部分掺杂N型杂质形成N型沟道区域2，配置与沟道区域2表面肖特基接触的栅电极3，在栅电极3的两侧，配置与GaAs表面欧姆接触的源·漏电极4、5。该晶体管利用栅电极3电位在正下方的沟道区域2内形成耗尽层，从而控制源电极4和漏电极5之间的沟道电流。
图10(B)是显示使用GaAs FET的被称作SPDT(Single PoleDouble Throw)的化合物半导体开关电路装置的原理性电路图。
第一和第二FET1、FET2的源极(或漏极)连接在共用输入端子IN上，各FET1、FET2的栅极通过电阻R1、R2连接在第一和第二控制端子Ctl-1、Ctl-2上。然后，各FET的漏极(或源极)连接在第一和第二输出端子OUT1、OUT2上。施加在第一和第二控制端子Ctl-1、Ctl-2上的信号是互补信号，使得施加了H电平信号的FET导通，使施加在输入端子IN上的信号传递到某一输出端子上。配置电阻R1、R2，其目的在于防止高频信号相对于作为交流接地的控制端子Ctl-1、Ctl-2的直流电位经栅电极而泄漏。
图11表示将图9所示的化合物半导体开关电路装置集成后的化合物半导体芯片之1例。
在GaAs衬底上，在中央部配置进行开关的FET1及FET2，电阻R1、R2连接在各FET栅电极上。在衬底的周边设置有各自对应于共用输入端子、输出端子、控制端子的电极焊盘INPad、OUT2Pad、OUT2Pad、Ctl-1Pad、Ctl-2Pad。另外，虚线所示的第二层布线是各FET栅电极形成时，同时形成的栅极金属层(Ti/Pt/Au)20。实线所示的第三层布线是进行各元件的连接及焊盘形成的焊盘金属层(Ti/Pt/Au)30。在第一层衬底上欧姆接触的欧姆金属层(AuGe/Ni/Au)10是形成各FET的源电极、漏电极及各电阻两端的取出电极的层。图10中，由于与焊盘金属层重叠，故没有显示。
图11(A)是表示把图10所示的FET1的局部放大的平面图。此图中，点划线包围的长方形区域是形成于衬底11的沟道区域12。自左侧延伸的梳齿状第三层焊盘金属层30是与输出端子OUT1连接的源极13(或漏极)，此下有第一层欧姆金属层10形成的源极14(或漏极)。另外，自右侧延伸的梳齿状的第三层焊盘金属层30是连接于共用输入端子IN的漏极15(或源极)，此下有第一层欧姆金属层10形成的漏极16(或源极)。该两电极配置成梳齿相互咬合的形状，其间，由第二层栅极金属层20形成的栅电极17梳齿状配置在沟道区域12上。
图11(B)是显示该FET的局部的剖面图。在衬底11上设有n型沟道区域12和在其两侧形成源区18及漏区19的n+型高浓度区域，在沟道区域12上设有栅电极17，在高浓度区域上设有由第一层欧姆金属层10形成的漏极14及源极16。并且，如前所述，在其上设有由第三层焊盘金属层30形成的漏极13及源极15，并进行各元件的布线等。
另外，图12中显示封装上述半导体芯片的剖面结构。图12(A)是封装剖面图，图12(B)是将封装后的FET的局部放大并概略显示的剖面图。FET部的详细结构和图11(B)相同。芯片整个面上除作为各端子的电极焊盘之上外，都设有氮化膜50作为抗蚀剂。形成有开关元件的化合物半导体芯片63利用导电糊65等固定安装在引线62的岛上，化合物半导体芯片63的各电极焊盘和引线62用键合线64连接。半导体芯片63的周边部分用与模制模型的形状一致的树脂层80覆盖，导线62的前端部分导出到树脂层80的外部。
目前，为了构筑可以传输更高密度信息的无线网络，强烈要求从现有的2.4GHz频带到5GHz频带的面向更高频带的制品。但是，我们知道当想要在高频下使用上述现有结构的化合物半导体开关电路装置时，绝缘比设计值更差。如图10、图11(B)所示，FET中作为信号输入及输出的源电极13和漏电极15夹着栅极电极17配置成梳齿形状。考虑例如在FET1接通时，FET2断开，输入FET2的高频信号在FET2的源-漏电极间即IN-OUT之间被截断，不能通过。但是，实际上，该源-漏电极间即信号的IN-OUT间是以微细图形形成的。也就是说，可以认为在断开侧FET(FET2)的IN-OUT之间，通过模制树脂层80高频信号泄漏，所以绝缘比设计值更差。
该高频信号的泄漏，在2.4GHz频带无线LAN、Bluetooth用途等2.4GHz程度的高频下不会太成问题。但是，在今后期待的5Hz以上的高频带下，绝缘的恶化会成为大问题。
发明内容
本发明是鉴于上述各种问题而开发的，其提供一种半导体开关电路装置，包括：至少一个FET，在半导体衬底表面上设置有源电极、栅电极及漏电极；电极焊盘，与下述端子分别对应，所述端子是，至少一个连接在上述FET的源电极或漏电极上的输入端子，至少一个连接在上述FET的漏电极或源电极上的输出端子，及将DC电位施加在上述FET上的端子；其特征在于，还包括：支柱，其设在上述FET的周围；金属层，支撑在上述支柱上并至少覆盖在上述FET之上；树脂层，覆盖集成了上述FET的芯片。另外，一种半导体开关电路装置的制作方法，其在半导体衬底上形成具有沟道区域、源区及漏区的FET，并形成和前述FET连接的输入端子、输出端子及施加DC电位的端子各自对应的电极焊盘。所述方法包括下述工序，在上述FET周围形成支柱，形成由上述支柱支承并至少将上述FET之上覆盖的金属层；由树脂层覆盖集成了上述FET的芯片。
附图说明
图1是用于说明本发明的平面图；
图2是用于说明本发明的剖面图；
图3是用于说明本发明的平面图；
图4是用于说明本发明的剖面图；
图5是用于说明本发明的平面图；
图6是用于说明本发明的制造方法的剖面图；
图7是用于说明本发明的制造方法的剖面图；
图8是用于说明本发明的制造方法的剖面图；
图9(A)是用于说明现有技术的剖面图、图9(B)是其电路图；
图10是用于说明现有技术的平面图；
图11(A)是用于说明现有技术的平面图、图11(B)是其剖面图；
图12A是说明现有技术的平面图，图12B是其剖面图；
图13是用于说明现有技术的剖面图。
具体实施方式
以下参照图1至图9，以化合物半导体开关电路装置为例说明本发明半导体开关电路装置的实施例。
图1中显示本发明的第一实施例即化合物半导体芯片的1例。其结构是在图11所示的布图的芯片上配置屏蔽金属。此外，电路图与图10(B)相同，FET的放大图和剖面图分别与图12(A)、图12(B)相同，所以省略说明。
在GaAs衬底的中央部配置进行开关的FET1及FET2，电阻R1、R2连接在各FET的栅极电极上。在衬底的周边设置有对应于共用输入端子、输出端子、控制端子的各电极焊盘INPad、OUT1Pad、OUT2Pad、Ctl-1Pad、Ctl-2Pad。另外，虚线所示的第二层布线是各FET栅极电极形成时，同时形成的栅极金属层(Ti/Pt/Au)20，实线所示的第三层布线是进行各元件的连接及焊盘形成的焊盘金属层(Ti/Pt/Au)30。在第一层衬底上欧姆接触的欧姆金属层(AuGe/Ni/Au)10是形成各FET的源电极、漏电极及各电阻两端的取出电极的层。在图10中，由于与焊盘金属层重叠，故没有显示。
在FET的周围，部分作为钝化膜设置在整个面上的氮化膜，露出GaAs，设置多个支柱(post)71。然后，设置由支柱71支撑的屏蔽金属70。屏蔽金属70设置成实质覆盖FET上整个面，在FET上设置多个孔。此孔具体地说是宽度为2μm～5μm左右，长度为15μm左右的狭缝90，均等地在屏蔽金属70上配置。
此狭缝90在用于实现由屏蔽金属70形成的中空结构的抗蚀剂消除工序中，作为抗蚀剂消除液的通路。也就是说，为了消除屏蔽金属下的残留抗蚀剂，只要是抗蚀剂消除液可以通过并且树脂膜不能进入的大小就可以，不限于上述大小，狭缝数也不限于图中所示的数量。另外，孔的形状也可以不是狭缝。
除去各电极焊盘部的钝化膜，压装键合线。
在此，屏蔽金属70下的芯片平面图和图10所示相同。另外，电路图和图9(B)相同，FET的放大图及其剖面图和图11(A)、(B)相同，故省略说明。
图2中是显示树脂模制图1的芯片的剖面图。图2(A)是封装剖面图、图2(B)是将FET部放大后的剖面图。
如图2(A)所示，形成有具有FET72的开关元件的化合物半导体芯片63利用导电糊65等固定安装在引线62的岛上，化合物半导体芯片63的各电极焊盘和引线62由键合线64连接。与模制模具形状一致的树脂层80覆盖在半导体芯片63的周边部分，引线62的前端部分导出到树脂层80的外部。
屏蔽金属70由多个设于FET72周围的支柱71支承，并整个设置在FET72上。支柱71和屏蔽金属70形成一体，屏蔽金属70由2μm～7μm程度的镀金层构成，FET72和屏蔽金属70以1～2μm左右的距离分开。
由已知的方法对芯片63及引线62进行树脂模制，由于FET72和屏蔽金属70的间隔距离小，故树脂不会进入该部分。另外，屏蔽金属70上为了防止抗蚀剂残留，设置了狭缝90，如本实施例所述若宽度为2um～5um，则树脂也不会自该处进入。也就是说，如图所示，由于FET72和屏蔽金属70之间形成中空部60，故可以实现高频信号通过的FET表面成为中空的封装结构。
图2(B)是概略性显示上述芯片的剖面图。另外，FET的详细结构和图10(B)相同。作为输入侧的源电极13(或漏电极15)和作为输出侧的漏电极15(或源电极13)之间配置有栅电极17，实际上是由它们多组集成而形成一个FET72。在本发明的结构中，在这些FET72上配置有由支柱71支承的屏蔽金属70，因为屏蔽金属70的外侧由树脂层80覆盖，所以FET72表面形成中空部60。
本发明的特征在于由支柱71支承的屏蔽金属70，特别在于FET72表面和屏蔽金属70的间隔距离设置为树脂层不会进入的程度。具体地，该间隔距离是1～2um左右，其厚度为即使通过传递模制等由树脂层80覆盖周围，FET72上也不会进入树脂。另外，因为狭缝90为2um～5um，故树脂不会由此进入，在FET72和屏蔽金属70之间形成中空部60。即，如图所示，源电极13、漏电极15及栅电极17和树脂层80由屏蔽金属70实质上屏蔽，并且，FET上成为中空，结果由介电常数低的空气将OFF侧FET的源-漏电极间即IN-OUT间屏蔽。因而，几乎可屏蔽输入OFF测FET的高频信号中通过模制树脂层80向输出侧泄漏的信号。
在此，支柱71在FET72的周围设置多个以能充分支承屏蔽金属70。支柱71设置成露出GaAs衬底，故只要是未配置开关电路元件的其他构成部件，就不限于图1的位置，可设置在任何部位。
另外，作为封装结构，以冲切框架的引线和传递模制为例进行了说明，但在绝缘基板上形成导电图形并一起进行模制的芯片尺寸封装结构也可同样实施。
如上所述，本发明的特征在于利用由支柱71支承的屏蔽金属70，在FET72之上设置中空部60，防止在开关元件的IN-OUT间泄漏高频信号。即，在上述实施例中，虽然以由一个共同输入端子和两个FET、两个OUT端子构成的SPDT开关为例进行了说明，但在带分流器的SPDT、串联连接多个FET的大功率用SPDT，两个输入端子两个输出端子的DPDT等开关电路装置、具有GND端子或电源端子的开关电路装置中也同样可以实施。另外，使用大功率用途的多栅结构FET的开关电路装置及非对称SPDT、SPST、SP3T、SP4T等的所有开关电路装置中均可实现。
这里，使用图3俩说明支柱71的形成位置。支柱71被多个设置在FET72的周围，以便可充分支撑屏蔽金属70。在本实施方式中，支柱71使GaAs衬底露出来设置，所以只要是没有配置开关电路元件等其他部件的部位就可以，而不限于图1的位置。
但是，在支柱71被原封不动地连接在不掺杂的GaAs衬底上的情况下，需要将支柱71和构成支柱71相邻的开关电路装置的元件101(例如FET的漏区等)的距离确保20μ以上。这是因为支柱71和元件101的电位差产生的耗尽层相互到达对方侧，存在两者间的电干扰对开关电路动作产生影响的危险。
因此，在固定支柱71的区域的GaAs表面上，为了从支柱71突出1μm以上，可设置分离区域100。这种情况下，该分离区域是高浓度区域100。由此，可抑制与支柱71相邻的元件101间的电位差产生的衬底中的耗尽层的扩大，所以与支柱71相邻的元件101的分离距离d可接近至4μm(图3(A))。
此外，在本实施方式中，举例说明了化合物半导体开关电路装置，但不限于此，即使在图3(B)、图3(C)所示的硅半导体开关电路装置中也可实施。
在硅半导体开关电路装置中，衬底211例如为p+型的高浓度硅衬底，在其上，设置沟道区域212组成的p-外延层。在沟道区域212表面上设置栅极氧化膜213，在其表面上设置栅极217。在栅极217两侧的沟道区域212中，有设置了所谓低浓度的杂质扩散区域LE的LDD(Light Doped Drain)结构。由此，可以抑制沟道电阻的下降和短沟道效应。而且，在其两侧设置形成了源区218和漏区219的n+型的高浓度区域。在源区218和漏区219中，通过A1等来设置源极216和漏极214，进行各元件的布线等。
在FET101的周围，作为钝化膜，除去在整个表面设置的氮化膜215，使衬底211表面露出，并设置分离区域100。在分离区域100上设置支柱71、支撑于支柱71上的屏蔽金属70。
这种情况下，衬底211是p+型硅衬底，通常为GND电位。这种情况下，作为分离区域100，将扩散了与衬底211相同程度的杂质的高浓度区域100a配置在支柱71的正下方，相邻的元件101例如与漏区219分离就可以(图3(B)。
但是，该构造对于施加在屏蔽金属70上的电位为GND电位没有问题，而如果是其他的DC电位，则成为与GND短路的状态，是有问题的。因此，在这样的情况下，作为分离区域100，也可以设置LOCOS氧化膜100b。如果在LOCOS氧化膜100b上配置支柱71，则与支柱71相邻的元件扩散区域和衬底211不产生电干扰，即使在屏蔽金属70上施加任何的DC电位也没有问题。
其次，图3及图4表示本发明的第二实施例。如图3所示，也可以使覆盖在FET上的屏蔽金属70延伸设置，与控制端子用电极焊盘Ctl-1Pad接触。
在此，屏蔽金属70下的芯片平面图，和图9所示的相同。另外，电路图和图8(B)相同，FET的放大图及剖面图分别和图10(A)、(B)相同，所以省略其说明。
图4表示树脂模制该芯片后的剖面图。
如图4(A)所示，形成有开关元件的化合物半导体芯片63通过导电糊65等固定安装在引线62的岛上，用键合线连接化合物半导体芯片63的各电极焊盘和引线62。用与模制模具的形状一致的树脂层80覆盖半导体芯片63的周边部分，引线62的前端部分导出树脂层80的外部。以在树脂模制时树脂层不会进入程度的间隔距离，在FET72上设置由支柱支承的屏蔽金属70，从而可在树脂模制中，在FET72上产生中空部60。
图4(B)是概略表示上述芯片的剖面图。另外，FET的详细结构和图11(B)相同。在输入侧的源电极13(或漏电极15)和输出侧的漏电极15(或源电极13)之间配置栅电极17，将它们多组集成形成一个FET。在本发明的结构中，在这些FET72的上面全面设置屏蔽金属70，将该芯片固定安装在引线上用树脂模制。即，如图所示，用屏蔽金属70实质性屏蔽源电极13、漏电极15及栅电极17和树脂层80。
另外，和第一实施例同样，在屏蔽金属70上设置了2μm～5μm宽的狭缝，按该尺寸下树脂不能进入。另外，因为屏蔽金属70和FET的距离也是1μm～2μm，所以树脂不会进入，形成中空部60。
通过该中空部60，由介电常数低的空气屏蔽OFF侧FET的源漏电极间即IN-OUT间，所以可几乎屏蔽输入OFF侧FET的高频信号中经模制树脂层80泄漏到输出侧的信号。
图4(C)表示控制端子用电极焊盘Ctl-1Pad部的剖面图。FET上设置的屏蔽金属70一直延伸到控制端子用电极焊盘Ctl-1Pad，与由栅极金属层20、焊盘金属层30形成的控制端子用电极焊盘Ctl-1Pad接触。键合线64固定焊接在屏蔽金属70上。
本发明的开关电路装置中，如上所述对控制端子Ctl-1施加0V或3V的控制信号进行开关动作，所以根据该结构屏蔽金属70上也就会施加3V或0V的DC电位。因为DC电位在高频下为GND电位，所以就会由GND电位将OFF侧FET的源-漏电极间即IN-OUT间屏蔽。因而，输入OFF侧FET的高频信号中，原来经模制树脂层80泄漏到输出侧的信号作为空气中三维扩展的电磁场泄漏的部分也被屏蔽金属70吸收，可实现隔离效果更高的结构。
本实施例中，屏蔽金属70是和控制端子用电极焊盘Ctl-1接触的，当然也可以和控制端子用电极焊盘Ctl-2接触。即，只要使施加DC电位的端子和屏蔽金属连接即可，在具有GND端子、电源电压端子等的开关电路装置的情况下，只要和GND端子、电源电压端子用电极焊盘接触即可。
另外，图5表示本发明的第三实施例。本实施例是屏蔽金属70不设置狭缝的结构。如后详述地，在本发明中，通过在抗蚀剂上设置屏蔽金属70，然后除去抗蚀剂形成中空结构。另外，为了除去该屏蔽金属70下的残留抗蚀剂，在屏蔽金属70设置狭缝作为抗蚀剂消除液的通路。但是，若要消除的抗蚀剂区域即中空部的面积比较小，则即使不设置狭缝也可以消除。具体地说，如果想要实现中空结构的FET部的面积在50μm×50μm以下，则可以不设置狭缝而在整个面上设置屏蔽金属，可用屏蔽金属完全遮蔽FET的上面。
以下用图6～图8说明本发明的开关电路装置的制造方法。
本发明开关电路装置的制造方法在半导体衬底上形成具有沟道区域、源区及漏区的FET，并形成与所述FET连接的输入端子、输出端子及施加DC电位的端子各自对应的电极焊盘；其包括下述工序：在所述FET周围形成支柱，由所述支柱支承并至少覆盖所述FET上面的金属层的工序；和由树脂层覆盖集成了所述FET的芯片的工序。
在本发明的第一工序，如图6所示，利用已知方法，在半导体衬底上形成开关电路装置。即，在半导体衬底上形成具有沟道区域、源区及漏区的FET，并形成和所述FET连接的输入端子、输出端子用电极焊盘，及施加DC电位的端子用电极焊盘。
即如图6(A)所示，由约100到200厚度的贯穿离子注入用硅氮化膜覆盖用GaAs等形成的化合物半导体衬底11整个面。然后，为了向预定的沟道层12选择动作层，而进行赋予p-型的杂质(24Mg+)的离子注入及赋予n型的杂质(29Si+)的离子注入。在非掺杂的衬底11上形成p-型区域，在其上形成n型沟道层12。然后，在预定的源区18及漏区19、预定的布线层162及焊盘电极170之下的衬底表面上进行赋予n型的杂质(29Si+)的离子注入。由此，形成n+型的源区18及漏区19，同时在预定的焊盘区域170及布线层162之下的衬底表面上形成高浓度区域160、161。在此，通过在焊盘电极170及布线层162的下面比这些区域鼓出而设置高浓度区域160、161，不将焊盘电极170及布线层162直接设置在GaAs衬底上，也可充分确保相互的隔离。
再有，在形成高浓度区域160、161时，同时在支柱71形成区域下的衬底表面上也可形成分离区域的高浓度区域100。由此，可以将与支柱71相邻的构成开关电路装置的元件(例如FET的漏区等)的分离距离接近到4μm来配置。
另外，如图7(B)所示，在所述源区18及漏区19上作为第一层电极，顺序真空蒸镀并层积欧姆金属层即AnGe/Ni/Au这3层，形成第一源电极14及第一漏电极16。接着通过合金化热处理形成第一源电极14和源区18及第一漏电极16和漏区19的欧姆结。
另外，在所述沟道层12及所述高浓度区域160、161上顺序真空蒸镀并层积作为第二层电极的栅极金属层的Ti/Pt/Au这3层，形成与沟道层12接触的栅极17和第一焊盘电极170及布线层162。
然后，在图6(C)中，在第一源电极14及第一漏电极16和第一焊盘电极170上顺序真空蒸镀并层积作为第三层电极的焊盘金属层即Ti/Pt/Au这3层，形成与第一源电极14、第一漏电极16及第一焊盘电极170接触的第二源电极13及第二漏电极15和第二焊盘电极177。
此外，在硅半导体开关电路装置的情况下，在省略图示的高浓度衬底上设置的外延层中，在预定的支柱形成区域下形成高浓度区域或LOCOS氧化膜的分离区域100，并且形成开关电路装置的元件，支柱和屏蔽金属与以下工序同样地形成(参照图3(B)、图3(C))。
本发明的第二工序如图7所示，在所述FET周围形成支柱，形成由所述支柱支承并至少覆盖所述FET上面的金属层。
本工序是作为本发明第一特征的工序。
首先，如图7(A)所示，在整个面上形成抗蚀剂PR1，进行光刻处理，选择性地使FET周围的预定的支柱71形成区域开窗，除去预定的支柱71形成区域的氮化膜，露出GaAs衬底。
这里FET图示了1组源电极、漏电极、栅电极。但实际上，如图1所示该FET配置有多组。
以下如图7(B)所示，在整个面上蒸镀例如Ti/Pt/Au等，形成镀敷用衬底金属180。设置新的抗蚀剂PR2，进行光刻处理，选择性地使屏蔽金属70形成区域开窗。另外，在屏蔽金属70形成区域中，因为为了防止抗蚀剂残留而形成狭缝，故在狭缝部分残留抗蚀剂PR2。在此，因为镀敷用抗蚀剂PR2涂敷在设置于整个面上的镀敷用衬底金属上，所以与形成支柱时设置的抗蚀剂PR1，被该镀敷用衬底金属180上下完全分离。
然后，进行镀金，除去光致抗蚀剂PR2，离子蚀刻露出的衬底电极180。由此，和支柱71一体化，形成实质上覆盖FET72上面整个面的屏蔽金属70。另外，狭缝90也同时形成(图7(C))。
之后，通过除去形成支柱71时设置的抗蚀剂PR1，在FET72和屏蔽金属70之间形成中空部60。这时，当屏蔽金属70的面积大时，抗蚀剂PR1就会不完全除去，容易残留抗蚀剂PR1。为了防止这一点，在屏蔽金属70上设置狭缝90，将该狭缝90用作抗蚀剂消除液的通路。抗蚀剂消除液从邻接的支柱71之间和狭缝90渗入，完全消除屏蔽金属下的抗蚀剂PR1。由此形成中空部60(图7(D))。
FET72上的中空部60只要能屏蔽高频信号即可，没有必要设置得很厚。根据上述方法，即使为了形成中空部60而设置屏蔽金属70，与现有技术相比，可忽略因形成屏蔽金属造成的芯片厚度的增加，所以封装外形的厚度不会变大。
而且，在图3所示的第二实施例的情况下，在图7(A)的使支柱71部分露出的光刻工序中，使屏蔽金属70接触的控制端子用电极焊盘Ctl-1Pad部分也同时开口。
然后，进行图7(B)～图7(D)的工序，如图7(E)所示形成和控制端子用电极焊盘Ctl-1Pad接触的屏蔽金属70。
本发明的第三工序是用树脂层覆盖集成了所述FET的芯片。
本工序是作为本发明的第二特征的工序。
当完成半导体开关电路装置的前部工序后，就移动到进行组装的后部工序。切开晶片状的半导体芯片，分离为独立的半导体芯片，在将半导体芯片63固定安装在引线62的岛上后，用键合线64将半导体芯片63的焊盘电极和引线62连接。键合线64用金细线，用公知的球形接合进行连接。之后，进行传递模模制形成树脂封装，得到图2(A)或图4(A)所示的最终结构。
在此，屏蔽金属70和FET72离开1～2um左右而设置，树脂不能进入该空间中。另外，因为狭缝90宽也是2um～5um左右，故树脂也不能由此进入。即，通过设置由支柱71支承的屏蔽金属70，可以在通常的树脂模制工序中，在FET上形成中空部60。
这样，FET72和树脂层80由屏蔽金属70覆盖，并且，FET的源-漏极之间即开关的IN-OUT之间由介电常数低的空气屏蔽，可以防止高频信号的泄漏。
为使封装内部形成中空，也有例如将帽固定安装在装载半导体芯片的引线框架上进行模制的方法，这种情况下，会另外耗费帽的材料费及固定安装帽的工时费用等成本。但是，根据本发明的制造方法，仅用在晶片上形成开关电路元件的晶片处理工序就可以实现中空结构，与在组装工序实现中空结构相比，具有大幅度降低成本的优点。
在此，用图8说明本发明的第三实施例(图5)的制造方法。本实施例不在屏蔽金属70设置狭缝，用屏蔽金属70完全覆盖FET上面的全部。在要形成中空部的FET的形成区域为50um×50um以下的小面积的情况下，可不在屏蔽金属70上设置狭缝。这是由于如果屏蔽金属70的面积很小，则用从邻接的支柱71间渗入的抗蚀剂消除液可充分除去抗蚀剂PR1。
即，形成元件区域后，进行光刻处理选择性使支柱71部开孔，在进行氮化膜的蚀刻后，形成镀金的衬底电极180。设置新的抗蚀剂PR2，进行光刻处理选择性地使屏蔽金属70部分开窗(图8(A))。
然后，实施镀金除去抗蚀剂PR2，离子蚀刻露出的衬底金属。再除去抗蚀剂PR1，形成中空部60(图8(B))。
然后，进行树脂模制，形成最终结构(图2(A)、图4(A))。
另外，本实施例中，以化合物半导体开关电路装置为例进行了说明，但并不限于此，在硅半导体开关电路装置中也可以实施。
如上详述，如依照本发明可得到以下的效果。
第一、通过在FET上设置屏蔽金属，使FET和屏蔽金属间形成中空，可以抑制OFF侧FET的源-漏电极间(IN-OUT间)的高频信号的泄漏。树脂层和FET可由屏蔽金属屏蔽，并且FET的源-漏极之间即开关的IN-OUT间可由介电常数低的空气屏蔽，可以防止高频信号的泄漏。
第二，通过使屏蔽金属和控制端子用电极焊盘Ctl-1Pad接触，使隔离效果进一步提高。
在本发明的开关电路装置中，向控制端子Ctl-1施加0V或3V的控制信号进行开关动作，所以根据该结构屏蔽金属上也会被施加3V或0V的DC电位。因为DC电位在高频下为GND电位，所以就由GND电位将OFF侧FET的源-漏电极间即IN-OUT间屏蔽。因此，输入OFF侧FET的高频信号中，以往经由模制树脂层80向输出侧泄漏的信号，包括作为空气中三维扩展的电磁场泄漏的部分也可由屏蔽金属吸收，故可实现隔离效果更高的结构。
另外，根据本发明的制造方法，在晶片上形成开关电路装置的制造工艺中，容易在FET上形成中空部。作为中空封装的制造方法还有例如在载置半导体开关的引线框架上固定安装帽进行模制的方法，但这种情况下，要另外消耗帽的材料费及固定安装帽的工时费用等成本。而根据本发明的制造方法，仅通过在晶片上形成开关电路元件的光刻处理工序就可以实现中空结构，与在组装工序中实现中空结构相比，具有大幅度降低成本的优点。在组装工序中实现中空结构的方法中，作为在空气中三维扩展的电磁场，其泄漏的信号不能被吸收，故与由组装工序形成的中空结构相比，不仅可消减成本，而且可提高特性。

Claims (15)

1、一种半导体开关电路装置，包括：至少一个FET，在半导体衬底表面上设置有源电极、栅电极及漏电极；电极焊盘，与下述端子分别对应，所述端子是，至少一个连接在上述FET的源电极或漏电极上的输入端子，至少一个连接在上述FET的漏电极或源电极上的输出端子，及将DC电位施加在上述FET上的端子；其特征在于，还包括：
支柱，其设在上述FET的周围；金属层，由上述支柱支承并至少覆盖在上述FET之上；以及
树脂层，覆盖集成了上述FET的芯片。
2、如权利要求1所述的半导体开关电路装置，其特征在于，由所述金属层和所述FET形成的空间是中空的。
3、如权利要求1所述的半导体开关电路装置，其特征在于，所述金属层和所述FET以所述树脂层不会进入的程度离开。
4、如权利要求3所述的半导体开关电路装置，其特征在于，所述金属层和所述FET离开0.5μm～3μm。
5、如权利要求1所述的半导体开关电路装置，其特征在于，所述金属层是金属镀层。
6、如权利要求1所述的半导体开关电路装置，其特征在于，所述金属层上设有多个孔。
7、如权利要求1所述的半导体开关电路装置，其特征在于，所述金属层与施加所述DC电位的端子对应的电极焊盘接触。
8、如权利要求1所述的半导体开关电路装置，其特征在于，所述金属层覆盖所述FET上的整个面而设置。
9、如权利要求1所述的半导体开关电路装置，其特征在于，在所述支柱之下的所述衬底上设有分离区域。
10、如权利要求9所述的半导体开关电路装置，其特征在于，所述支柱和邻接的该开关电路装置的元件接近配置。
11、一种半导体开关电路装置的制作方法，其在半导体衬底上形成具有沟道区域、源区及漏区的FET，并形成和所述FET连接的输入端子、输出端子及施加DC电位的端子各自对应的电极焊盘，其特征在于，所述方法包括下述工序，
在上述FET周围形成支柱，并形成由上述支柱支承并至少将上述FET之上覆盖的金属层；
由树脂层覆盖集成了上述FET的芯片。
12、如权利要求11所述的半导体开关电路装置的制造方法，其特征在于，还具有：至少在所述FET上形成抗蚀剂掩模、在形成所述金属层后除去所述抗蚀剂掩模、将所述FET和所述金属层之间形成中空的工序。
13、如权利要求12所述的半导体开关电路装置的制造方法，其特征在于，在形成所述金属层时，在该金属层形成多个孔，在所述抗蚀剂掩模除去工序中将所述孔用作抗蚀剂除去液的通路。
14、如权利要求11所述的半导体开关电路装置的制造方法，其特征在于，所述金属层利用金属镀敷形成。
15、如权利要求11所述的半导体开关电路装置的制造方法，其特征在于，在形成所述支柱之前，在支柱形成区域的所述衬底上形成分离区域。
CNB031104886A 2002-04-17 2003-04-17 半导体开关电路装置及其制造方法 Expired - Fee Related CN1291492C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP114959/2002 2002-04-17
JP2002114959 2002-04-17
JP114959/02 2002-04-17

Publications (2)

Publication Number Publication Date
CN1455458A CN1455458A (zh) 2003-11-12
CN1291492C true CN1291492C (zh) 2006-12-20

Family

ID=29267331

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB031104886A Expired - Fee Related CN1291492C (zh) 2002-04-17 2003-04-17 半导体开关电路装置及其制造方法

Country Status (3)

Country Link
US (1) US6853072B2 (zh)
EP (1) EP1363331A3 (zh)
CN (1) CN1291492C (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10951174B2 (en) 2016-10-24 2021-03-16 Mitsubishi Electric Corporation High-frequency amplifier

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7157385B2 (en) 2003-09-05 2007-01-02 Micron Technology, Inc. Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
US20030062610A1 (en) * 2001-09-28 2003-04-03 Kovacs Alan L. Multilayer thin film hydrogen getter
TWI236754B (en) * 2003-04-18 2005-07-21 Phoenix Prec Technology Corp Method for plating metal layer over isolated pads on substrate for semiconductor package substrate
KR100547709B1 (ko) * 2003-07-07 2006-01-31 삼성전자주식회사 자기 치유 파장분할다중방식 수동형 광 가입자망
CN100444371C (zh) 2004-09-13 2008-12-17 国际整流器公司 功率半导体封装
US7510966B2 (en) 2005-03-07 2009-03-31 Micron Technology, Inc. Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines
JP4575247B2 (ja) * 2005-07-11 2010-11-04 株式会社東芝 高周波パッケージ装置
JP2009176930A (ja) * 2008-01-24 2009-08-06 Toshiba Corp 半導体装置およびその製造方法
JP2010272749A (ja) * 2009-05-22 2010-12-02 Murata Mfg Co Ltd 半導体装置
US20120009777A1 (en) 2010-07-07 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. UBM Etching Methods
US9030841B2 (en) * 2012-02-23 2015-05-12 Apple Inc. Low profile, space efficient circuit shields
JP5865275B2 (ja) * 2013-01-25 2016-02-17 株式会社東芝 高周波半導体スイッチ
US9659717B2 (en) 2014-02-18 2017-05-23 Analog Devices Global MEMS device with constant capacitance
US9748048B2 (en) 2014-04-25 2017-08-29 Analog Devices Global MEMS switch
US9583294B2 (en) 2014-04-25 2017-02-28 Analog Devices Global MEMS swtich with internal conductive path
JP6540528B2 (ja) 2016-02-04 2019-07-10 三菱電機株式会社 半導体装置及びその製造方法
US10640363B2 (en) 2016-02-04 2020-05-05 Analog Devices Global Active opening MEMS switch device
DE102018212438A1 (de) * 2018-07-25 2020-01-30 Infineon Technologies Ag Halbleitergehäuse mit elektromagnetischer abschirmstruktur und verfahren zu dessen herstellung

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63124467A (ja) * 1986-11-13 1988-05-27 Seiko Epson Corp 半導体装置
JPH0232546A (ja) * 1988-07-22 1990-02-02 Hitachi Ltd 化合物半導体デバイス
JPH03218653A (ja) * 1989-11-13 1991-09-26 Mitsubishi Electric Corp エアーブリッジ金属配線を具えた半導体装置およびその製造方法
DE69023765T2 (de) * 1990-07-31 1996-06-20 Ibm Verfahren zur Herstellung von Bauelementen mit übereinander angeordneten Feldeffekttransistoren mit Wolfram-Gitter und sich daraus ergebende Struktur.
JPH0817186B2 (ja) * 1992-03-18 1996-02-21 三星電子株式会社 電界効果トランジスタの製造方法
US5965452A (en) * 1996-07-09 1999-10-12 Nanogen, Inc. Multiplexed active biologic array
JP2773685B2 (ja) * 1995-06-16 1998-07-09 日本電気株式会社 半導体装置
JPH09232827A (ja) * 1996-02-21 1997-09-05 Oki Electric Ind Co Ltd 半導体装置及び送受信切り替え型アンテナスイッチ回路
JP3831575B2 (ja) * 2000-05-15 2006-10-11 三洋電機株式会社 化合物半導体スイッチ回路装置
JP2002026035A (ja) * 2000-07-05 2002-01-25 Hitachi Ltd 半導体集積回路装置
TWI252582B (en) * 2001-02-27 2006-04-01 Sanyo Electric Co Switch circuit device
US6472962B1 (en) * 2001-05-17 2002-10-29 Institute Of Microelectronics Inductor-capacitor resonant RF switch
US6531668B1 (en) * 2001-08-30 2003-03-11 Intel Corporation High-speed MEMS switch with high-resonance-frequency beam

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10951174B2 (en) 2016-10-24 2021-03-16 Mitsubishi Electric Corporation High-frequency amplifier

Also Published As

Publication number Publication date
US6853072B2 (en) 2005-02-08
EP1363331A2 (en) 2003-11-19
EP1363331A3 (en) 2006-05-17
CN1455458A (zh) 2003-11-12
US20040021156A1 (en) 2004-02-05

Similar Documents

Publication Publication Date Title
CN1291492C (zh) 半导体开关电路装置及其制造方法
US11888027B2 (en) Monolithic integration of high and low-side GaN FETs with screening back gating effect
TWI538149B (zh) 低電磁干擾電路之封裝組態
JP5567513B2 (ja) シリコンおよびｉｉｉ−ｖ族のモノリシック集積デバイス
US9324645B2 (en) Method and system for co-packaging vertical gallium nitride power devices
US9431394B2 (en) Power semiconductor package with gate and field electrode leads
US20080017998A1 (en) Semiconductor component and method of manufacture
US12119343B2 (en) Semiconductor structure having a semiconductor substrate and an isolation component
CN1372381A (zh) 开关电路装置
CN1238896C (zh) 半导体开关电路器件
CN1193427C (zh) 化合物半导体开关电路装置
US10411126B2 (en) Semiconductor device having a first through contact structure in ohmic contact with the gate electrode
TWI222191B (en) Semiconductor switch circuit device and manufacturing method therefor
CN1901196A (zh) 具有高频开关电路的高频装置
CN1282256C (zh) 半导体装置
CN107026197B (zh) 半导体装置和制造半导体装置的方法
US11031388B2 (en) Semiconductor structure and driving chip
CN1194470C (zh) 开关电路装置
CN114864528A (zh) 半导体器件和半导体器件的制造方法
US10998305B2 (en) Semiconductor die
JPH10136642A (ja) Ｄｃ−ｄｃコンバータ装置
CN1215539C (zh) 化合物半导体装置的制造方法
DE102022120578B4 (de) Halbleitervorrichtung und elektronische vorrichtung
CN1187801C (zh) 化合物半导体装置的制造方法
JP4574624B2 (ja) 半導体装置および半導体装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20061220