CN114864528A - 半导体器件和半导体器件的制造方法 - Google Patents

半导体器件和半导体器件的制造方法 Download PDF

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Publication number
CN114864528A
CN114864528A CN202210111341.0A CN202210111341A CN114864528A CN 114864528 A CN114864528 A CN 114864528A CN 202210111341 A CN202210111341 A CN 202210111341A CN 114864528 A CN114864528 A CN 114864528A
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Prior art keywords
die
semiconductor device
encapsulant
terminal
mosfet
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CN202210111341.0A
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周安乐
王飞莹
李家诚
王志伟
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Nexperia BV
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Nexperia BV
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Publication of CN114864528A publication Critical patent/CN114864528A/zh
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Abstract

本发明涉及一种半导体器件以及制造半导体器件的方法，该半导体器件包括例如GaN HEMT管芯的第一管芯，以及例如MOSFET管芯的第二管芯，第二管芯位于第一管芯的顶部。使用管芯附接粘合剂来附接第二管芯。半导体器件还包括沉积在半导体器件顶部上的密封剂，该密封剂覆盖第一管芯和第二管芯。在密封剂内形成金属化导通孔，其中，金属化导通孔布置成将第一管芯的端子和第二管芯的端子分布到半导体器件的顶面。

Description

半导体器件和半导体器件的制造方法
技术领域
本发明涉及一种包括以共源共栅(级联)(cascode)构造定位的两个管芯(die)的半导体器件。本发明还涉及一种半导体器件的制造方法。
背景技术
本领域已知的WBG(宽带隙)器件为常开型，例如碳化硅(SiC)结栅场效应晶体管(JFET)、耗尽型氮化镓(GaN)高电子迁移率晶体管(HEMT)等。为了确保安全运行，硅金属氧化物半导体场效应晶体管(MOSFET)器件通常以共源共栅的方式与WBG器件连接，以使WBG器件处于常关运行模式。所述共源共栅可以构建为并排构造或堆叠管芯构造。
通常，如本领域已知的，堆叠管芯构造提供某些优点，例如：
-简化的管芯附接互连方案，
-由于器件的直接连接而具有更好的源漏导通电阻(Rdson)，
-不需要直接覆铜(DBC)基板，以及
-更多的空间可以用于容纳更大的电力管芯(功率管芯)。
图1a和图1b分别示出了并排构造和堆叠管芯构造的已知示例。
已知GaN HEMT器件被级联(cascoded)至各种封装类型中。
本领域中还已知的是，对于典型的电力(功率)模块结构，通常使用多个裸管芯来代替分立封装，以便在模块基板上的有限区域内实现更灵活和更有效的布局。为了进一步增强性能和减小尺寸，堆叠管芯是发展趋势。然而，直接供应堆叠管芯将造成包括已知合格芯片(KGD)问题的许多技术挑战。
在专利US9721944B2中对一种已知的半导体器件进行描述。在此专利中公开了一种外部互连的管芯焊盘结构。
如图2所示，通过将高压常开双极开关芯片和低压常关FET芯片并排管芯安装在金属化陶瓷基板板上来实现混合半导体双极开关。通过引线结合来实现芯片之间的连接和与基板的连接。陶瓷材料可以是例如氮化铝、氧化铝、氮化硅或类似材料。陶瓷板上的金属化部可以是例如直接覆铜(DBC)、活性钎焊铜(ABC)、钼基合金等，该金属化部中的任何一种可以与钛、钨、镍、铂和/或金涂层组合，以便于管芯附接和/或防止各种金属化层的相互扩散和氧化。类似地，可以将各种涂层覆盖在附接和/或结合该各种涂层的半导体芯片上。
还可以通过将低压常关FET芯片直接安装至高压常开双极开关芯片的结合焊盘上使混合开关实现为“堆叠”器件。图2是这种器件的示例的截面图。如图2所示，常开双极开关芯片301具有用于低电压、高电流连接的结合焊盘305。结合焊盘305与芯片301上的IGBT的发射极连接。芯片301使用诸如焊料或导电粘合剂等管芯附接材料302附接至金属表面310。金属表面310部分地是绝缘陶瓷板或引线框架。利用管芯附接材料304将低电压常关FET芯片306安装至结合焊盘305上。FET芯片306的栅极端子309用于堆叠共源共栅部200的栅极控制。经由互连件307使FET芯片306的源极端子308与常开双极开关芯片301的栅极端子303连接。在本构造中，常开双极开关301和低压常关开关306之间的高电流互连件的寄生串联电阻和电感将得到最小化，从而在高di/dt和dv/dt条件下切换期间，减少不期望的电压过冲。
发明内容
各个示例性实施例针对如上所述的缺点和/或从以下公开中可以变得显而易见的其它缺点。
根据本发明的实施例，半导体器件包括第一管芯(例如，GaN HEMT管芯)和位于第一管芯顶部的第二管芯(例如，MOSFET管芯)。使用管芯附接粘合剂或焊料来附接第二管芯。半导体器件还包括沉积在半导体器件顶部上的密封剂，该密封剂覆盖第一管芯和第二管芯。在密封剂内形成金属化导通孔，其中金属化导通孔布置成将第一管芯的端子和第二管芯的端子分布到半导体器件的顶面。
在本发明的实施例中，MOSFET管芯的栅极端、MOSFET管芯的源极端、GaN HEMT管芯的栅极端和GaN HEMT管芯的漏极端经由金属化导通孔分布到半导体器件的顶面。
半导体器件可以是电力(功率)半导体器件。
本发明还涉及一种制造半导体器件的方法。该方法包括以下步骤：
-将第一管芯(例如，GaN HEMT管芯)附接在膜载体上，
-使用管芯附接粘合剂或焊料将第二管芯(例如，MOSFET管芯)附接在第一管芯上，
-固化管芯附接粘合剂或焊料，
-利用模塑料(mold compound)或其它密封剂来密封第一管芯和第二管芯，
-利用激光在密封剂内钻孔出导通孔直至第一管芯的焊盘和第二管芯的焊盘，
-使导通孔金属化，以便为第一管芯和为第二管芯建立电接触，
-在密封剂上烧结厚Cu膜，以便产生半导体器件的端子，可以使用替代的金属材料，诸如在密封剂上烧结厚Ag膜。
-分割半导体器件。
该方法还可以包括在厚Cu膜上沉积有机可焊性保护剂(organic solderabilitypreservative)以防止Cu氧化的步骤。
本发明实施例中描述的新型封装具有显著优点：
-封装外形适于在集成器件制造(IDM)和客户模块组装中相对容易制造。
-确保占地面积减少，例如从12×12(CCPAK)减少至5×6(近芯片级封装)
-启用KGD的最终测试和老化
-半导体封装端子可以设计用于诸如倒装芯片、Cu引线结合等高级组装。
根据本发明实施例的半导体封装适于客户可以将多个封装连接在一起以用于各种特定电源应用的电力模块(功率模块)。作为裸管芯的代替，封装可以支持测试和老化，并且向客户提供KGD(已知合格芯片)解决方案。近芯片级封装还降低电力模块的有限空间内的占地面积要求，并且改善电气和热性能。封装端子可以在模块组装中利用不同的互连技术，并且端子位置可以得到重新分布以用于更灵活的基板布局。
附图说明
为了能够详细理解本公开的特征的方式，参照实施例进行更具体的描述，其中一些实施例在附图中示出。然而，应当注意的是，附图仅示出了典型实施例，因此不应认为是对其范围的限制。附图是为了便于理解本公开，因此不一定按比例绘制。在结合附图阅读本说明书后，所要求保护的主题的优点对于本领域技术人员将变得显而易见，在附图中，相同的附图标记用于表示相同的元件，其中：
图1a和图1b示出了已知的半导体器件；
图2示出了已知的半导体器件；
图3示出了根据本发明的实施例的半导体器件；
图4示出了根据本发明的实施例的制造半导体器件的方法；
图5示出了根据本发明的实施例的半导体器件；
图6a和图6b示出了根据本发明实施例的半导体器件。
具体实施方式
图3示出了本发明的实施例。半导体封装100包括GaN HEMT管芯104。GaN HEMT包括露出的背面102。MOSFET管芯108位于GaN HEMT管芯104的顶面上，并且通过管芯附接粘合剂或焊料106将MOSFET管芯108附接至GaN HEMT管芯104。密封剂110沉积在整个半导体封装的顶部，即GaN HEMT管芯104和MOSFET管芯108两者的顶部。在密封剂110内存在激光钻孔的并金属化的导通孔112。封装接触端子114的Cu膜放置在这些导通孔112的顶面上。在图3中，还示出了半导体封装100的顶视图。在半导体器件的所述顶视图中可见MOSFET管芯120的栅极端、MOSFET管芯122的源极端、GaN HEMT管芯124的栅极端、GaN HEMT管芯126的漏极端。
尽管图3所示的实施例涉及GaN HEMT管芯和MOSFET管芯，但本发明还涵盖具有共源共栅操作的所有种类的宽带隙半导体器件和封装。
本发明涉及一种在电力模块中实现KGD堆叠管芯组装的近芯片级封装方法，与单独的裸管芯组装或常规分立封装相比，该方法明显具有优势。
根据本发明实施例的封装适于WBG器件的封装，例如适于D型GaN HEMT、SiC JFET等，这些器件需要额外的硅MOSFET的共源共栅以实现安全的常关操作。根据本发明实施例的半导体器件用于各种产品，例如电力模块。
图3所示的示例性实施例仅是由本发明所涵盖的可能性中的一个。本发明的范围包括所有类似的实施例和变型。
使用GaN HEMT管芯以用于说明的图3所示的示例性实施例具有以下关键特征：
-驱动管芯以堆叠管芯的构造附接至电力管芯。
-堆叠管芯组件被封装，其中电力管芯的背面露出或在另一设计中周围露出5个面。
-通过激光钻孔的、并且金属化的导通孔将驱动管芯的接触焊盘和电力管芯的接触焊盘连接至封装端子。
-使用印刷或分配方法通过Cu烧结或替代的金属烧结来形成封装端子。
图4示出了本发明的实施例。制造半导体封装的方法包括以下步骤：
-图4中的附图标记202：
o将GaN HEMT管芯104附接在膜载体上
o使用管芯附接粘合剂106将MOSFET管芯108附接在GaN HEMT管芯104上
o固化管芯附接材料
-图4中的附图标记204：
o利用模塑料或其它密封剂110密封堆叠管芯组件
-图4中的附图标记206：
o激光钻孔出导通孔112直至管芯焊盘；多个导通孔能够改善半导体封装的性能
-图4中的附图标记208：
o金属化113导通孔，形成半导体封装的电接触
-图4中的附图标记210：
o在密封剂110上烧结厚Cu膜以产生到导通孔的封装端子连接部114
o可以施加有机保焊剂(OSP)以防止Cu氧化
-图4中的附图标记212：
o分割成单个单元，例如通过刀片切割
根据本发明的实施例，在共源共栅电路内，MOSFET管芯的源极和WBG管芯的栅极连接在一起。可以在模块基板表面上完成这种连接。这在图5中示出。
如图6a所示，可以使用已知的板安装方法(例如焊接、烧结等)将堆叠管芯封装以倒装芯片的方式结合至模块基板上。将应用兼容的接触金属化。
此外，如图6b所示，可以使用普通管芯附接方法将堆叠管芯封装结合至模块基板上。可以使用Cu引线结合将焊盘与基板连接。
根据本发明的实施例，栅极接触可以重新定位至晶片的背面以在互连中提供了更多灵活性。
本发明还可以应用于竖直器件，例如SiC FET。在这种情况下，封装背面是漏极焊盘。
根据本发明的实施例，代替引线框架载体，可以在晶片级上直接处理堆叠管芯组件。
本发明还涉及多个堆叠管芯单元。可以通过最终分割方法来产生双堆叠管芯封装。双堆叠管芯还可以构造成用于例如半桥的特定应用，该双堆叠管芯具有新的端子焊盘几何形状和封装顶面上的连接布线，由印刷或分配Cu烧结材料的新图案形成。
在所附独立权利要求中阐述本发明的特定和优选方面。可以适当组合从属和/或独立权利要求的特征的组合，而不仅仅是如权利要求中所阐述的组合。
本公开的范围包括其中明确或隐含公开的任何新颖特征或特征的组合或其任何概括，而无论其是否涉及所要求保护的发明或减轻由本发明解决的任何或所有问题。由此，申请人特此申明，在本申请或从其衍生的任何此种其它申请的审查期间，可以针对这些特征提出新的权利要求。特别地，参照所附权利要求，来自从属权利要求的特征可以与独立权利要求的特征组合，并且来自各个独立权利要求的特征可以以任何适当方式组合，而不仅仅是在权利要求中列举的特定组合。
还可以在单个实施例中组合提供在单独实施例的上下文中描述的特征。相反，为了简洁起见，还可以单独或以任何合适的子组合提供在单个实施例的上下文中描述的各种特征。
术语“包括”不排除其它元件或步骤，术语“一”或“一个”不排除多个。权利要求中的附图标记不应解释为限制权利要求的范围。

Claims (8)

1.一种半导体器件包括：
第一管芯，
第二管芯，其定位在所述第一管芯的顶部上，所述第二管芯使用管芯附接粘合剂或焊料附接，
密封剂，其沉积在所述半导体器件的顶部，所述密封剂覆盖所述第一管芯和所述第二管芯，
金属化导通孔，其在所述密封剂内，其中，所述金属化导通孔布置成将所述第一管芯的端子和所述第二管芯的端子分布到所述半导体器件的顶面。
2.根据权利要求1所述的半导体器件，其中，所述第一管芯是GaN HEMT管芯。
3.根据前述权利要求中任一项所述的半导体器件，其中，所述第二管芯是MOSFET管芯。
4.根据权利要求3所述的半导体器件，其中，所述MOSFET管芯的栅极端子、所述MOSFET管芯的源极端子、所述GaN HEMT管芯的栅极端子和所述GaN HEMT管芯的漏极端子经由所述金属化导通孔分布到所述半导体器件的所述顶面。
5.根据前述权利要求中任一项所述的半导体器件，其中，所述半导体器件是电力半导体器件。
6.一种制造半导体器件的方法，所述方法包括以下步骤：
将第一管芯附接在膜载体上，
使用管芯附接粘合剂或焊料将第二管芯附接在所述第一管芯上，
固化所述管芯附接粘合剂或焊料，
利用模塑料或其它密封剂来密封所述第一管芯和所述第二管芯，
利用激光在所述密封剂内钻孔出导通孔直至所述第一管芯的焊盘和所述第二管芯的焊盘，
使所述导通孔金属化，以便为所述第一管芯和为所述第二管芯建立电接触，
在所述密封剂上烧结厚Cu膜或替代的金属膜，以便产生所述半导体器件的端子，
分割所述半导体器件。
7.根据权利要求6所述的制造半导体器件的方法，其中，所述方法包括在所述厚Cu膜上沉积有机可焊性保护剂以防止Cu氧化的步骤。
8.根据权利要求6或7所述的制造半导体器件的方法，其中，所述第一管芯是GaN HEMT管芯，并且其中所述第二管芯是MOSFET管芯。
CN202210111341.0A 2021-02-03 2022-01-29 半导体器件和半导体器件的制造方法 Pending CN114864528A (zh)

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