JP2006522486A5 - - Google Patents

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JP2006522486A5
JP2006522486A5 JP2006509467A JP2006509467A JP2006522486A5 JP 2006522486 A5 JP2006522486 A5 JP 2006522486A5 JP 2006509467 A JP2006509467 A JP 2006509467A JP 2006509467 A JP2006509467 A JP 2006509467A JP 2006522486 A5 JP2006522486 A5 JP 2006522486A5
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fin
gate
insulating layer
etching
layer
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JP2006509467A
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JP5409997B2 (ja
JP2006522486A (ja
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JP2006509467A 2003-04-03 2004-03-30 ＦｉｎＦＥＴデバイス中にゲートを形成する方法、および半導体デバイスの製造方法 Expired - Lifetime JP5409997B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/405,342 US6764884B1 (en) 2003-04-03 2003-04-03 Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US10/405,342 2003-04-03
PCT/US2004/009669 WO2004093181A1 (en) 2003-04-03 2004-03-30 Method for forming a gate in a finfet device and thinning a fin in a channel region of the finfet device

Publications (3)

Publication Number Publication Date
JP2006522486A JP2006522486A (ja) 2006-09-28
JP2006522486A5 true JP2006522486A5 (enExample) 2012-08-09
JP5409997B2 JP5409997B2 (ja) 2014-02-05

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JP2006509467A Expired - Lifetime JP5409997B2 (ja) 2003-04-03 2004-03-30 ＦｉｎＦＥＴデバイス中にゲートを形成する方法、および半導体デバイスの製造方法

Country Status (8)

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US (1) US6764884B1 (enExample)
JP (1) JP5409997B2 (enExample)
KR (1) KR101079348B1 (enExample)
CN (1) CN100413039C (enExample)
DE (1) DE112004000578B4 (enExample)
GB (1) GB2417134B (enExample)
TW (1) TWI337392B (enExample)
WO (1) WO2004093181A1 (enExample)

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