JP2006518151A5 - - Google Patents

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Publication number
JP2006518151A5
JP2006518151A5 JP2006503296A JP2006503296A JP2006518151A5 JP 2006518151 A5 JP2006518151 A5 JP 2006518151A5 JP 2006503296 A JP2006503296 A JP 2006503296A JP 2006503296 A JP2006503296 A JP 2006503296A JP 2006518151 A5 JP2006518151 A5 JP 2006518151A5
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JP
Japan
Prior art keywords
vco
frequency
pll
phase difference
reference frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006503296A
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English (en)
Japanese (ja)
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JP2006518151A (ja
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Publication date
Priority claimed from US10/367,007 external-priority patent/US6774732B1/en
Application filed filed Critical
Publication of JP2006518151A publication Critical patent/JP2006518151A/ja
Publication of JP2006518151A5 publication Critical patent/JP2006518151A5/ja
Pending legal-status Critical Current

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JP2006503296A 2003-02-14 2004-02-04 ２パイ・スリップ検出を用いて位相同期ループ（ｐｌｌ）シンセサイザを粗調整するためのシステムおよび方法 Pending JP2006518151A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/367,007 US6774732B1 (en) 2003-02-14 2003-02-14 System and method for coarse tuning a phase locked loop (PLL) synthesizer using 2-PI slip detection
PCT/US2004/003098 WO2004075411A2 (en) 2003-02-14 2004-02-04 System and method for coarse tuning a phase locked loop (pll) synthesizer using 2-pi slip detection

Publications (2)

Publication Number Publication Date
JP2006518151A JP2006518151A (ja) 2006-08-03
JP2006518151A5 true JP2006518151A5 (https=) 2007-03-22

Family

ID=32824695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006503296A Pending JP2006518151A (ja) 2003-02-14 2004-02-04 ２パイ・スリップ検出を用いて位相同期ループ（ｐｌｌ）シンセサイザを粗調整するためのシステムおよび方法

Country Status (6)

Country Link
US (1) US6774732B1 (https=)
JP (1) JP2006518151A (https=)
KR (1) KR101082724B1 (https=)
CN (1) CN100483947C (https=)
TW (1) TW200509537A (https=)
WO (1) WO2004075411A2 (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7224951B1 (en) * 2003-09-11 2007-05-29 Xilinx, Inc. PMA RX in coarse loop for high speed sampling
US6954091B2 (en) * 2003-11-25 2005-10-11 Lsi Logic Corporation Programmable phase-locked loop
US7248122B2 (en) * 2005-09-14 2007-07-24 Fairchild Semiconductor Corporation Method and apparatus for generating a serial clock without a PLL
NL1031209C2 (nl) * 2006-02-22 2007-08-24 Enraf Bv Werkwijze en inrichting voor het nauwkeurig vaststellen van het niveau L van een vloeistof met behulp van naar het vloeistofniveau uitgestraalde radarsignalen en door het vloeistofniveau gereflecteerde radarsignalen.
US7412617B2 (en) 2006-04-06 2008-08-12 Mediatek Inc. Phase frequency detector with limited output pulse width and method thereof
KR100842727B1 (ko) * 2006-11-15 2008-07-01 삼성전자주식회사 전압 제어 발진기 및 이를 구비한 위상고정루프회로
US7692497B2 (en) * 2007-02-12 2010-04-06 Analogix Semiconductor, Inc. PLLS covering wide operating frequency ranges
NL1034327C2 (nl) * 2007-09-04 2009-03-05 Enraf Bv Werkwijze en inrichting voor het binnen een bepaald meetbereik vaststellen van het niveau L van een vloeistof met behulp van naar het vloeistofniveau uitgestraalde radarsignalen en door het vloeistofniveau gereflecteerde radarsignalen.
US8010072B1 (en) * 2008-06-18 2011-08-30 Atheros Communications, Inc. Charge pump current compensation for phase-locked loop frequency synthesizer systems
US8401140B2 (en) 2008-09-05 2013-03-19 Freescale Semiconductor, Inc. Phase/frequency detector for a phase-locked loop that samples on both rising and falling edges of a reference signal
US8224594B2 (en) * 2008-09-18 2012-07-17 Enraf B.V. Apparatus and method for dynamic peak detection, identification, and tracking in level gauging applications
US8659472B2 (en) * 2008-09-18 2014-02-25 Enraf B.V. Method and apparatus for highly accurate higher frequency signal generation and related level gauge
US8271212B2 (en) * 2008-09-18 2012-09-18 Enraf B.V. Method for robust gauging accuracy for level gauges under mismatch and large opening effects in stillpipes and related apparatus
US8513992B1 (en) * 2010-09-10 2013-08-20 Integrated Device Technology, Inc. Method and apparatus for implementation of PLL minimum frequency via voltage comparison
JP5703882B2 (ja) 2011-03-22 2015-04-22 富士通株式会社 デジタルｐｌｌ回路及びクロック生成方法
US8508308B2 (en) * 2011-09-01 2013-08-13 Lsi Corporation Automatic frequency calibration of a multi-LCVCO phase locked loop with adaptive thresholds and programmable center control voltage
US9046406B2 (en) 2012-04-11 2015-06-02 Honeywell International Inc. Advanced antenna protection for radars in level gauging and other applications
CN103067000B (zh) * 2012-12-17 2016-02-10 江汉大学 基于量子系统的伺服系统模型
US9350366B2 (en) 2013-10-18 2016-05-24 Raytheon Company Phase-locked loop filter with coarse and fine tuning
CN103684433B (zh) * 2013-12-18 2016-08-17 北京航天测控技术有限公司 一种宽带频综装置
KR102375949B1 (ko) 2015-01-02 2022-03-17 삼성전자주식회사 주파수 합성기의 출력을 제어하기 위한 장치 및 방법
US12052022B2 (en) * 2021-07-09 2024-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Coarse-mover with sequential finer tuning step

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4764737A (en) * 1987-11-20 1988-08-16 Motorola, Inc. Frequency synthesizer having digital phase detector with optimal steering and level-type lock indication
KR940005459A (ko) 1992-06-22 1994-03-21 모리시타 요이찌 Pll회로
US5686864A (en) 1995-09-05 1997-11-11 Motorola, Inc. Method and apparatus for controlling a voltage controlled oscillator tuning range in a frequency synthesizer
JP2845185B2 (ja) * 1995-11-29 1999-01-13 日本電気株式会社 Ｐｌｌ回路
JP2914287B2 (ja) * 1996-03-08 1999-06-28 日本電気株式会社 Ｐｌｌ回路
US5736904A (en) 1996-12-02 1998-04-07 Motorola, Inc. Automatic trimming of a controlled oscillator in a phase locked loop
US5942949A (en) * 1997-10-14 1999-08-24 Lucent Technologies Inc. Self-calibrating phase-lock loop with auto-trim operations for selecting an appropriate oscillator operating curve
US6256362B1 (en) * 1998-06-30 2001-07-03 Texas Instruments Incorporated Frequency acquisition circuit and method for a phase locked loop
US6313707B1 (en) * 1998-11-09 2001-11-06 Agere Systems Guardian Corp. Digital phase-locked loop with pulse controlled charge pump
FR2798019B1 (fr) * 1999-08-26 2002-08-16 Cit Alcatel Synthetiseur de frequences a boucle de phase
CN1307406A (zh) * 2000-01-27 2001-08-08 华为技术有限公司 数字锁相环的滤波方法
JP2001230667A (ja) * 2000-02-16 2001-08-24 Nec Corp 位相調整回路

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