Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
  • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
  • H03L7/102—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
  • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

• This invention relates in general to phase locked loops (PLL) and more particularly to the tuning of a voltage controlled oscillator (VCO) to stay within the operational range of a PLL synthesizer.
• PLL phase locked loops
• VCO voltage controlled oscillator
• VCO voltage controlled oscillator
• PLL phased locked loop
• RF radio frequency
• PLL phased locked loop
• a PLL is used to control the VCO in order to provide a highly stable source of RF energy preferably with low current drain.
• VCO voltage controlled oscillator
• One problem associated in using a voltage controlled oscillator (VCO) is that there are many different types of factors that work to change and/or vary the oscillators center frequency of operation. These factors include variations in VCO components, power supply restrictions that limit the dynamic range of the PLL and a need to lower the VCO frequency gain limiting PLL range. Many environmental conditions also contribute vary center frequency such as wide swings in ambient temperature. Often these deviations in center frequency can be extreme to the extent that the PLL will no longer operate due to this frequency deviation and the PLL's design limitations.
• modem wireless networked devices require low cost implementations and demand quick methods to tune the range of the integrated VCO. These methods are often required to be as simple as possible to reduce the cost of implementing the integrated VCO in a device.
• the time required to "tune” is important to reduce power dissipation and overall current drain in the device. The longer the device has to be in the "operational" state the greater the average current drain.
• a wireless network such as that defined by the Institute of Electrical and Electronics Engineers IEEE 802.15.4 WPAN standard, low power consumption is crucial.
• any modem VCO tuning method for wireless networked devices should be low in complexity with rapid speed in tuning.
• FIG. 1 illustrates a prior art circuit diagram of a commonly used phase-frequency detector (PFD) circuit 100.
• PFD phase-frequency detector
• the PFD 100 utilizes a plurality of flip-flops (101, 103, 105, 107) to compare the phase of a first input 111 and a second input 113.
• the PFD 100 determines whether the operational frequency of input signals needs to be increased or decreased to match the phase of these input signals. This information is output at the up output 115 and output 117.
• PFD 100 offers some unique benefits if the signals input to input 111 and input 113 are substantially distinct in frequency and phase. If the signals that are directed to input 111 and input 113 are greater than 360 degrees (2-pi or 2 ⁇ radians) out of phase, then PFD 100 offers the ability to provide a phase slip. As known in the art, a "phase slip" is the ability to detect a required amount of frequency correction that should be applied to keep the two input signals in-phase. Flip flop 105 and flip flop 107 as well as the OR gate 119 provide an ability to measure this phase slip.
• PFD 100 provides the ability to determine whether there are two "UP” frequency corrections before there is a “DOWN” frequency correction or alternatively ' whether there are two “DOWN” frequency corrections before there is an "UP” frequency correction.
• PFD 100 can determine with certainty that the signals provided to the inputs 111, 113 are more than 360 degrees out of phase. If the two input signals are too low in frequency, there will be a high pulse on the UP-SLIP output 121. Conversely if the two input signals are too high in frequency, there will be a high pulse generated on the DOWN-SLIP output 123.
• the OR gate 119 is used to remove the pulse once it is provided to either the UP-SLIP output 121 or DOWN -SLIP output 123.
• PFD 100 is used to provide a direction upon which to make a frequency correction.
• U.S. Patent 4,764,737 assigned to Motorola, Inc. describes this invention in detail and is herein incorporated by reference.
• Prior art techniques for tuning a VCO have used a "closed loop" operation of the
• a system and method for coarse tuning the voltage controlled oscillator (VCO) in a phase locked loop (PLL) synthesizer During a coarse tune mode, the voltage on the VCO input is forced to a predetermined nominal value by removing the charge pump from the PLL circuit and setting a desirable target bias for the VCO free running frequency.
• the circuit topology of the present invention uses a loop filter driven by the same voltage reference that also drives the input to the VCO. This has the effect of minimizing transients and settling the frequency of operation when the PLL switches from a "coarse tune" mode to normal closed loop tracking mode.
• the output of the VCO is compared to the reference frequency after a pre-determined frequency division.
• the phase detector is designed to output pulses whenever a 2 ⁇ slip occurs between the reference frequency and the divided down VCO.
• the 2 ⁇ slip pulses are used by a monitor and control circuit to estimate the error in the VCO's operating center frequency.
• the invention provides several methods by which to monitor and control is frequency.
• the output of the monitor and control circuit can then be used to control a second port in the VCO that acts to coarse tune the VCO without affecting its tune sensitivity.
• the present invention offers a distinct advantage in that the coarse tuning system does not require the closed loop operation of the PLL.
• the PLL quickly arrives at a final frequency adjustment solution, and can be used with VCOs that have overlapping and non-monotonic tune ranges.
• FIG. 1 is a prior art circuit diagram illustrating a common phase-frequency detector (PFD) circuit showing implementation of a typical 2 ⁇ slip detector.
• PFD phase-frequency detector
• FIG. 2 illustrates a block diagram of a phase locked loop (PLL) synthesizer using a phase frequency detector (PFD) with 2 ⁇ slip detection with monitor and control in accordance with the present invention.
• PLL phase locked loop
• PFD phase frequency detector
• FIG. 3 illustrates the preferred embodiment of the monitor and control circuit operating using 2 ⁇ radians frequency slips for adjusting VCO range.
• FIG. 4 and FIG. 5 illustrate alternative embodiments of the monitor and control circuit shown in FIG. 2.
• FIG. 2 a block diagram illustrating a phase locked loop (PLL) 200 that uses a 2 ⁇ slip detection system and method according to the present invention.
• the invention includes passing the 2 ⁇ radians slip information generated by a phase-frequency detector 201 to the monitor and control 215. Based upon input from the PFD 201, the monitor and control 215 then applies an increasing or decreasing frequency correction to one or more VCOs 211 via a coarse tune digital bus. Since the output of the VCOs 211 are fed directly to the input of the PFD 201, the VCO tuning becomes closer to the proper correction, there are fewer slip corrections. As will be evident to a skilled
• the system and methods used by the present invention are in direct contrast to the prior art since the information provided by PFD 201 is used to directly tune the frequency of the VCO 211 rather than through the charge pump 203.
• the PLL synthesizer 200 is illustrated as a "charge pump” PLL and includes a phase-frequency detector 201 that uses a frequency reference input (F ref ) and is used for determining the degree of frequency error is present in the PLL. Although shown as a charge pump PLL it will be recognized by those skilled in the art that the present invention might apply to other types of PLL circuits as well.
• a charge pump 203 is controlled by the PFD 201 where 'UP" frequency or “DOWN" frequency pulses are used to apply a charge to loop filter 209 in the direction that PFD 201 had instructed it to move. If the PFD 201 indicates to the charge pump 203 to move up on frequency then a voltage charge to sent to the loop filter to make an incremental increase in frequency.
• a multiplexer (MUX) 205 is positioned between the charge pump 203 and the loop filter 209.
• the MUX 205 performs at least two critical functions during the operation of the system and method of the present invention. First, the MUX 205 works to break the PLL 200 continuity during the coarse tune condition by disconnecting the charge pump 203 from the loop filter 209. Thus, the present invention is capable of operating in an "open loop" state which gives a tuning speed advantage over prior art techniques.
• the MUX 205 works to select a bias point that can be used as a reference for the VCO 211 free running frequency.
• the VCO 211 may represent one or more VCOs (VCO n ).
• the programmable voltage reference 207 is used to program the MUX 205 to adjust the free running frequency of the VCO 211 so that in a "closed loop" state, the final VCO control voltage input is near the voltage of the programmable voltage reference 207. This is an important feature of the present invention in that it helps to enhance the overall operational range of the VCO 211. The user can then select the optimal range of the VCO by programming the value in the programmable voltage source 207.
• the charge pump 203 is connected through-the MUX 205 to the loop filer 209 to resume closed loop PLL operation.
• the charge pulses applied to the loop filter 209 are then smoothed by the loop filter to eliminate noise and stability problems at the VCO 211.
• the smoothed voltage input is applied to the VCO 211 and it oscillates at some predetermined frequency output.
• the output of the VCO 211 is supplied to a divider 213 to divide down or lower the VCO output frequency.
• the divider may be either an integer or fractional divider.
• the VCO 211 to operate at some predetermined frequency other than that of the reference frequency (F ref ). This permits the lower VCO output frequency to be compared to the reference frequency by PFD 201. Since the function of the PFD 201 is to attempt to match these frequencies it generates both "UP-SLLP" and "DOWN-SLIP” pulses to an error accumulation in the monitor and control 215 in an attempt to match PFD 201 VCO input frequency (F 0 ) to the reference frequency (F ref ). When F o p erat i ng and F ref are more then 360 degrees i.e. 2 ⁇ offset in phase, the UP-SLIP and DOWN-SLIP pulses are processed the monitor and control 215. This is referred to as 2 ⁇ slip detection.
• the monitor and control 215 includes a timer (not shown), error accumulator (not shown), and controller (not shown).
• the monitor and control 215 provides a signal to the MUX 205 to change the PLL to an "open loop" state while the PLL is in coarse tune mode.
• the UP-SLIPs and DOWN-SLIPs are tracked by the error accumulator in the monitor and control 215.
• it is a novel aspect of the present invention for providing a coarse tuning port at the VCO 211 that allows the monitor and control 215 to coarsely alter the VCOs free running frequency.
• a wire bus of "m" bits may be used to control the free running frequency of one or more of the VCOs 211 by the coarse tuning method as taught by the present invention.
• the MUX 205 forces a voltage on the VCO 211 input by removing the charge pump 203 from the PLL and setting a desirable target bias for the VCO free running frequency.
• the implementation shown herein has the loop filter 209 driven by the same voltage reference that is driving the input to the VCO 211. This tends to minimize transients and settling time when the PLL 200 switches from a coarse tune mode to the fine tuning or normal close loop tracking mode.
• the output of the VCO 211 is compared to the reference frequency (F ref ) after any required frequency division.
• the UP and DOWN pulses from the PFD 201 that operate the charge pump 203 are ignored during coarse tune due to the MUX 205 which opens the PLL.
• the 2 ⁇ slip pulses can be used to increase or decrease an error accumulation to adjust the VCO 211 free running frequency close to a desired target frequency.
• the 2 ⁇ slip pulses occur at a rate approximately equal to: l/(F re f- F operat i n g)-
• F ref frequency of F 0 p era ting
• the slip pulses only occur on the UP-SLIP output of PFD 201.
• the pulses only occur on the DOWN-SLIP output of PFD 201.
• the direction of the required frequency adjustment is easily known and can be used to direct the tuning of the VCO 211.
• the monitor and control 215 may be implemented in several ways. As best seen in FIG. 3, the preferred embodiment uses a timer 302 to control the times upon which the error accumulator 303 will start and stop its counting sequence. Alternate methods include monitoring the time between 2 ⁇ slips and starting and stopping the timer based upon this time. In addition, the error accumulator 303 may be stopped by sensing a change in tuned frequency polarity.
• the system and tuning method of the present invention is very flexible in this regard and in some systems it may be desirable to track coarse tune updates while the PLL 200 is closed for monitoring purposes.
• FIG 3 also illustrates an example of the method for implementing the monitor and control 215 so as the coarse tune can be stopped after the VCO 211 is tuned within a specified and/or predetermined frequency range.
• the UP-SLIP and DOWN- SLIP pulses from PFD 201 work as inputs to an error accumulator 303 that processes the 2 ⁇ slip information.
• the error accumulator will perform a simple linear count, enforce a non-linear count or any custom tune sequence to "m" bits that alter the VCO 211 free running frequency.
• the UP-SLIP and DOWN-SLIP pulses from PFD 201 are also inputs to the OR gate 301.
• the OR gate 301 generates a signal output at the occurrence of any 2 ⁇ slip and triggers timer 302 to clear and restart the timing sequence. If the amount of time between 2 ⁇ slips is long enough for timer 302 to timeout, an output signal is sent to an input of the error accumulator 303 to hold the current tune condition being sent to VCO 211.
• FIG. 4 illustrates an alternative embodiment of the monitor and control 215 that can be implemented with the present invention.
• a coarse tune stop is used after the polarity of the tune frequency corrections first changes direction.
• An enable signal "en” is input to a logical inverter 406 that holds the digital flip-flop circuits 401 and 402 in a reset state. When tuning begins, the enable signal "en” changes state so that the reset condition on flip-flops 401 and 402 are no longer enforced.
• the UP-SLIP and DOWN-SLIP pulses from PFD 201 are input to an error accumulator 404 that processes the 2 ⁇ slip information.
• the error accumulator then performs a simple linear count, a non-linear count or any custom tune sequence to the "m" bits that alter the VCO 211 free running frequency.
• the UP-SLIP pulses from PFD 201 are also input to the digital flip- flop circuit 401.
• This flip-flop circuit 401 is connected in such a way that the UP-SLIP pulses pass an enabling signal through the flip-flop changing it from the reset state into a set state.
• the DOWN-SLIP pulses from PFD 201 work also an input to a second digital flip-flop circuit 402.
• This flip-flop circuit 402 is connected in such a way that the UP-SLIP pulses pass an enabling signal through the flip-flop changing it from the reset state into a set state.
• the output of flip-flop 401 is input to NAND gate 403 while the output of flip-flop 403 is input to a second input of NAND gate 403.
• both flip- flops 401 and 402 are in the set state the output of NAND gate 403 changes state.
• the output of NAND gate 403 is an input to AND gate 405 while AND gate 405 will pass the state of the output of NAND gate 403 to the output of AND gate 405 if the enable signal "en” on a second input to AND gate 405 is in an enabling state.
• the output of AND gate 405 is then sent to the error accumulator 404 to hold the current tune condition being sent to VCO 211.
• This same output signal from AND gate 405 is sent to MUX 205 as loop control to close the PLL loop to allow fine tuning to proceed under closed loop conditions.
• FIG. 5 is yet another embodiment of the monitor and control 215 that may be implemented to allow the coarse tune to be stopped after a fixed time interval.
• the UP- SLIP and DOWN SLIP pulses from PFD 201 are inputs to an error accumulator 501 that processes the 2 ⁇ slip information.
• the error accumulator then works to either perform a simple linear count, enforce a non-linear count or any custom tune sequence to the m bits that alter the VCO 211 free running frequency.
• An enable signal "en” is input to the tune time allocator 502 that establishes the amount of time allocated for tuning to occur.
• the tune time allocator output is sent to MUX 205 as loop control to open the PLL loop to allow the coarse tuning sequence to begin.
• the tune time allocator output is sent to MUX 205 as loop control to close the PLL loop to allow fine tuning to proceed under closed loop conditions.
• the system and method of the present invention offers a distinct advantage in that the 2 ⁇ slips occur at a rate proportional to the frequency difference that can be used to constrain the coarse tune any number of ways. This greatly enhances the ability of a PLL synthesizer to avoid the circuit and environment anomalies of the prior art to permit the VCO to be quickly tuned maintaining it within its predetermined operating range.

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• 2003
  • 2003-02-14 US US10/367,007 patent/US6774732B1/en not_active Expired - Lifetime
• 2004
  • 2004-02-04 CN CNB2004800040588A patent/CN100483947C/zh not_active Expired - Fee Related
  • 2004-02-04 WO PCT/US2004/003098 patent/WO2004075411A2/en not_active Ceased
  • 2004-02-04 JP JP2006503296A patent/JP2006518151A/ja active Pending
  • 2004-02-04 KR KR1020057014941A patent/KR101082724B1/ko not_active Expired - Fee Related
  • 2004-02-13 TW TW093103504A patent/TW200509537A/zh unknown

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