WO2018000530A1 - 锁相环路中压控振荡器的校准系统及方法 - Google Patents

锁相环路中压控振荡器的校准系统及方法 Download PDF

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Publication number
WO2018000530A1
WO2018000530A1 PCT/CN2016/094504 CN2016094504W WO2018000530A1 WO 2018000530 A1 WO2018000530 A1 WO 2018000530A1 CN 2016094504 W CN2016094504 W CN 2016094504W WO 2018000530 A1 WO2018000530 A1 WO 2018000530A1
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Prior art keywords
voltage
controlled oscillator
voltage controlled
phase
locked loop
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PCT/CN2016/094504
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English (en)
French (fr)
Inventor
汤勉芝
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上海晶曦微电子科技有限公司
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Publication of WO2018000530A1 publication Critical patent/WO2018000530A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • Embodiments of the present application relate to electronic circuit technologies, for example, to a calibration system and method for a voltage controlled oscillator in a phase locked loop.
  • phase-locked loops PLLs
  • VCOs voltage-controlled oscillators
  • Kvco tuning gain of the voltage controlled oscillator
  • Many circuit designers use multiple overlapping frequency tuning subbands (small Kvco) to cover the target frequency range.
  • the first related technique is to switch Vtune to a predefined value, such as Vdd/2, to cut off the voltage controlled oscillator at Vtune and use a counter as shown in FIG.
  • the frequencies Fref and Fvco/N are counted.
  • compare the count values of Fref and Fvco/N Based on the comparison, changes are made to the array of capacitors in the VCO.
  • this method shortens the calibration time after the phase-locked loop is stable, it is restricted by the Fref and Ncal frequency dividers.
  • the Fref frequency value is low, the counter must accumulate enough count values to ensure a certain calibration accuracy. This means that more calibrations are required during calibration and the allocation time for each calibration is extended.
  • the division value Ncal will often be changed for the sigma-delta modulator. This causes the counter to spend more time getting the average of the Ncal.
  • the second related technique is that, as shown in FIG. 2, an analog open loop calibration method is used to compare the frequencies Fref and Fvco/N.
  • the method first clocks Fref and Fvco/N to obtain a 50% duty cycle. Then use a time-to-voltage converter (TVC) to find the difference between Fref/2 and Fvco/N/2 on the rising/falling edge, and input the rising/falling edge signal to the charge pump, charge pump output
  • the charging circuit has a charging capacitor to obtain the charging value Vc.
  • Vref and Vc it can be known which of the two frequencies Fref and Fvco/N are faster or slower, and then logic circuits are used to control the capacitor array in the VCO.
  • the method needs to have two TVC output circuits and two large capacitors at the output of the circuit, which will occupy a large area in the integrated circuit; in addition, when the system adopts a fractional frequency division with ⁇ - ⁇ modulator In the frequency synthesizer, the division value N will often be changed for the sigma-delta modulator, resulting in system complexity and will take more time to obtain an average of N.
  • the present application provides a calibration system and method for a voltage controlled oscillator in a phase locked loop to solve the defect of long calibration time of the voltage controlled oscillator.
  • an embodiment of the present application provides a calibration system for a voltage controlled oscillator in a phase locked loop, including: a gain adjustment unit and a calibration detection unit, wherein the gain adjustment unit is connected to the input end of the voltage controlled oscillator, Directing the voltage controlled oscillator to output a voltage control signal of a first loop bandwidth before the phase tracked by the phase locked loop is stable; and a calibration detecting unit is coupled to the voltage controlled oscillator for collecting The voltage in the voltage controlled oscillator is calibrated based on a comparison result between the collected voltage and a preset detection voltage window, and the loop bandwidth of the voltage control signal is calibrated when determining the phase locked loop When the phase is stable, the gain adjustment unit is instructed to reduce the voltage control signal from the first loop bandwidth to the second loop bandwidth.
  • the embodiment of the present application further provides a calibration method of a voltage controlled oscillator in a phase locked loop, including: indicating voltage control in the phase locked loop before the phase tracked by the phase locked loop is stable An oscillator outputs a voltage control signal of a first loop bandwidth, and collects a voltage of the voltage controlled oscillator; and a loop of the voltage control signal based on a comparison result between the collected voltage and a preset detection voltage window The bandwidth is calibrated; and, when it is determined that the phase tracked by the phase locked loop is stable, the voltage control signal is reduced from the first loop bandwidth to the second loop bandwidth.
  • the present application speeds up the phase convergence speed through a large bandwidth (ie, the first loop bandwidth), and improves the phase locking speed of the phase locked loop.
  • the calibration detection is involved during the oscillation of the voltage controlled oscillator, and the phase locked loop converges to the phase.
  • the tracking is stable, it is determined that the calibration is completed, which effectively shortens the phase detection time limit of the phase locked loop.
  • FIG. 1 is a schematic structural view of a first calibration system in the related art
  • FIG. 2 is a schematic structural diagram of a second calibration system in the related art
  • FIG. 3 is a schematic structural diagram of a calibration system of a voltage controlled oscillator in a phase locked loop in the first embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of a calibration system of a voltage controlled oscillator in a phase locked loop in an alternative embodiment of the present application
  • FIG. 5 is a schematic diagram of a waveform when the acquisition voltage is higher than the upper limit of the detection voltage window in the first embodiment of the present application;
  • FIG. 6 is a schematic diagram of a waveform when the acquisition voltage is lower than the lower limit of the detection voltage window in the first embodiment of the present application;
  • FIG. 7 is a schematic diagram of a waveform when an acquisition voltage falls within a detection voltage window in Embodiment 1 of the present application;
  • FIG. 8 is a flowchart of a method for calibrating a voltage controlled oscillator in a phase locked loop in the second embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a calibration system of a voltage controlled oscillator in a phase-locked loop according to Embodiment 1 of the present application.
  • This embodiment is applicable to a voltage control signal of a voltage controlled oscillator 2 during convergence of a phase locked loop.
  • the adjustment is to calibrate the phase tracking condition of the phase locked loop, and the calibration system includes: a gain adjustment unit 11 and a calibration detection unit 12.
  • the gain control unit 11 is connected to the input end of the voltage controlled oscillator 2 for instructing the voltage controlled oscillator 2 to output a voltage control signal of the first loop bandwidth before the phase tracked by the phase locked loop is stabilized. .
  • the gain control unit 11 supplies current to the voltage controlled oscillator 2 with a larger gain after the voltage controlled oscillator 2 is powered up, so that the voltage control signal output by the voltage controlled oscillator 2 has a larger loop. Road bandwidth.
  • the gain control unit 11 reduces the loop bandwidth of the voltage controlled oscillator 2 from the first loop bandwidth to the second loop by reducing the gain of the supply current. bandwidth.
  • the switching of the control loop bandwidth between the first loop bandwidth and the second loop bandwidth by the gain adjustment unit 11 can be implemented in at least three manners.
  • the first alternative is that the gain adjustment unit 11 includes a charge pump regulation module 111.
  • the charge pump regulation module 111 is connected to the input end of the voltage controlled oscillator 2 for adjusting the voltage control signal output by the voltage controlled oscillator 2 by adjusting the input current of the voltage controlled oscillator 2
  • the loop bandwidth is the first loop bandwidth or the second loop bandwidth.
  • the charge pump regulation module 111 can be installed in a charge pump.
  • the charge pump regulation module 111 is a control device and logic circuit that adjusts the voltage in the charge pump.
  • the charge pump regulation module 111 adjusts the voltage to the first gear position, so that the current output by the charge pump is filtered by the low-pass filter and still has a large gain.
  • the voltage controlled oscillator 2 is based on the loop bandwidth of the voltage control signal output by the current as the first loop bandwidth.
  • the charge pump regulation module 111 receives the determination calibration command, the charge pump regulation module 111 adjusts the voltage from the first gear position to the second gear position, so that the current gain of the charge pump output to the voltage controlled oscillator 2 is small.
  • the loop bandwidth of the voltage control signal output by the voltage controlled oscillator 2 is the second loop bandwidth.
  • the gain adjustment unit 11 includes a low pass filter adjustment module 112.
  • the low pass filter control module 112 is connected to the input end of the voltage controlled oscillator 2 for adjusting the voltage controlled oscillator 2 by adjusting the load resistance value of the low pass filter in the phase locked loop.
  • the loop bandwidth of the output voltage control signal is the first loop bandwidth or the second loop bandwidth.
  • the low pass filter control module 112 can be installed in a circuit where the low pass filter is located.
  • the low pass filter control module 112 is a control device and logic circuit that adjusts the resistance in the low pass filter.
  • the low-pass filter control module 112 adjusts the resistance to the first gear position, so that the current gain of the low-pass filter control module 112 to the voltage-controlled oscillator 2 is large.
  • the loop bandwidth of the voltage controlled oscillator 2 corresponding to the output voltage control signal is the first loop bandwidth.
  • the low pass filter control module 112 When the low pass filter control module 112 receives the determined calibration command, the low pass filter control module 112 adjusts the resistance from the first gear to the second gear, so that the low pass filter outputs the current to the voltage controlled oscillator 2 The gain is small, and the loop bandwidth of the voltage control signal outputted by the voltage controlled oscillator 2 is the second loop bandwidth.
  • the gain adjustment unit 11 includes a charge pump regulation module 111 and a low-pass filter regulation module 112.
  • the gain adjustment unit 11 realizes that the loop bandwidth of the voltage control signal outputted by the voltage controlled oscillator 2 is the first loop bandwidth or the second loop bandwidth by simultaneously adjusting the two control modules.
  • the calibration detecting unit 12 is connected to the voltage controlled oscillator 2 for collecting the voltage of the voltage controlled oscillator 2, based on a comparison result between the collected voltage and a preset detection voltage window. Calibrating the loop bandwidth of the control signal, and when determining that the phase tracked by the phase-locked loop is stable, instructing the gain control unit 11 to reduce the output voltage control signal from the first loop bandwidth to the second loop bandwidth.
  • the calibration detecting unit 12 can be connected to the input terminal of the voltage controlled oscillator 2 in the voltage controlled oscillator 2 to collect the voltage of the input voltage controlled oscillator 2.
  • the calibration detecting unit 12 can also be connected to the output of the voltage controlled oscillator 2 to acquire the output voltage of the voltage control signal.
  • the calibration detecting unit 12 is pre-configured with a detection voltage window designed by using a capacitance characteristic. For example, select a suitable capacitor device, the first terminal is grounded, and the second terminal is connected to a preset voltage (such as Vdd).
  • Vdd a preset voltage
  • the calibration detecting unit 12 immediately starts collecting the voltage in the voltage controlled oscillator 2 in real time and compares the collected voltage with the detected voltage window.
  • the obtained comparison result falls within the detection voltage window, it is determined that the phase tracked by the phase-locked loop is stable (ie, the calibration is determined), and vice versa, determining that the phase-locked loop is unstable (ie, required) Continue to calibrate).
  • the tuning gain of the voltage controlled oscillator 2 is adjusted by adjusting the capacitance, resistance, etc. of the voltage controlled oscillator 2 in itself, and the tuning voltage is continuously detected until the calibration is completed.
  • the calibration detecting unit 12 When it is determined that the phase is stable, the calibration detecting unit 12 outputs a determination calibration instruction to the gain adjustment unit 11 so that the gain adjustment unit 11 adjusts the voltage of the charge pump and the resistance of the low-pass filter by the first The loop bandwidth is reduced to the second loop bandwidth.
  • each of the voltages collected in the preset period may be analyzed, and the tuning voltage may be selected therefrom, and then the tuning voltage and the detection voltage window may be selected. Compare.
  • the window width of the preset detection voltage window is smaller than the oscillation width of the collected electrical signal.
  • the calibration detecting unit 12 includes a tuning voltage determining module for determining a tuning voltage of the voltage control signal according to the oscillation frequency of the voltage controlled oscillator 2.
  • the phase margin of the voltage controlled oscillator 2 is preset in the tuning voltage determination module, and the access is The value of the resistor and the value of the capacitor in the voltage controlled oscillator 2.
  • the tuning voltage determination module obtains the oscillation frequency of the voltage control signal in advance, and acquires the tuning voltage (Vtune) of the voltage control signal according to the obtained oscillation frequency.
  • ⁇ is the damping factor
  • ⁇ is the phase margin
  • ⁇ is the resistance value
  • c is the capacitance value
  • ⁇ c is the oscillation frequency
  • ⁇ n is the oscillation period.
  • the calibration detecting unit 12 may collect a tuning voltage (Vtune) according to the oscillation frequency, and perform calibration according to a comparison result between the collected tuning voltage and the detection voltage window.
  • Vtune tuning voltage
  • the calibration detection unit 12 includes three resistors 121 for identifying a voltage threshold interval of the detection voltage window, two comparators 122, and an output of the first comparator 1201 and A logic device 123 connected to the output of the comparator 1202, and a capacitor array 124 controlled by the logic device 123 and connected to the voltage controlled oscillator 2.
  • the first input end of the first comparator 1201 and the first input end of the second comparator 1202 are respectively connected to two ends of the second resistor 1212, and the second input end of the first comparator 1201 and the second comparator The two inputs collectively receive the collected voltage.
  • the logic device 123 adjusts the capacitance value in the capacitor array 124 to be connected to the voltage controlled oscillator 2 according to the comparison result output by the two comparators 122.
  • the three resistors 121 include a first resistor 1211, a second resistor 1212, and a third resistor 1213 connected in series.
  • each comparator 122 can receive a tuning voltage that is acquired by the tuning voltage determination module.
  • the logic device 123 adjusts the number of capacitive devices connected to the voltage controlled oscillator 2 in the capacitor array 124 when determining that the current tuning voltage is outside the detection voltage window (ie, adjusting the voltage controlled oscillation in the capacitor array 124)
  • the capacitance value in the device 2 when it is determined that the current tuning voltage is within the detection voltage window, it is determined that the calibration is completed.
  • each of the comparators 122 can receive the voltage control signal provided by the voltage controlled oscillator 2 in real time.
  • the logic device 123 detects a comparison result between the tuning voltage and the detection voltage window output by each comparator 122 according to a period corresponding to the oscillation frequency determined by the tuning voltage determination module, and then determines whether the comparison result is used according to the comparison result. The calibration is complete.
  • the logic device 123 increases the voltage-controlled oscillation by gradually adjusting the capacitance value of the voltage-controlled oscillator 2 in the capacitor array 124 when detecting that the collected voltage is not within the detection voltage window (ie, determining that calibration is still required).
  • each capacitor in the capacitor array 124 has a parallel trend, and the parallel capacitor devices are equipped with control switches. Initially, the capacitor array 124 can be fully connected/not connected to the capacitive device to maximize/minimize the gain of the voltage controlled oscillator 2, and then gradually adjust from the maximum/minimum to the appropriate gain for calibration purposes.
  • the logic device 123 reduces the capacitance value of the voltage controlled oscillator 2 in the capacitor array 124 according to a preset step size. And again detecting the tuning voltage of the next cycle, based on the capacitance value of the previous cycle, reducing the capacitance value again according to the step size, thus gradually increasing the tuning gain of the voltage controlled oscillator 2 until the detected tuning voltage falls into the voltage Inside the window.
  • the logic device 123 increases the capacitance value of the voltage controlled oscillator 2 in the capacitor array 124 according to a preset step size. And again detecting the tuning voltage of the next cycle, based on the capacitance value of the previous cycle, increasing the capacitance value according to the step size, thus gradually increasing the tuning gain of the voltage controlled oscillator 2 until the detected tuning voltage falls into the voltage Inside the window.
  • the logic device 123 instructs the capacitor array 124 to increase/decrease the number of capacitive components that are connected based on the number of currently accessed capacitive devices in a stepwise adjustment manner of the binary method.
  • the capacitor array 124 is connected to a capacitive device that is half the capacitance.
  • the logic device 123 uses a binary method to connect one half of the parallel capacitance of the capacitor array 124 that is not currently connected to the voltage controlled oscillator 2 to the voltage controlled oscillator 2.
  • the logic device 123 When it is again detected that the tuning voltage is still above the upper limit of the detection voltage window, the logic device 123 then connects one of the parallel capacitors of the capacitor array 124 that are not currently connected to the voltage controlled oscillator 2 to the voltage controlled oscillator 2.
  • the gain is adjusted step by step such that the detected tuning voltage falls within the detection voltage window.
  • the logic device 123 disconnects half of the shunt capacitance of the current capacitor array 124 into which the voltage controlled oscillator 2 is connected.
  • the gain is adjusted step by step such that the detected tuning voltage falls within the detection voltage window.
  • the logic device 123 detects that the collected voltage is lower than the lower limit of the detection voltage window, the parallel capacitance of the voltage controlled oscillator 2 is connected from the capacitor array 124, and the voltage-controlled oscillation is first reduced. Half of the capacitor 2 is connected in parallel. When it is detected that the tuning voltage is lower than the lower limit of the detection voltage window, the logic device 123 reduces the access amount of the capacitor again by half the previous connection of the parallel capacitor to reduce the gain of the voltage controlled oscillator 2 until the detection The voltage collected is higher than the upper limit of the detection voltage window, or the collected voltage falls within the detection voltage window.
  • the logic device 123 connects one half of the unconnected parallel capacitive device to the voltage controlled oscillation on the basis of the last connected parallel capacitance. 2 to increase the gain until it is detected that the collected voltage falls within the detection voltage window.
  • the logic device 123 may determine that the calibration is completed, and output a determination calibration instruction to the gain adjustment unit 11 so that the gain adjustment unit 11 controls the The voltage controlled oscillator 2 outputs a voltage control signal of a second loop bandwidth.
  • the logic device 123 detects that the collected voltage (such as the tuning voltage) falls within the detection voltage window, it is verified whether the subsequently collected voltage still falls within the detection voltage window; Entering the detection voltage window, determining that the phase tracked by the voltage controlled oscillator 2 is stable, and instructing the gain adjustment unit 11 to reduce the output voltage control signal from the first loop bandwidth to the second loop Bandwidth; when not falling within the detection voltage window, continue to adjust the capacitance value of the capacitor array 124 to the voltage controlled oscillator 2 according to one of the above various manners.
  • the logic device 123 detects that the collected voltage (such as the tuning voltage) falls within the detection voltage window, it is verified whether the subsequently collected voltage still falls within the detection voltage window; Entering the detection voltage window, determining that the phase tracked by the voltage controlled oscillator 2 is stable, and instructing the gain adjustment unit 11 to reduce the output voltage control signal from the first loop bandwidth to the second loop Bandwidth; when not falling within the detection voltage window, continue to adjust the capacitance value of the capacitor array 124
  • the voltage control oscillator outputs a voltage control signal with a large bandwidth (ie, the first loop bandwidth) to speed up the phase convergence speed, thereby improving the phase locking speed of the phase locked loop; and simultaneously, intervening during the phase locked loop oscillation.
  • Calibration detection when the phase-locked loop converges to phase tracking stability, determines the calibration is completed, effectively shortening the phase detection time limit of the phase-locked loop.
  • the charge pump and the low-pass filter to change the loop bandwidth of the voltage control signal, the loop bandwidth can be adjusted without changing the circuit structure of the phase-locked loop, thereby effectively reducing the phase lock.
  • the complexity of the circuit structure of the loop is a large bandwidth (ie, the first loop bandwidth) to speed up the phase convergence speed, thereby improving the phase locking speed of the phase locked loop; and simultaneously, intervening during the phase locked loop oscillation.
  • the stability of the acquisition voltage can be effectively improved, and the interference of the signal amplitude on the comparison result can be avoided.
  • the gradual adjustment of the capacitor array by the dichotomy method can accurately and efficiently determine the calibration result, reduce the number of repeated adjustments, and shorten the calibration time limit.
  • the second embodiment provides a calibration method for a voltage controlled oscillator in a phase locked loop.
  • the calibration method can be performed based on a calibration system designed in accordance with any of the alternative embodiments described above. It can also be performed by other calibration systems as follows.
  • Step S110 Before the phase tracked by the phase locked loop is stabilized, instruct the voltage controlled oscillator to output a voltage control signal of the first loop bandwidth, and collect the voltage of the voltage controlled oscillator.
  • the current is supplied to the voltage controlled oscillator with a larger gain, so that the voltage control signal output by the voltage controlled oscillator has a larger loop bandwidth.
  • the loop bandwidth of the voltage controlled oscillator is reduced from the first loop bandwidth to the second loop bandwidth by reducing the gain of the supply current.
  • switching of the loop bandwidth between the first loop bandwidth and the second loop bandwidth may be implemented in at least three manners.
  • An alternative is: adjusting a loop bandwidth of the voltage control signal output by the voltage controlled oscillator to a first loop bandwidth or a second loop bandwidth by adjusting an input current of the voltage controlled oscillator .
  • the charge pump regulation module is installed in a charge pump.
  • the charge pump regulation module is a control device and logic circuit that adjusts the voltage in the charge pump.
  • the charge pump regulation module adjusts the voltage to the first gear position, so that the current output by the charge pump is filtered by the low-pass filter and still has a large gain.
  • the voltage controlled oscillator is based on a loop bandwidth of a voltage control signal output by the current as a first loop bandwidth.
  • the charge pump regulation module When the charge pump regulation module receives the determined calibration command, the charge pump regulation module adjusts the voltage from the first gear to the second gear such that the current gain of the charge pump output to the voltage controlled oscillator is small, the pressure The loop bandwidth of the voltage control signal output by the controlled oscillator is reduced to the second loop bandwidth.
  • the second alternative is to adjust the loop bandwidth of the voltage control signal output by the voltage controlled oscillator to the first loop by adjusting the load resistance value of the low pass filter in the voltage controlled oscillator. Bandwidth or second loop bandwidth.
  • a low pass filter control module is installed in the circuit where the low pass filter is located.
  • the low pass filter control module is a control device and a logic circuit that adjust the resistance in the low pass filter.
  • the low-pass filter control module adjusts the resistance to the first gear position, so that the current gain of the low-pass filter control module output to the voltage-controlled oscillator is large.
  • the loop bandwidth of the voltage controlled oscillator corresponding to the output voltage control signal is the first loop bandwidth.
  • the low-pass filter control module receives the determined calibration command, the low-pass filter control module adjusts the resistance from the first gear to the second gear, so that the current gain of the low-pass filter output to the voltage-controlled oscillator is small.
  • the loop bandwidth of the voltage control signal output by the voltage controlled oscillator Drop to the second loop bandwidth.
  • a third alternative is to install the above-described charge pump control module and low-pass filter control module. By adjusting the two control modules at the same time, the loop bandwidth of the voltage control signal outputted by the voltage controlled oscillator is the first loop bandwidth or the second loop bandwidth.
  • Step S120 Calibrate a loop bandwidth of the voltage control signal based on a comparison result between the collected voltage and a preset detection voltage window.
  • the collected voltage may be the voltage of the input voltage controlled oscillator or the voltage of the voltage control signal.
  • a detection voltage window designed using capacitive characteristics is pre-configured. For example, select a suitable capacitor device, the first terminal is grounded, and the second terminal is connected to a preset voltage (such as Vdd).
  • Vdd a preset voltage
  • the voltage controlled oscillator is powered up, the voltage in the voltage controlled oscillator is immediately acquired in real time, and the collected voltage is compared with the detected voltage window.
  • the obtained comparison results all fall within the detection voltage window, it is determined that the phase tracked by the voltage controlled oscillator is stable (ie, the calibration is determined), and when the obtained comparison result is outside the detection voltage window, It is determined that the voltage controlled oscillator is unstable (ie, calibration needs to be continued).
  • the tuning gain of the voltage controlled oscillator is adjusted by adjusting the capacitance, resistance, etc. of the voltage controlled oscillator in itself, and the tuning voltage is continuously detected until the calibration is completed.
  • each of the voltages collected in the preset period may be analyzed, and the tuning voltage may be selected therefrom, and then the tuning voltage and the detection voltage window may be selected. Compare.
  • the window width of the preset detection voltage window is smaller than the oscillation width of the collected electrical signal.
  • An alternative is to determine the tuning voltage of the voltage control signal according to the oscillation frequency of the voltage controlled oscillator.
  • the phase margin of the voltage controlled oscillator is preset, and the resistance value and the capacitance value in the voltage controlled oscillator are connected. According to the above parameters, the oscillation frequency of the voltage control signal is obtained in advance, and the tuning voltage of the voltage control signal is acquired according to the obtained oscillation frequency.
  • the calibration system may acquire a tuning voltage according to the oscillation frequency and perform calibration according to a comparison result between the collected tuning voltage and the detection voltage window.
  • the calibration system includes: three resistors identifying a voltage threshold interval of the detection voltage window, two comparators, an output of the first comparator, and an output of the second comparator Connected logic devices, and an array of capacitors controlled by the logic device and connected to the voltage controlled oscillator.
  • the first input end of the first comparator and the first input end of the second comparator are respectively connected to two ends of the second resistor, and the second input end of the first comparator and the second input end of the second comparator are common Receive the collected voltage.
  • the logic device adjusts a capacitance value in the voltage controlled oscillator connected to the capacitor array according to a comparison result output by the two comparators.
  • each of the comparators can receive a tuning voltage according to the acquisition.
  • the logic device adjusts the number of capacitive devices connected to the voltage controlled oscillator in the capacitor array when determining that the current tuning voltage is outside the detection voltage window (ie, adjusting the capacitance in the capacitor array to be connected to the voltage controlled oscillator) Value), when it is determined that the tuning voltage falls within the detection voltage window, it is determined that the calibration is completed.
  • each of the comparators can receive the voltage control signal provided by the voltage controlled oscillator in real time.
  • the logic device detects a comparison result between the tuning voltage and the detection voltage window outputted by each comparator according to the determined oscillation frequency, and then determines whether the calibration is completed according to the comparison result.
  • the logic device When it is detected that the collected voltage is not within the detection voltage window (ie, it is determined that calibration is still required), the logic device increases the output of the voltage controlled oscillator by gradually adjusting the capacitance value of the voltage controlled oscillator in the capacitor array. Tuning gain of the voltage control signal.
  • each capacitor in the capacitor array has a parallel trend, and the parallel capacitor devices are equipped with control switches.
  • the capacitor array can be fully connected/not connected to the capacitive device so that the gain of the voltage controlled oscillator is maximized/minimized, and then adjusted from the maximum/minimum to the appropriate gain for calibration purposes.
  • the logic device When the detected tuning voltage is higher than the upper limit of the detection voltage window, the logic device reduces the capacitance value of the voltage controlled oscillator in the capacitor array according to a preset step size, and detects the tuning voltage of the next period again. Based on the capacitance value of one cycle, the capacitance value is again reduced according to the step size, so that the tuning gain of the voltage controlled oscillator is gradually increased until the detected tuning voltage falls within the voltage window.
  • the logic device When the detected tuning voltage is lower than the lower limit of the detection voltage window, the logic device is preset The step size increases the capacitance value of the voltage controlled oscillator in the capacitor array, and detects the tuning voltage of the next cycle again. Based on the capacitance value of the previous cycle, the capacitance value is increased again according to the step size, so that the voltage control is gradually increased. The tuning gain of the oscillator until the detected tuning voltage falls within the voltage window.
  • the logic device instructs the capacitor array to increase/decrease the number of capacitive components that are connected based on the number of currently connected capacitive devices according to a stepwise adjustment of the binary method.
  • the capacitor array is connected to a capacitive device that is half the capacitance.
  • the logic device uses a dichotomy method to connect one half of the parallel capacitors of the capacitor array that are not currently connected to the voltage controlled oscillator to the voltage controlled oscillator.
  • the logic device When it is again detected that the tuning voltage is still above the upper limit of the sense voltage window, the logic device then connects one half of the parallel capacitors of the capacitor array that are not currently connected to the voltage controlled oscillator to the voltage controlled oscillator.
  • the gain is adjusted step by step such that the detected tuning voltage falls within the detection voltage window.
  • the logic device When again detecting that the tuning voltage is below the lower limit of the sense voltage window, the logic device disconnects half of the shunt capacitance of the current capacitor array into which the voltage controlled oscillator is connected.
  • the gain is adjusted step by step such that the detected tuning voltage falls within the detection voltage window.
  • the logic device detects that the collected voltage is lower than the lower limit of the detection voltage window, starting from the parallel capacitance of the voltage controlled oscillator in the capacitor array, first reducing half of the voltage controlled oscillator Parallel capacitors.
  • the logic device reduces the access amount of the capacitor again by the last time the parallel capacitor is connected, so as to reduce the gain of the voltage controlled oscillator until the detected The acquired voltage is higher than the upper limit of the detection voltage window, or the collected voltage falls within the detection voltage window.
  • the logic device connects one half of the unconnected parallel capacitive device to the voltage controlled oscillator on the basis of the last connected parallel capacitor to improve The gain is until it is detected that the collected voltage falls within the detection voltage window.
  • step S130 is performed.
  • Step S130 When it is determined that the phase tracked by the voltage controlled oscillator is stable, the voltage control signal is reduced from the first loop bandwidth to the second loop bandwidth.
  • the logic device may determine that the calibration is completed, and output a determination calibration instruction to the gain adjustment unit, so that the gain adjustment unit controls the voltage controlled oscillator output.
  • the voltage control signal of the second loop bandwidth may be determined that the calibration is completed, and output a determination calibration instruction to the gain adjustment unit, so that the gain adjustment unit controls the voltage controlled oscillator output.
  • An optional case is that, when detecting that the collected voltage (such as the tuning voltage) falls within the detection voltage window, the logic device verifies whether the subsequently collected voltage still falls within the detection voltage window; Determining, in the detection voltage window, that the phase tracked by the voltage controlled oscillator is stable, and instructing the gain adjustment unit to reduce the output voltage control signal from the first loop bandwidth to the second loop bandwidth; If it does not fall within the detection voltage window, continue to adjust the capacitance value of the capacitor array to the voltage controlled oscillator according to one of the various manners described in step S120.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

一种锁相环路中压控振荡器的校准系统及方法。其中，所述校准系统包括：与压控振荡器输入端相连的增益调控单元，用于在所述锁相环路所跟踪的相位稳定之前，指示所述压控振荡器输出第一环路带宽的压控信号；与所述压控振荡器相连的校准检测单元，用于采集所述压控振荡器中的电压，基于对所采集的电压与预设的检测电压窗的比较结果，对所述压控信号的环路带宽进行校准，当确定所述压控振荡器所跟踪的相位稳定时，指示所述增益调控单元将所述压控信号由第一环路带宽降至第二环路带宽。

Description

锁相环路中压控振荡器的校准系统及方法 技术领域
本申请实施例涉及电子电路技术，例如涉及一种锁相环路中压控振荡器的校准系统及方法。
背景技术
随着通信系统工作频率范围的越来越宽，并且越来越多的相关技术采用了低工作电压的锁相环(PLL)及压控振荡器(VCO)。为了适应锁相环的相位跟踪，压控振荡器(VCO)的调谐增益(Kvco)就必须得到相应的增大。很多电路设计者采用多个重叠的频率调谐子频带(小Kvco)来覆盖目标频率范围。
当这种拓扑在覆盖较宽的频率调谐范围时，可获得小的VCO的调谐增益(Kvco)，但这需要一种VCO校准方法来选择覆盖目标频率范围的频率调谐子频带。由于校准所花费的时间包括在锁相环的固有锁定时间里，或受到系统(特别是采用跳频扩频技术的系统)定义制约的锁定时间里，故实现一种快速校准方法来减少在调谐过程中的时间开销是十分重要的。
为了缩短校准所花费的时间，第一种相关技术为，如图1所示，将Vtune切换至一个预定义的值，如Vdd/2，来切断在Vtune处的压控振荡器，并采用计数器对频率Fref和Fvco/N进行计数。然后比较Fref和Fvco/N的计数值。根据比较结果，对VCO中的电容阵列做出变更。该方法虽然缩短了在锁相环路稳定后的校准时间，但受到Fref和Ncal分频器的制约。当Fref频率值较低时，计数器必须累计足够多的计数值以确保一定的校准精度。这意味着校准期间需要更多的校准次数，同时延长了每次校准的分配时间。对于Ncal分频器来说，当系统采用的是一个小数分频的、带∑-Δ调制器的频率合成器时，分频值Ncal将经常为∑-Δ调制器所改变。这导致计数器将花费更多的时间来获取Ncal的平均值。
第二种相关技术为，如图2所示，采用模拟方式的开环校准方法，以对频率Fref和Fvco/N进行比较。该方法首先对Fref和Fvco/N进行时钟分割来获取50％的占空比。然后采用一个时间至电压的转换器(TVC)来找出Fref/2和Fvco/N/2在上升/下降沿上的区别，并将该上升/下降沿信号输入到电荷泵上，电荷泵输出 端带有一个充电电容，可得到充电值Vc。最后，在对Vref和Vc作出比较后，可以获知Fref和Fvco/N这两个频率哪个为更快或更慢，再用逻辑电路来控制VCO中的电容阵列。该方法在电路输出端需要具备两个TVC输出电路和两个大电容，这将占用集成电路中的一大片面积；另外，当系统采用的是一个小数分频的、带∑-Δ调制器的频率合成器时，分频值N将经常为∑-Δ调制器所改变，导致了系统的复杂性并将花费更多的时间来获取N的平均值。
因此，上述两个方案都在有效缩短校准时间上有缺陷，需要对相关技术进行改进。
发明内容
本申请提供一种锁相环路中压控振荡器的校准系统及方法，以解决压控振荡器的校准时间长的缺陷。
第一方面，本申请实施例提供了一种锁相环路中压控振荡器的校准系统，包括：增益调控单元和校准检测单元，其中，增益调控单元与压控振荡器输入端相连，用于在所述锁相环路所跟踪的相位稳定之前，指示所述压控振荡器输出第一环路带宽的压控信号；以及，校准检测单元与所述压控振荡器相连，用于采集所述压控振荡器中的电压，基于对所采集的电压与预设的检测电压窗的比较结果，对所述压控信号的环路带宽进行校准，当确定所述锁相环路所跟踪的相位稳定时，指示所述增益调控单元将所述压控信号由第一环路带宽降至第二环路带宽。
第二方面，本申请实施例还提供了一种锁相环路中压控振荡器的校准方法，包括：在锁相环路所跟踪的相位稳定之前，指示所述锁相环路中压控振荡器输出第一环路带宽的压控信号，并采集所述压控振荡器的电压；基于对所采集的电压与预设的检测电压窗的比较结果，对所述压控信号的环路带宽进行校准；以及，当确定所述锁相环路所跟踪的相位稳定时，将所述压控信号由第一环路带宽降至第二环路带宽。
本申请通过大带宽(即第一环路带宽)来加快相位收敛速度，提高了锁相环路相位锁定速度；同时，在压控振荡器振荡期间介入校准检测，在锁相环路收敛到相位跟踪稳定时，确定校准完毕，有效缩短了锁相环路的相位检测时限。
附图说明
图1为相关技术中的第一种校准系统的结构示意图；
图2为相关技术中的第二种校准系统的结构示意图
图3是本申请实施例一中的锁相环路中压控振荡器的校准系统的结构示意图；
图4是本申请实施例一中的一种可选方案中的锁相环路中压控振荡器的校准系统的结构示意图；
图5是本申请实施例一中当采集电压高于检测电压窗上限的波形示意图；
图6是本申请实施例一中当采集电压低于检测电压窗下限的波形示意图；
图7是本申请实施例一中当采集电压落入检测电压窗内的波形示意图；
图8是本申请实施例二中的锁相环路中压控振荡器的校准方法的流程图。
具体实施方式
下面结合附图和实施例对本申请作详细说明。可以理解的是，此处所描述的实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
实施例一
图3为本申请实施例一提供的锁相环路中压控振荡器的校准系统的结构示意图，本实施例可适用于在锁相环路收敛期间通过对压控振荡器2的压控信号的调整，来校准锁相环路的相位跟踪情况，该校准系统包括：增益调控单元11和校准检测单元12。
所述增益调控单元11与压控振荡器2输入端相连，用于在所述锁相环路所跟踪的相位稳定之前，指示所述压控振荡器2输出第一环路带宽的压控信号。
可选的，所述增益调控单元11在压控振荡器2上电后以较大的增益向压控振荡器2提供电流，使得压控振荡器2所输出的压控信号具有较大的环路带宽。当 锁相环路经校准确定相位跟踪稳定后，所述增益调控单元11再通过降低供电电流的增益的方式，使压控振荡器2的环路带宽从第一环路带宽降至第二环路带宽。
本实施例可采用至少三种方式来实现增益调控单元11调控环路带宽在第一环路带宽和第二环路带宽之间的切换。
第一种可选方案为：所述增益调控单元11包括：电荷泵调控模块111。
所述电荷泵调控模块111与所述压控振荡器2输入端相连，用于通过调节所述压控振荡器2的输入电流的方式，调整所述压控振荡器2所输出的压控信号的环路带宽为第一环路带宽或第二环路带宽。
可选的，所述电荷泵调控模块111可安装在电荷泵中。例如，所述电荷泵调控模块111为调整电荷泵中电压的控制器件和逻辑电路。当电荷泵上电工作时，所述电荷泵调控模块111将电压调在第一档位，使得电荷泵所输出的电流经低通滤波器滤波后，仍具有增益较大。所述压控振荡器2基于该电流所输出的压控信号的环路带宽为第一环路带宽。当电荷泵调控模块111接收到确定校准指令时，所述电荷泵调控模块111将电压从第一档位调至第二档位，使得电荷泵输出至压控振荡器2的电流增益较小，所述压控振荡器2所输出的压控信号的环路带宽为第二环路带宽。
第二种可选方案为，所述增益调控单元11包括：低通滤波调控模块112。
所述低通滤波调控模块112与所述压控振荡器2输入端相连，用于通过调节所述锁相环路中低通滤波器的负载电阻值的方式，调整所述压控振荡器2所输出的压控信号的环路带宽为第一环路带宽或第二环路带宽。
可选的，所述低通滤波调控模块112可安装在低通滤波器所在电路中。例如，所述低通滤波调控模块112为调整低通滤波器中电阻的控制器件和逻辑电路。当低通滤波器上电工作时，所述低通滤波调控模块112将电阻调在第一档位，使得低通滤波调控模块112输出至压控振荡器2的电流增益较大。所述压控振荡器2对应输出的压控信号的环路带宽为第一环路带宽。当低通滤波调控模块112接收到确定校准指令时，所述低通滤波调控模块112将电阻从第一档位调至第二档位，使得低通滤波器输出至压控振荡器2的电流增益较小，所述压控振荡器2所输出的压控信号的环路带宽为第二环路带宽。
第三种可选方案为，如图4所示，所述增益调控单元11包括电荷泵调控模块111和低通滤波调控模块112。所述增益调控单元11通过同时调整该两个调控模块实现令压控振荡器2所输出的压控信号的环路带宽为第一环路带宽或第二环路带宽。
所述校准检测单元12与所述压控振荡器2相连，用于采集所述压控振荡器2的电压，基于对所采集的电压与预设的检测电压窗的比较结果，对所述压控信号的环路带宽进行校准，当确定所述锁相环路所跟踪的相位稳定时，指示所述增益调控单元11将所输出的压控信号由第一环路带宽降至第二环路带宽。
在此，所述校准检测单元12可连接压控振荡器2中压控振荡器2的输入端，以采集输入压控振荡器2的电压。所述校准检测单元12也可连接压控振荡器2的输出端，以采集压控信号的输出电压。
可选的，所述校准检测单元12预设有利用电容特性而设计的检测电压窗。例如，选取合适的电容器件，第一端接地，第二端接预设的电压(如Vdd)。在压控振荡器2上电时，所述校准检测单元12即刻开始实时采集压控振荡器2中的电压，并将所采集的电压与检测电压窗进行比较。当所得到的比较结果均落入所述检测电压窗内，则确定所述锁相环路所跟踪的相位稳定(即确定校准完毕)，反之，则确定所述锁相环路不稳定(即需要继续校准)。
当确定需要继续校准时，通过调整自身中接入压控振荡器2的电容、电阻等来调整压控振荡器2的调谐增益，并继续检测调谐电压，直至确定校准完毕。
当确定相位稳定时，所述校准检测单元12向增益调控单元11输出确定校准指令，以便增益调控单元11通过调节电荷泵的电压和低通滤波器的电阻，将所述压控信号由第一环路带宽降至第二环路带宽。
需要说明的是，本领域技术人员并非一定采用上述采集方式，为了提高校准精度，可通过对预设周期内所采集的每个电压进行分析，从中选取调谐电压，再将调谐电压与检测电压窗进行比较。
为了确保校准精度，所预设的检测电压窗的窗宽小于所采集电信号的震荡幅宽。第一种可选方案为，所述校准检测单元12包括：调谐电压确定模块，用于按照所述压控振荡器2的振荡频率，确定压控信号的调谐电压。
可选的，所述调谐电压确定模块中预设有压控振荡器2的相位裕度、及接入 压控振荡器2中的电阻值和电容值。根据上述参数，所述调谐电压确定模块预先得到压控信号的振荡频率，并按照所得到的振荡频率来采集压控信号的调谐电压(Vtune)。
例如，所述调谐电压确定模块利用公式：
Figure PCTCN2016094504-appb-000001
和ωc＝2□ζ□ωn来计算振荡频率。其中，ζ为阻尼因子、φ为相位裕度、ω为电阻值、c为电容值、ωc为振荡频率、ωn为振荡周期。
所述校准检测单元12可根据所述振荡频率来采集调谐电压(Vtune)，并根据所采集的调谐电压与检测电压窗的比较结果进行校准。
在第二种可选方案中，所述校准检测单元12包括：用于标识检测电压窗的电压门限区间的三个电阻121、两个比较器122、与第一比较器1201的输出端和第二比较器1202的输出端连接的逻辑器件123、以及受所述逻辑器件123控制且连接所述压控振荡器2的电容阵列124。
其中，第一比较器1201的第一输入端和第二比较器1202的第一输入端分别连接第二电阻1212的两端，第一比较器1201的第二输入端和第二比较器的第二输入端共同接收所采集的电压。
所述逻辑器件123根据两比较器122所输出的比较结果调整所述电容阵列124中接入压控振荡器2中的电容值。
其中，三个电阻121包括：第一电阻1211、第二电阻1212和第三电阻1213串联而成。
在此，每个比较器122可接收根据所述调谐电压确定模块所采集的调谐电压。所述逻辑器件123当确定当前的调谐电压位于检测电压窗之外，则调整电容阵列124中接入压控振荡器2的电容器件的数量(即调整所述电容阵列124中接入压控振荡器2中的电容值)，当确定当前的调谐电压位于检测电压窗之内，则确定校准完毕。
或者，每个所述比较器122可实时接收压控振荡器2所提供的压控信号。所述逻辑器件123按照所述调谐电压确定模块所确定的振荡频率所对应的周期，检测每个比较器122输出的关于调谐电压与检测电压窗之间的比较结果，再按照比较结果来确定是否校准完毕。
所述逻辑器件123当检测到所采集的电压不在检测电压窗内(即确定仍需校准)时，通过逐步调整电容阵列124中接入压控振荡器2的电容值的方式，增加压控振荡器2输出的压控信号的调谐增益。
可选的，所述电容阵列124中的每个电容之间呈并联趋势，并联的电容器件配有控制开关。初始时所述电容阵列124可以全部接入/不接入电容器件，以使得压控振荡器2的增益最大/最小，再由最大/最小逐步调整到合适的增益，以达到校准目的。
如图5所示，当所检测的调谐电压高于检测电压窗的上限(Vref1)时，所述逻辑器件123按照预设的步长减少电容阵列124中接入压控振荡器2的电容值，并再次检测下一周期的调谐电压，在上一周期的电容值的基础上，按照步长再次减少电容值，如此逐步增加压控振荡器2的调谐增益，直到所检测的调谐电压落入电压窗内。
如图6所示，当所检测的调谐电压低于检测电压窗的下限(Vref2)时，所述逻辑器件123按照预设的步长增加电容阵列124中接入压控振荡器2的电容值，并再次检测下一周期的调谐电压，在上一周期的电容值的基础上，按照步长再次增加电容值，如此逐步增加压控振荡器2的调谐增益，直到所检测的调谐电压落入电压窗内。
在一种可选方式中，所述逻辑器件123按照二分法的逐步调整方式，指示电容阵列124在当前接入电容器件数量的基础上增加/减少所接入的电容器件数量。
可选的，为了快速调整增益，所述电容阵列124接入电容量程一半的电容器件。当所检测的调谐电压高于检测电压窗的上限时，所述逻辑器件123采用二分法将电容阵列124中当前未接入压控振荡器2的并联电容中的一半接入压控振荡器2。
当再次检测调谐电压仍高于检测电压窗的上限时，所述逻辑器件123再将电容阵列124中当前未接入压控振荡器2的并联电容中的一半接入压控振荡器2。如此逐步调整增益，使得所检测的调谐电压落入检测电压窗。
当再次检测调谐电压低于检测电压窗的下限时，所述逻辑器件123断开当前电容阵列124中已接入压控振荡器2的并联电容中的一半。如此逐步调整增益，使得所检测的调谐电压落入检测电压窗。
或者，当所述逻辑器件123当检测到所采集的电压低于检测电压窗的下限时，从电容阵列124中接入压控振荡器2的并联电容开始，先减少其中已接入压控振荡器2的一半并联电容。当再次检测调谐电压低于检测电压窗的下限时，所述逻辑器件123在上次已接入并联电容的基础上再次减少一半电容的接入量，以降低压控振荡器2的增益，直至检测到所采集的电压高于检测电压窗的上限、或者所采集的电压落入检测电压窗。
继续地，当再次检测调谐电压高于检测电压窗的上限，则所述逻辑器件123在上次已接入并联电容的基础上，将未接入的并联电容器件中的一半接入压控振荡器2，以提高所述增益，直至检测到所采集的电压落入检测电压窗。
如图7所示，当所检测的调谐电压落入检测电压窗内时，所述逻辑器件123可确定校准完毕，并向所述增益调控单元11输出确定校准指令，以便增益调控单元11控制所述压控振荡器2输出第二环路带宽的压控信号。
一种可选情况是，所述逻辑器件123在检测到所采集的电压(如调谐电压)落入检测电压窗内时，验证后续采集的电压是否仍落入所述检测电压窗内；当落入所述检测电压窗内，则确定所述压控振荡器2所跟踪的相位稳定，并指示所述增益调控单元11将所输出的压控信号由第一环路带宽降至第二环路带宽；当未落入所述检测电压窗内，则按照上述各种方式之一继续调整电容阵列124接入压控振荡器2的电容值。
当确定校准完毕时，也是锁相环路的相位跟踪收敛的时间。
本实施例通过令压控振荡器输出大带宽(即第一环路带宽)的压控信号来加快相位收敛速度，提高了锁相环路相位锁定速度；同时，在锁相环路振荡期间介入校准检测，在锁相环路收敛到相位跟踪稳定时，确定校准完毕，有效缩短了锁相环路的相位检测时限。另外，利用调节电荷泵和低通滤波器的方式来改变压控信号的环路带宽，能够在不更改锁相环路的电路结构的情况下，实现环路带宽的调整，有效降低了锁相环路的电路结构的复杂度。另外，利用压控信号的振荡频率来确定调谐电压，能够有效提高采集电压的稳定性，避免信号振幅对比较结果的干扰。另外，利用二分法逐步调整电容阵列，能够准确、高效的确定校准结果，减少反复调整的次数，缩短了校准时限。
实施例二
如图8所示，本实施例二提供了一种锁相环路中压控振荡器的校准方法。所述校准方法可以基于上述实施例中的任一可选方案所设计的校准系统来执行。也可以由按照如下步骤的其他校准系统来执行。
步骤S110、在锁相环路所跟踪的相位稳定之前，指示所述压控振荡器输出第一环路带宽的压控信号，并采集所述压控振荡器的电压。
可选的，在压控振荡器上电后以较大的增益向压控振荡器提供电流，使得压控振荡器所输出的压控信号具有较大的环路带宽。当压控振荡器经校准确定相位跟踪稳定后，再通过降低供电电流的增益的方式，使压控振荡器的环路带宽从第一环路带宽降至第二环路带宽。
本实施例可采用至少三种方式来实现环路带宽在第一环路带宽和第二环路带宽之间的切换。
一种可选方案为：通过调节所述压控振荡器的输入电流的方式，调整所述压控振荡器所输出的压控信号的环路带宽为第一环路带宽或第二环路带宽。
可选的，在电荷泵中安装所述电荷泵调控模块。例如，所述电荷泵调控模块为调整电荷泵中电压的控制器件和逻辑电路。当电荷泵上电工作时，所述电荷泵调控模块将电压调在第一档位，使得电荷泵所输出的电流经低通滤波器滤波后，仍具有较大增益。所述压控振荡器基于该电流所输出的压控信号的环路带宽为第一环路带宽。当电荷泵调控模块接收到确定校准指令时，所述电荷泵调控模块将电压从第一档位调至第二档位，使得电荷泵输出至压控振荡器的电流增益较小，所述压控振荡器所输出的压控信号的环路带宽降为第二环路带宽。
第二种可选方案为，通过调节所述压控振荡器中低通滤波器的负载电阻值的方式，调整所述压控振荡器所输出的压控信号的环路带宽为第一环路带宽或第二环路带宽。
可选的，在低通滤波器所在电路中安装低通滤波调控模块。例如，所述低通滤波调控模块为调整低通滤波器中电阻的控制器件和逻辑电路。当低通滤波器上电工作时，所述低通滤波调控模块将电阻调在第一档位，使得低通滤波调控模块输出至压控振荡器的电流增益较大。所述压控振荡器对应输出的压控信号的环路带宽为第一环路带宽。当低通滤波调控模块接收到确定校准指令时，所述低通滤波调控模块将电阻从第一档位调至第二档位，使得低通滤波器输出至压控振荡器的电流增益较小，所述压控振荡器所输出的压控信号的环路带宽 降为第二环路带宽。
第三种可选方案为，同时安装上述的电荷泵调控模块和低通滤波调控模块。通过同时调整该两个调控模块实现令压控振荡器所输出的压控信号的环路带宽为第一环路带宽或第二环路带宽。
步骤S120、基于对所采集的电压与预设的检测电压窗的比较结果，对所述压控信号的环路带宽进行校准。
在此，所采集的电压可以是输入压控振荡器的电压，也可以是压控信号的电压。
可选的，预设有利用电容特性而设计的检测电压窗。例如，选取合适的电容器件，第一端接地，第二端接预设的电压(如Vdd)。在压控振荡器上电时，即刻开始实时采集压控振荡器中的电压，并将所采集的电压与检测电压窗进行比较。当所得到的比较结果均落入所述检测电压窗内，则确定所述压控振荡器所跟踪的相位稳定(即确定校准完毕)，当所得到的比较结果位于所述检测电压窗之外，则确定所述压控振荡器不稳定(即需要继续校准)。
当确定需要继续校准时，通过调整自身中接入压控振荡器的电容、电阻等来调整压控振荡器的调谐增益，并继续检测调谐电压，直至确定校准完毕。
需要说明的是，本领域技术人员并非一定采用上述采集方式，为了提高校准精度，可通过对预设周期内所采集的每个电压进行分析，从中选取调谐电压，再将调谐电压与检测电压窗进行比较。
为了确保校准精度，所预设的检测电压窗的窗宽小于所采集电信号的震荡幅宽。一种可选方案为，按照所述压控振荡器的振荡频率，确定压控信号的调谐电压。
可选的，预设有压控振荡器的相位裕度、及接入压控振荡器中的电阻值和电容值。根据上述参数，预先得到压控信号的振荡频率，并按照所得到的振荡频率来采集压控信号的调谐电压。
例如，利用公式：
Figure PCTCN2016094504-appb-000002
和ωc＝2□ζ□ωn来计算振荡频率。其中，ζ为阻尼因子、φ为相位裕度、ω为电阻值、c为电容值、ωc为振荡频率、ωn为振荡周期。
所述校准系统可根据所述振荡频率来采集调谐电压，并根据所采集的调谐电压与检测电压窗的比较结果进行校准。
在另一种可选情况中，所述校准系统中包含：标识检测电压窗的电压门限区间的三个电阻、两个比较器、与第一比较器的输出端和第二比较器的输出端连接的逻辑器件、以及受所述逻辑器件控制且连接所述压控振荡器的电容阵列。
其中，第一比较器的第一输入端和第二比较器的第一输入端分别连接第二电阻的两端，第一比较器的第二输入端和第二比较器的第二输入端共同接收所采集的电压。
所述逻辑器件根据两比较器所输出的比较结果调整所述电容阵列中接入压控振荡器中的电容值。
在此，每个所述比较器可接收根据所采集的调谐电压。所述逻辑器件当确定当前的调谐电压位于检测电压窗之外，则调整电容阵列中接入压控振荡器的电容器件的数量(即调整所述电容阵列中接入压控振荡器中的电容值)，当确定调谐电压均落入所述检测电压窗之内，则确定校准完毕。
或者，每个所述比较器可实时接收压控振荡器所提供的压控信号。所述逻辑器件按照所确定的振荡频率，检测每个比较器输出的关于调谐电压与检测电压窗之间的比较结果，再按照比较结果来确定是否校准完毕。
当检测到所采集的电压不在检测电压窗内(即确定仍需校准)时，所述逻辑器件通过逐步调整电容阵列中接入压控振荡器的电容值的方式，增加压控振荡器输出的压控信号的调谐增益。
可选的，所述电容阵列中的每个电容之间呈并联趋势，并联的电容器件配有控制开关。初始时所述电容阵列可以全部接入/不接入电容器件，以使得压控振荡器的增益最大/最小，再由最大/最小逐步调整到合适的增益，以达到校准目的。
当所检测的调谐电压高于检测电压窗的上限时，所述逻辑器件按照预设的步长减少电容阵列中接入压控振荡器的电容值，并再次检测下一周期的调谐电压，在上一周期的电容值的基础上，按照步长再次减少电容值，如此逐步增加压控振荡器的调谐增益，直到所检测的调谐电压落入电压窗内。
当所检测的调谐电压低于检测电压窗的下限时，所述逻辑器件按照预设的 步长增加电容阵列中接入压控振荡器的电容值，并再次检测下一周期的调谐电压，在上一周期的电容值的基础上，按照步长再次增加电容值，如此逐步增加压控振荡器的调谐增益，直到所检测的调谐电压落入电压窗内。
在一种可选方式中，所述逻辑器件按照二分法的逐步调整方式，指示电容阵列在当前接入电容器件数量的基础上增加/减少所接入的电容器件数量。
可选的，为了快速调整增益，所述电容阵列接入电容量程一半的电容器件。当所检测的调谐电压高于检测电压窗的上限时，所述逻辑器件采用二分法将电容阵列中当前未接入压控振荡器的并联电容中的一半接入压控振荡器。
当再次检测调谐电压仍高于检测电压窗的上限时，所述逻辑器件再将电容阵列中当前未接入压控振荡器的并联电容中的一半接入压控振荡器。如此逐步调整增益，使得所检测的调谐电压落入检测电压窗。
当再次检测调谐电压低于检测电压窗的下限时，所述逻辑器件断开当前电容阵列中已接入压控振荡器的并联电容中的一半。如此逐步调整增益，使得所检测的调谐电压落入检测电压窗。
或者，当所述逻辑器件当检测到所采集的电压低于检测电压窗的下限时，从电容阵列中接入压控振荡器的并联电容开始，先减少其中已接入压控振荡器的一半并联电容。当再次检测调谐电压低于检测电压窗的下限时，所述逻辑器件在上次已接入并联电容的基础上再次减少一半电容的接入量，以降低压控振荡器的增益，直至检测到所采集的电压高于检测电压窗的上限、或者所采集的电压落入检测电压窗。
当再次检测调谐电压高于检测电压窗的上限时，所述逻辑器件在上次已接入并联电容的基础上，将未接入的并联电容器件中的一半接入压控振荡器，以提高所述增益，直至检测到所采集的电压落入检测电压窗。
当确定相位稳定时，执行步骤S130。
步骤S130、当确定所述压控振荡器所跟踪的相位稳定时，将所述压控信号由第一环路带宽降至第二环路带宽。
可选的，当所检测的调谐电压落入检测电压窗内时，所述逻辑器件可确定校准完毕，并向所述增益调控单元输出确定校准指令，以便增益调控单元控制所述压控振荡器输出第二环路带宽的压控信号。
一种可选情况是，所述逻辑器件在检测到所采集的电压(如调谐电压)落入检测电压窗内时，验证后续采集的电压是否仍落入所述检测电压窗内；当落入所述检测电压窗内，则确定所述压控振荡器所跟踪的相位稳定，并指示所述增益调控单元将所输出的压控信号由第一环路带宽降至第二环路带宽；当未落入所述检测电压窗内，则按照步骤S120中所述的各种方式之一继续调整电容阵列接入压控振荡器的电容值。
当确定校准完毕时，也是锁相环路的相位跟踪收敛的时间。
注意，申请本领域技术人员会理解，本申请不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种变化、重新调整和替代而不会脱离本申请的保护范围。

Claims (14)

  1. 一种锁相环路中压控振荡器的校准系统，包括：增益调控单元和校准检测单元，其中，
    增益调控单元与锁相环路中的压控振荡器输入端相连，用于在所述锁相环路所跟踪的相位稳定之前，指示所述压控振荡器输出第一环路带宽的压控信号；以及
    校准检测单元与所述压控振荡器相连，用于采集所述压控振荡器中的电压，基于对所采集的电压与预设的检测电压窗的比较结果，对所述压控信号的环路带宽进行校准，当确定所述锁相环路所跟踪的相位稳定时，指示所述增益调控单元将所述压控信号由第一环路带宽降至第二环路带宽。
  2. 根据权利要求1所述的锁相环路中压控振荡器的校准系统，其中，所述增益调控单元包括：电荷泵调控模块和/或低通滤波调控模块；
    其中，电荷泵调控模块与所述压控振荡器输入端相连，用于通过调节所述压控振荡器的输入电流的方式，调整所述压控振荡器所输出的压控信号的环路带宽为第一环路带宽或第二环路带宽；以及，
    低通滤波调控模块与所述压控振荡器输入端相连，用于通过调节所述锁相环路中低通滤波器的负载电阻值的方式，调整所述压控振荡器所输出的压控信号的环路带宽为第一环路带宽或第二环路带宽。
  3. 根据权利要求1所述的锁相环路中压控振荡器的校准系统，其中，所述校准检测单元包括：
    调谐电压确定模块，用于按照所述锁相环路中压控振荡器的振荡频率，确定压控信号的调谐电压。
  4. 根据权利要求1或3所述的锁相环路中压控振荡器的校准系统，其中，所述校准检测单元包括：用于标识检测电压窗的电压门限区间的三个电阻、两个比较器、与第一比较器的输出端和第二比较器的输出端连接的逻辑器件、以及受所述逻辑器件控制且连接所述压控振荡器的电容阵列；
    其中，第一比较器的第一输入端和第二比较器的第一输入端分别连接第二电阻的两端，第一比较器的第二输入端和第二比较器的第二输入端共同接收所采集的电压；以及，
    所述逻辑器件根据两比较器所输出的比较结果调整所述电容阵列中接入压控振荡器中的电容值。
  5. 根据权利要求4所述的锁相环路中压控振荡器的校准系统，其中，所述 电容阵列中的每个电容之间呈并联趋势，初始时接入电容量程一半的电容器件。
  6. 根据权利要求4所述的锁相环路中压控振荡器的校准系统，其中，当检测到所采集的电压不在检测电压窗内时，所述逻辑器件通过调整电容阵列中接入压控振荡器的电容值的方式，增加压控振荡器输出的压控信号的调谐增益。
  7. 根据权利要求6所述的锁相环路中压控振荡器的校准系统，其中，所述逻辑器件按照二分法的调整方式，指示电容阵列在当前接入电容器件数量的基础上增加/减少所接入的电容器件数量。
  8. 根据权利要求4所述的锁相环路中压控振荡器的校准系统，其中，当检测到所采集的电压落入检测电压窗内时，所述逻辑器件验证后续采集的电压是否仍落入所述检测电压窗内；当落入所述检测电压窗内，则确定所述压控振荡器所跟踪的相位稳定，并指示所述增益调控单元将所输出的压控信号由第一环路带宽降至第二环路带宽；当未落入所述检测电压窗内，则继续调整电容阵列接入压控振荡器的电容值。
  9. 一种锁相环路中压控振荡器的校准方法，包括：
    在锁相环路所跟踪的相位稳定之前，指示所述锁相环路中的压控振荡器输出第一环路带宽的压控信号，并采集所述压控振荡器的电压；
    基于对所采集的电压与预设的检测电压窗的比较结果，对所述压控信号的环路带宽进行校准；以及，
    当确定所述锁相环路所跟踪的相位稳定时，将所述压控信号由第一环路带宽降至第二环路带宽。
  10. 根据权利要求9所述的锁相环路中压控振荡器的校准方法，其中，所述指示压控振荡器输出第一环路带宽的压控信号包括：
    通过调节所述压控振荡器的输入电流的方式，调整所述压控振荡器所输出的压控信号的环路带宽为第一环路带宽或第二环路带宽；
    和/或，通过调节所述压控振荡器中低通滤波器的负载电阻值的方式，调整所述压控振荡器所输出的压控信号的环路带宽为第一环路带宽或第二环路带宽。
  11. 根据权利要求9所述的锁相环路中压控振荡器的校准方法，其中，所采集的电压为基于所述压控振荡器的振荡频率所确定的调谐电压。
  12. 根据权利要求9或11所述的锁相环路中压控振荡器的校准方法，其中，所述基于对所采集的电压与预设的检测电压窗的比较结果，对所述压控信号的 环路带宽进行校准包括：
    当检测到所采集的电压不在检测电压窗内时，通过调整接入压控振荡器的电容值的方式，增加压控振荡器输出的压控信号的增益。
  13. 根据权利要求12所述的锁相环路中压控振荡器的校准方法，其中，所述通过调整接入压控振荡器的电容值的方式，增加压控振荡器输出的压控信号的增益包括：
    初始上电时在压控振荡器中接入电容量程一半的电容器件；以及，
    按照二分法的调整方式，在当前接入电容器件数量的基础上增加/减少所接入的电容器件数量。
  14. 根据权利要求9或11所述的锁相环路中压控振荡器的校准方法，其中，所述基于对所采集的电压与预设的检测电压窗的比较结果，对所述压控信号的环路带宽进行校准包括：
    当检测到所采集的电压落入检测电压窗内时，验证后续采集的电压是否仍落入所述检测电压窗内；当落入所述检测电压窗内，则确定所述锁相环路所跟踪的相位稳定，并将所输出的压控信号由第一环路带宽降至第二环路带宽；当未落入所述检测电压窗内，则继续调整电接入压控振荡器的电容值。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112203303A (zh) * 2020-09-30 2021-01-08 锐迪科创微电子（北京）有限公司 时延失配校准方法及装置、计算机可读存储介质
CN112203304A (zh) * 2020-09-30 2021-01-08 锐迪科创微电子（北京）有限公司 时延失配校准方法及装置、计算机可读存储介质
CN114401001A (zh) * 2021-12-30 2022-04-26 北京力通通信有限公司 一种锁相环快速锁相方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106209087B (zh) * 2016-06-28 2019-04-16 上海晶曦微电子科技有限公司 锁相环路中压控振荡器的校准系统及方法
CN109391264A (zh) * 2017-08-02 2019-02-26 上海华虹挚芯电子科技有限公司 锁相环路中压控振荡器的校准系统及方法
EP3780395A4 (en) * 2018-04-28 2021-04-21 Huawei Technologies Co., Ltd. PHASE LOOP
CN110212913B (zh) 2019-06-24 2020-04-17 广东高云半导体科技股份有限公司 锁相环及其压控振荡器的校准方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1496604A (zh) * 2001-03-14 2004-05-12 �������ɭ 压控振荡器的自动调谐
CN101582695A (zh) * 2009-06-19 2009-11-18 广州润芯信息技术有限公司 具有快速锁定功能的锁相环频率综合器
US20100127739A1 (en) * 2007-05-30 2010-05-27 Tsuyoshi Ebuchi Spread spectrum control pll circuit and its start-up method
TW201114187A (en) * 2009-10-01 2011-04-16 Mstar Semiconductor Inc Loop bandwidth control apparatus and method of phase locked loop
CN103036560A (zh) * 2012-12-13 2013-04-10 广州润芯信息技术有限公司 锁相环、其闭环频率自动校准电路及方法
CN106209087A (zh) * 2016-06-28 2016-12-07 上海晶曦微电子科技有限公司 锁相环路中压控振荡器的校准系统及方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105577180A (zh) * 2015-12-11 2016-05-11 中国航空工业集团公司西安航空计算技术研究所 一种锁相环快速锁定和带宽校准的系统和方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1496604A (zh) * 2001-03-14 2004-05-12 �������ɭ 压控振荡器的自动调谐
US20100127739A1 (en) * 2007-05-30 2010-05-27 Tsuyoshi Ebuchi Spread spectrum control pll circuit and its start-up method
CN101582695A (zh) * 2009-06-19 2009-11-18 广州润芯信息技术有限公司 具有快速锁定功能的锁相环频率综合器
TW201114187A (en) * 2009-10-01 2011-04-16 Mstar Semiconductor Inc Loop bandwidth control apparatus and method of phase locked loop
CN103036560A (zh) * 2012-12-13 2013-04-10 广州润芯信息技术有限公司 锁相环、其闭环频率自动校准电路及方法
CN106209087A (zh) * 2016-06-28 2016-12-07 上海晶曦微电子科技有限公司 锁相环路中压控振荡器的校准系统及方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112203303A (zh) * 2020-09-30 2021-01-08 锐迪科创微电子（北京）有限公司 时延失配校准方法及装置、计算机可读存储介质
CN112203304A (zh) * 2020-09-30 2021-01-08 锐迪科创微电子（北京）有限公司 时延失配校准方法及装置、计算机可读存储介质
CN112203304B (zh) * 2020-09-30 2023-11-14 锐迪科创微电子（北京）有限公司 时延失配校准方法及装置、计算机可读存储介质
CN112203303B (zh) * 2020-09-30 2023-11-14 锐迪科创微电子（北京）有限公司 时延失配校准方法及装置、计算机可读存储介质
CN114401001A (zh) * 2021-12-30 2022-04-26 北京力通通信有限公司 一种锁相环快速锁相方法
CN114401001B (zh) * 2021-12-30 2022-11-15 北京力通通信有限公司 一种锁相环快速锁相方法

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