JP2006513585A - 検査可能な静電気放電保護回路 - Google Patents
検査可能な静電気放電保護回路 Download PDFInfo
- Publication number
- JP2006513585A JP2006513585A JP2005510021A JP2005510021A JP2006513585A JP 2006513585 A JP2006513585 A JP 2006513585A JP 2005510021 A JP2005510021 A JP 2005510021A JP 2005510021 A JP2005510021 A JP 2005510021A JP 2006513585 A JP2006513585 A JP 2006513585A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- pad
- gate
- esd protection
- protection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007689 inspection Methods 0.000 claims abstract description 54
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 51
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 230000008569 process Effects 0.000 claims description 19
- 238000004806 packaging method and process Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000012858 packaging process Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 35
- 230000002950 deficient Effects 0.000 description 32
- 230000005684 electric field Effects 0.000 description 21
- 239000002184 metal Substances 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 18
- 238000012360 testing method Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 16
- 230000007547 defect Effects 0.000 description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 14
- 229910000679 solder Inorganic materials 0.000 description 14
- 230000015556 catabolic process Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 7
- 239000000523 sample Substances 0.000 description 7
- 238000012216 screening Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000002028 premature Effects 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 229910017980 Ag—Sn Inorganic materials 0.000 description 1
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 229910017758 Cu-Si Inorganic materials 0.000 description 1
- 229910017931 Cu—Si Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- HZEWFHLRYVTOIW-UHFFFAOYSA-N [Ti].[Ni] Chemical compound [Ti].[Ni] HZEWFHLRYVTOIW-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- -1 aluminum-copper-silicon Chemical compound 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 230000003090 exacerbative effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000000707 layer-by-layer assembly Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000002991 molded plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000009662 stress testing Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04073—Bonding areas specifically adapted for connectors of different types
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12035—Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
- Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
ここで、VGSは印加されたゲート電圧、Xoxは酸化膜厚さ、Eavalはなだれ臨界電界であり、表1に示されるようなものである。
Claims (28)
- 半導体デバイスを製造する方法であって、
第1のボンディングパッドを有するデバイスと第2のボンディングパッドを有するESD保護回路とを含むダイを製作する過程と、
前記第1のボンディングパッドに検査システムを電気的に接続して前記デバイスを検査する過程と、
検査後に前記第1のボンディングパッドを前記第2のボンディングパッドに接続する過程とを含み、
前記第1のボンディングパッドを前記第2のボンディングパッドに接続して初めて前記ESD保護回路が静電放電から前記デバイスを保護するために作動するようにしたことを特徴とする方法。 - 前記デバイスが、パワーMOSFETを含み、
前記ダイが、前記パワーMOSFETのゲートに接続されたゲートパッドを含むことを特徴とする請求項1に記載の方法。 - 前記デバイスを検査する過程が、
前記ESD保護回路の許容電圧より高い電圧を前記パワーMOSFETの前記ゲートに印加する過程を含むことを特徴とする請求項2に記載の方法。 - 前記第1のボンディングパッドが、前記パワーMOSFETの前記ゲートパッドであることを特徴とする請求項2に記載の方法。
- 前記第1のボンディングパッドが、前記パワーMOSFETのソースに接続されたソースパッドであることを特徴とする請求項2に記載の方法。
- 前記第1のボンディングパッドを前記第2のボンディングパッドに接続する前に、前記第2のボンディングパッドに検査システムを電気的に接続して前記ESD保護回路を検査する過程を更に含むことを特徴とする請求項1に記載の方法。
- 前記ダイが複数のダイスを含むウェーハの一部分である間に検査が実施されることを特徴とする請求項1に記載の方法。
- 前記第1のボンディングパッドを前記第2のボンディングパッドに接続する過程が、前記ウェーハから前記ダイが分離された後に実施されることを特徴とする請求項7に記載の方法。
- 前記第1のボンディングパッドを前記第2のボンディングパッドに接続する過程が、前記ダイのパッケージング中に実施されることを特徴とする請求項1に記載の方法。
- 前記第1のボンディングパッドを前記第2のボンディングパッドに接続する過程が、
前記第1のボンディングパッドと前記第2のボンディングパッドとを接触させるようなワイヤボンドを形成する過程を含むことを特徴とする請求項1に記載の方法。 - 前記第1のボンディングパッドを前記第2のボンディングパッドに接続する過程が、
第1のワイヤを前記第1のボンディングパッドとリードフレームの一部分とに接続する過程と、
第2のワイヤを前記第2のボンディングパッドと前記リードフレームの前記一部分とに接続する過程とを含むことを特徴とする請求項1に記載の方法。 - 前記リードフレームの前記一部分が、前記ダイを含むパッケージにおいて前記第1のボンディングパッドと前記第2のボンディングパッドとに電気的接続を与えるような外部リードを含むことを特徴とする請求項11に記載の方法。
- 前記第1のボンディングパッドを前記第2のボンディングパッドに接続する過程が、
前記第1のボンディングパッド上に第1の導電性バンプを形成する過程と、
前記第2のボンディングパッド上に第2の導電性バンプを形成する過程と、
前記第1の導電性バンプと前記第2の導電性バンプとを導電性領域に接続する過程とを含むことを特徴とする請求項1に記載の方法。 - 前記第1の導電性バンプと前記第2の導電性バンプとを前記導電性領域に接続する過程が、
前記第1及び第2の導電性バンプが形成される前記ダイの表面を、前記導電性領域を含む基板に接触させる過程と、
前記導電性バンプを前記導電性領域に取着するようなリフロー工程を実行する過程とを含むことを特徴とする請求項13に記載の方法。 - 半導体デバイスを製造する方法であって、
第1のボンディングパッドを有するデバイスと第2のボンディングパッドを有するESD保護回路とを含むダイを製作する過程と、
前記第2のボンディングパッドに検査システムを電気的に接続して前記ESD保護回路を検査する過程と、
検査後に前記第1のボンディングパッドを前記第2のボンディングパッドに接続する過程とを含み、
前記第1のボンディングパッドを前記第2のボンディングパッドに接続して初めて前記ESD保護回路が静電放電から前記デバイスを保護するために作動するようにしたことを特徴とする方法。 - ダイを含む半導体デバイスであって、
第1のボンディングパッドを有するトランジスタと、
第2のボンディングパッドを有するESD保護回路とを含み、
前記第1のボンディングパッドを前記第2のボンディングパッドに接続して初めて前記ESD保護回路が静電放電から前記デバイスを保護するために作動するようにしたことを特徴とするデバイス。 - 前記ESD保護回路が、
前記第2のボンディングパッドに接続されたアノードを有する第1のダイオードと、
前記第1のダイオードのカソードに接続されたカソードを有する第2のダイオードとを含むことを特徴とする請求項16に記載のデバイス。 - 前記第2のダイオードの前記アノードが、前記トランジスタのゲートに電気的に接続されていることを特徴とする請求項17に記載のデバイス。
- 前記第2のダイオードの前記アノードを前記トランジスタの前記ゲートに電気的に接続するような抵抗体を更に含むことを特徴とする請求項18に記載のデバイス。
- 前記ダイ内で前記第1のボンディングパッドが前記トランジスタのソースに電気的に接続していることを特徴とする請求項18に記載のデバイス。
- 前記第2のダイオードの前記アノードが前記トランジスタの前記ソースに電気的に接続されていることを特徴とする請求項17に記載のデバイス。
- 前記ダイ内で前記第1のボンディングパッドが前記トランジスタのゲートに電気的に接続することを特徴とする請求項21に記載のデバイス。
- 前記ダイが、前記トランジスタ及び前記ESD保護回路上にある絶縁層を更に含み、
前記絶縁層が、前記第1のボンディングパッドの一部分と前記第2のボンディングパッドの一部分とを露出するような近接する開口部を含むことを特徴とする請求項16に記載のデバイス。 - 前記絶縁層の前記開口部内にワイヤボンドを更に含み、
前記ワイヤボンドが、前記第1のボンディングパッドと前記第2のボンディングパッド間のギャップを跨いで延在しかつ前記第1のボンディングパッドを前記第2のボンディングパッドに電気的に接続することを特徴とする請求項23に記載のデバイス。 - リードフレームと、
前記ワイヤボンドから前記リードフレームの一部分に延在するワイヤとを更に含むことを特徴とする請求項24に記載のデバイス。 - リードフレームと、
前記第1のボンディングパッドと前記リードフレームとにボンディングされた第1のワイヤと、
前記第2のボンディングパッドと前記リードフレームとにボンディングされた第2のワイヤとを更に含み、
前記第1のボンディングパッドと前記第2のボンディングパッドとが、前記第1のワイヤと前記第2のワイヤと前記リードフレームを介して電気的に接続されていることを特徴とする請求項16に記載のデバイス。 - 前記第1のボンディングパッド上の第1の導電性バンプと、
前記第2のボンディングパッド上の第2の導電性バンプと、
前記第1の導電性バンプと前記第2の導電性バンプとに取着された導電性領域とを更に含むことを特徴とする請求項16に記載のデバイス。 - 前記導電性領域が、フリップチップパッケージ形成のために前記ダイにボンディングされた基板の部分をなすことを特徴とする請求項27に記載のデバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US43583002P | 2002-12-20 | 2002-12-20 | |
US10/423,177 US6906386B2 (en) | 2002-12-20 | 2003-04-24 | Testable electrostatic discharge protection circuits |
PCT/US2003/040628 WO2004059734A1 (en) | 2002-12-20 | 2003-12-19 | Testable electrostatic discharge protection circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006513585A true JP2006513585A (ja) | 2006-04-20 |
Family
ID=32599997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005510021A Pending JP2006513585A (ja) | 2002-12-20 | 2003-12-19 | 検査可能な静電気放電保護回路 |
Country Status (6)
Country | Link |
---|---|
US (3) | US6906386B2 (ja) |
EP (1) | EP1573811A4 (ja) |
JP (1) | JP2006513585A (ja) |
KR (1) | KR100731270B1 (ja) |
AU (1) | AU2003297407A1 (ja) |
WO (1) | WO2004059734A1 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008147923A (ja) * | 2006-12-08 | 2008-06-26 | Renesas Technology Corp | 負荷駆動回路および負荷駆動回路の製造方法 |
JP2008153615A (ja) * | 2006-11-21 | 2008-07-03 | Denso Corp | 電力用半導体装置 |
KR101986711B1 (ko) * | 2017-12-12 | 2019-09-30 | (주) 트리노테크놀로지 | 정전기 보호 기능을 구비한 전력 반도체 장치 |
JP7197646B1 (ja) | 2021-07-28 | 2022-12-27 | 聯嘉光電股▲ふん▼有限公司 | 電気的検出位置を有する垂直型発光ダイオードチップパッケージ |
JP7197645B1 (ja) | 2021-07-28 | 2022-12-27 | 聯嘉光電股▲ふん▼有限公司 | 複数のテスト端子及び並列接続部品を有する発光ダイオードパッケージ |
JP7353312B2 (ja) | 2021-01-07 | 2023-09-29 | シーシーエス株式会社 | Led光源、及び、led光源の検査方法 |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI232569B (en) * | 2003-03-21 | 2005-05-11 | Comchip Technology Co Ltd | Metal bonding method for semiconductor circuit components employing prescribed feeds of metal balls |
JP4248953B2 (ja) | 2003-06-30 | 2009-04-02 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US20050269677A1 (en) * | 2004-05-28 | 2005-12-08 | Martin Standing | Preparation of front contact for surface mounting |
DE102004041088B4 (de) * | 2004-08-24 | 2009-07-02 | Infineon Technologies Ag | Halbleiterbauteil in Flachleitertechnik mit einem Halbleiterchip und Verfahren zu seiner Herstellung |
JP4913336B2 (ja) * | 2004-09-28 | 2012-04-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20060151785A1 (en) * | 2005-01-13 | 2006-07-13 | Campbell Robert J | Semiconductor device with split pad design |
US7479691B2 (en) * | 2005-03-16 | 2009-01-20 | Infineon Technologies Ag | Power semiconductor module having surface-mountable flat external contacts and method for producing the same |
US7462497B2 (en) * | 2005-09-14 | 2008-12-09 | Semiconductor Manufacturing International (Shanghai) Corporation | Method and system for derivation of breakdown voltage for MOS integrated circuit devices |
US7928753B2 (en) | 2006-01-04 | 2011-04-19 | Freescale Semiconductor, Inc. | Device and method for evaluating electrostatic discharge protection capabilities |
US20070153441A1 (en) * | 2006-01-05 | 2007-07-05 | Chien-Chin Hsiao | Voltage-responsive protection device, and lamp-string apparatus that incorporates the same |
US20070176239A1 (en) * | 2006-01-31 | 2007-08-02 | M-Mos Semiconductor Sdn. Bhd. | Trenched MOSFETS with improved ESD protection capability |
TWI496272B (zh) * | 2006-09-29 | 2015-08-11 | Fairchild Semiconductor | 用於功率金氧半導體場效電晶體之雙電壓多晶矽二極體靜電放電電路 |
US8155916B2 (en) * | 2008-07-07 | 2012-04-10 | Infineon Technologies Ag | Semiconductor component and method of determining temperature |
JP6000513B2 (ja) | 2011-02-17 | 2016-09-28 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 絶縁ゲート型半導体装置 |
US8659860B2 (en) * | 2011-07-14 | 2014-02-25 | Cooper Technologies Company | Transient voltage blocking for power converter |
JP5926988B2 (ja) * | 2012-03-08 | 2016-05-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9229446B2 (en) | 2012-05-08 | 2016-01-05 | International Business Machines Corporation | Production line quality processes |
WO2014006442A1 (en) * | 2012-07-02 | 2014-01-09 | Freescale Semiconductor, Inc. | Integrated circuit device, safety circuit, safety-critical system and method of manufacturing an integrated circuit device |
US20140264434A1 (en) * | 2013-03-15 | 2014-09-18 | Fairchild Semiconductor Corporation | Monolithic ignition insulated-gate bipolar transistor |
US9594246B2 (en) | 2014-01-21 | 2017-03-14 | Osterhout Group, Inc. | See-through computer display systems |
JP6462367B2 (ja) * | 2015-01-13 | 2019-01-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN105259722A (zh) | 2015-11-24 | 2016-01-20 | 京东方科技集团股份有限公司 | 一种测试元件组及其制作方法、阵列基板及显示装置 |
US10256227B2 (en) | 2016-04-12 | 2019-04-09 | Vishay-Siliconix | Semiconductor device having multiple gate pads |
US20180166419A1 (en) * | 2016-12-12 | 2018-06-14 | Nanya Technology Corporation | Semiconductor package |
JP6619522B1 (ja) * | 2018-03-29 | 2019-12-11 | 新電元工業株式会社 | ワイドギャップ半導体装置 |
US10944256B2 (en) | 2018-03-29 | 2021-03-09 | Intel Corporation | On-die circuitry for electrostatic discharge protection (ESD) analysis |
KR20200051231A (ko) | 2018-11-05 | 2020-05-13 | 삼성전자주식회사 | 반도체 장치, 반도체 장치의 테스트 방법 및 반도체 장치의 제조 방법 |
US11217541B2 (en) | 2019-05-08 | 2022-01-04 | Vishay-Siliconix, LLC | Transistors with electrically active chip seal ring and methods of manufacture |
US11579645B2 (en) * | 2019-06-21 | 2023-02-14 | Wolfspeed, Inc. | Device design for short-circuitry protection circuitry within transistors |
US11218144B2 (en) | 2019-09-12 | 2022-01-04 | Vishay-Siliconix, LLC | Semiconductor device with multiple independent gates |
DE102019127871A1 (de) * | 2019-10-16 | 2021-04-22 | Semikron Elektronik Gmbh & Co. Kg | Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelements |
CN116825850B (zh) * | 2023-08-25 | 2023-11-17 | 江苏应能微电子股份有限公司 | 一种集成esd保护器件的分离栅沟槽mos器件及工艺 |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05160265A (ja) | 1991-04-26 | 1993-06-25 | American Teleph & Telegr Co <Att> | 可遮断性接続 |
US5359211A (en) * | 1991-07-18 | 1994-10-25 | Harris Corporation | High voltage protection using SCRs |
KR970009101B1 (ko) * | 1993-08-18 | 1997-06-05 | 엘지반도체 주식회사 | 정전기(esd) 보호회로의 제조 방법 |
US5652689A (en) | 1994-08-29 | 1997-07-29 | United Microelectronics Corporation | ESD protection circuit located under protected bonding pad |
US5535086A (en) | 1994-09-22 | 1996-07-09 | National Semiconductor Corp. | ESD protection circuit and method for BICMOS devices |
US5637900A (en) * | 1995-04-06 | 1997-06-10 | Industrial Technology Research Institute | Latchup-free fully-protected CMOS on-chip ESD protection circuit |
US5869869A (en) * | 1996-01-31 | 1999-02-09 | Lsi Logic Corporation | Microelectronic device with thin film electrostatic discharge protection structure |
US5708289A (en) * | 1996-02-29 | 1998-01-13 | Sgs-Thomson Microelectronics, Inc. | Pad protection diode structure |
TW359023B (en) * | 1996-04-20 | 1999-05-21 | Winbond Electronics Corp | Device for improvement of static discharge protection in ICs |
JP2850868B2 (ja) * | 1996-08-05 | 1999-01-27 | 日本電気株式会社 | 半導体装置 |
US5900643A (en) * | 1997-05-19 | 1999-05-04 | Harris Corporation | Integrated circuit chip structure for improved packaging |
JPH113984A (ja) * | 1997-06-13 | 1999-01-06 | Hitachi Ltd | 半導体集積回路装置 |
US5991134A (en) * | 1997-06-19 | 1999-11-23 | Advanced Micro Devices, Inc. | Switchable ESD protective shunting circuit for semiconductor devices |
US6147857A (en) * | 1997-10-07 | 2000-11-14 | E. R. W. | Optional on chip power supply bypass capacitor |
US6172383B1 (en) * | 1997-12-31 | 2001-01-09 | Siliconix Incorporated | Power MOSFET having voltage-clamped gate |
KR100506802B1 (ko) * | 1998-05-20 | 2005-10-14 | 삼성전자주식회사 | 모오스 트랜지스터 패키지 |
US6355508B1 (en) * | 1998-09-02 | 2002-03-12 | Micron Technology, Inc. | Method for forming electrostatic discharge protection device having a graded junction |
US6495442B1 (en) * | 2000-10-18 | 2002-12-17 | Magic Corporation | Post passivation interconnection schemes on top of the IC chips |
US6456099B1 (en) * | 1998-12-31 | 2002-09-24 | Formfactor, Inc. | Special contact points for accessing internal circuitry of an integrated circuit |
EP1127377B1 (de) * | 1999-01-15 | 2005-04-20 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Esd-schutztransistor |
US6448865B1 (en) * | 1999-02-25 | 2002-09-10 | Formfactor, Inc. | Integrated circuit interconnect system |
US6180426B1 (en) * | 1999-03-01 | 2001-01-30 | Mou-Shiung Lin | High performance sub-system design and assembly |
TW469622B (en) * | 1999-09-13 | 2001-12-21 | Koninkl Philips Electronics Nv | Semiconductor device with ESD protection |
GB9922763D0 (en) * | 1999-09-28 | 1999-11-24 | Koninkl Philips Electronics Nv | Semiconductor devices |
US6624998B2 (en) * | 2000-01-24 | 2003-09-23 | Medtronic, Inc. | Electrostatic discharge protection scheme in low potential drop environments |
JP4041675B2 (ja) * | 2000-04-20 | 2008-01-30 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
TW473979B (en) * | 2001-03-28 | 2002-01-21 | Silicon Integrated Sys Corp | ESD protection circuit for mixed-voltage I/O by using stacked NMOS transistors with substrate triggering technique |
JP4091838B2 (ja) * | 2001-03-30 | 2008-05-28 | 富士通株式会社 | 半導体装置 |
KR100426330B1 (ko) * | 2001-07-16 | 2004-04-08 | 삼성전자주식회사 | 지지 테이프를 이용한 초박형 반도체 패키지 소자 |
TW518738B (en) * | 2001-09-24 | 2003-01-21 | Faraday Tech Corp | Chip with built-in CMOS having whole-chip ESD protection circuit with low capacitance |
US20030058591A1 (en) * | 2001-09-26 | 2003-03-27 | Jeffrey Johnson | Electro-static discharge protection for high frequency port on an integrated circuit |
US6667870B1 (en) * | 2001-12-12 | 2003-12-23 | Natiional Semiconductor Corporation | Fully distributed slave ESD clamps formed under the bond pads |
US6757147B1 (en) | 2002-05-03 | 2004-06-29 | Pericom Semiconductor Corp. | Pin-to-pin ESD-protection structure having cross-pin activation |
US7705349B2 (en) * | 2002-08-29 | 2010-04-27 | Micron Technology, Inc. | Test inserts and interconnects with electrostatic discharge structures |
-
2003
- 2003-04-24 US US10/423,177 patent/US6906386B2/en not_active Expired - Lifetime
- 2003-12-19 WO PCT/US2003/040628 patent/WO2004059734A1/en active Application Filing
- 2003-12-19 EP EP03814225A patent/EP1573811A4/en not_active Withdrawn
- 2003-12-19 AU AU2003297407A patent/AU2003297407A1/en not_active Abandoned
- 2003-12-19 JP JP2005510021A patent/JP2006513585A/ja active Pending
- 2003-12-19 KR KR1020057011521A patent/KR100731270B1/ko active IP Right Grant
-
2005
- 2005-05-05 US US11/124,439 patent/US7329551B2/en not_active Expired - Fee Related
- 2005-05-05 US US11/123,448 patent/US7432555B2/en not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008153615A (ja) * | 2006-11-21 | 2008-07-03 | Denso Corp | 電力用半導体装置 |
JP2008147923A (ja) * | 2006-12-08 | 2008-06-26 | Renesas Technology Corp | 負荷駆動回路および負荷駆動回路の製造方法 |
KR101986711B1 (ko) * | 2017-12-12 | 2019-09-30 | (주) 트리노테크놀로지 | 정전기 보호 기능을 구비한 전력 반도체 장치 |
JP7353312B2 (ja) | 2021-01-07 | 2023-09-29 | シーシーエス株式会社 | Led光源、及び、led光源の検査方法 |
JP7197646B1 (ja) | 2021-07-28 | 2022-12-27 | 聯嘉光電股▲ふん▼有限公司 | 電気的検出位置を有する垂直型発光ダイオードチップパッケージ |
JP7197645B1 (ja) | 2021-07-28 | 2022-12-27 | 聯嘉光電股▲ふん▼有限公司 | 複数のテスト端子及び並列接続部品を有する発光ダイオードパッケージ |
JP2023018836A (ja) * | 2021-07-28 | 2023-02-09 | 聯嘉光電股▲ふん▼有限公司 | 複数のテスト端子及び並列接続部品を有する発光ダイオードパッケージ |
JP2023018845A (ja) * | 2021-07-28 | 2023-02-09 | 聯嘉光電股▲ふん▼有限公司 | 電気的検出位置を有する垂直型発光ダイオードチップパッケージ |
Also Published As
Publication number | Publication date |
---|---|
WO2004059734A1 (en) | 2004-07-15 |
AU2003297407A8 (en) | 2004-07-22 |
AU2003297407A1 (en) | 2004-07-22 |
EP1573811A1 (en) | 2005-09-14 |
US20050202577A1 (en) | 2005-09-15 |
US20050194643A1 (en) | 2005-09-08 |
US7432555B2 (en) | 2008-10-07 |
US6906386B2 (en) | 2005-06-14 |
US20040119118A1 (en) | 2004-06-24 |
KR20050085826A (ko) | 2005-08-29 |
KR100731270B1 (ko) | 2007-06-21 |
EP1573811A4 (en) | 2010-01-06 |
US7329551B2 (en) | 2008-02-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100731270B1 (ko) | 테스트 가능한 정전기 방전 보호 회로 | |
US9761663B2 (en) | Semiconductor device | |
US7068058B2 (en) | Semiconductor integrated circuit device with test element group circuit | |
JPH1079468A (ja) | 非オーミック特性物質を使用するリードフレーム及び半導体素子 | |
US7709279B2 (en) | Methods for testing semiconductor devices methods for protecting the same from electrostatic discharge events during testing, and methods for fabricating inserts for use in testing semiconductor devices | |
JP5926988B2 (ja) | 半導体装置 | |
US11410892B2 (en) | Semiconductor device and method of inspecting semiconductor device | |
US20210287950A1 (en) | Wirebond damage detector | |
CN101582421B (zh) | 可测试静电放电保护电路 | |
US11004841B2 (en) | Semiconductor device having multiple gate pads | |
JP3792931B2 (ja) | 半導体装置およびそのテスト方法 | |
JP6894544B2 (ja) | 半導体装置の製造方法 | |
JP4179491B2 (ja) | 半導体装置及びその製造方法、ならびにその特性評価方法 | |
JP2924107B2 (ja) | 半導体装置 | |
US11942471B2 (en) | Semiconductor chip, semiconductor device and manufacturing method of semiconductor device | |
JP5861822B2 (ja) | 半導体装置およびその試験方法 | |
JP6681948B2 (ja) | 半導体装置の製造方法および半導体装置の評価方法 | |
JPH11345847A (ja) | 半導体ウエハ及び半導体装置の製造方法 | |
US6180964B1 (en) | Low leakage wire bond pad structure for integrated circuits | |
JP2522207B2 (ja) | 半導体装置 | |
CN113889421A (zh) | 用于检测深沟槽隔离和soi缺陷的筛检方法和设备 | |
JPH01158738A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070402 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090609 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20090909 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20090916 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20091009 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20091019 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100112 |