JP2006513325A5 - - Google Patents

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Publication number
JP2006513325A5
JP2006513325A5 JP2004567443A JP2004567443A JP2006513325A5 JP 2006513325 A5 JP2006513325 A5 JP 2006513325A5 JP 2004567443 A JP2004567443 A JP 2004567443A JP 2004567443 A JP2004567443 A JP 2004567443A JP 2006513325 A5 JP2006513325 A5 JP 2006513325A5
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JP
Japan
Prior art keywords
layer
material layer
metal
depositing
catalytic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004567443A
Other languages
English (en)
Japanese (ja)
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JP5214092B2 (ja
JP2006513325A (ja
Filing date
Publication date
Priority claimed from DE10302644A external-priority patent/DE10302644B3/de
Application filed filed Critical
Priority claimed from PCT/US2003/041185 external-priority patent/WO2004068576A2/en
Publication of JP2006513325A publication Critical patent/JP2006513325A/ja
Publication of JP2006513325A5 publication Critical patent/JP2006513325A5/ja
Application granted granted Critical
Publication of JP5214092B2 publication Critical patent/JP5214092B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2004567443A 2003-01-23 2003-12-22 触媒を用いた無電解めっきによりパターン化された絶縁体上に金属層を形成する方法 Expired - Lifetime JP5214092B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE10302644A DE10302644B3 (de) 2003-01-23 2003-01-23 Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum mittels stromloser Abscheidung unter Verwendung eines Katalysators
DE10302644.4 2003-01-23
US10/602,192 2003-06-24
US10/602,192 US6951816B2 (en) 2003-01-23 2003-06-24 Method of forming a metal layer over patterned dielectric by electroless deposition using a catalyst
PCT/US2003/041185 WO2004068576A2 (en) 2003-01-23 2003-12-22 Method of forming a catalyst containing layer over a patterned dielectric

Publications (3)

Publication Number Publication Date
JP2006513325A JP2006513325A (ja) 2006-04-20
JP2006513325A5 true JP2006513325A5 (enExample) 2009-01-15
JP5214092B2 JP5214092B2 (ja) 2013-06-19

Family

ID=32826166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004567443A Expired - Lifetime JP5214092B2 (ja) 2003-01-23 2003-12-22 触媒を用いた無電解めっきによりパターン化された絶縁体上に金属層を形成する方法

Country Status (5)

Country Link
JP (1) JP5214092B2 (enExample)
KR (1) KR101098568B1 (enExample)
AU (1) AU2003299875A1 (enExample)
GB (1) GB2417132B (enExample)
WO (1) WO2004068576A2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6943106B1 (en) * 2004-02-20 2005-09-13 Micron Technology, Inc. Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling
JP2006128288A (ja) * 2004-10-27 2006-05-18 Tokyo Electron Ltd 成膜方法、半導体装置の製造方法、半導体装置、プログラムおよび記録媒体
CN101578394B (zh) * 2007-07-31 2011-08-03 日矿金属株式会社 通过无电镀形成金属薄膜的镀敷物及其制造方法
WO2010087392A1 (ja) * 2009-01-30 2010-08-05 日鉱金属株式会社 バリア機能を有する金属元素と触媒能を有する金属元素との合金膜を有する基板
TWI864099B (zh) * 2019-09-25 2024-12-01 日商東京威力科創股份有限公司 基板液處理方法及基板液處理裝置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4574095A (en) * 1984-11-19 1986-03-04 International Business Machines Corporation Selective deposition of copper
JPH0762545A (ja) * 1993-08-30 1995-03-07 Mitsubishi Cable Ind Ltd 配線基板およびその製造方法
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6197688B1 (en) * 1998-02-12 2001-03-06 Motorola Inc. Interconnect structure in a semiconductor device and method of formation
US6461675B2 (en) * 1998-07-10 2002-10-08 Cvc Products, Inc. Method for forming a copper film on a substrate
US6380083B1 (en) * 1998-08-28 2002-04-30 Agere Systems Guardian Corp. Process for semiconductor device fabrication having copper interconnects
JP4049978B2 (ja) * 1999-09-15 2008-02-20 三星電子株式会社 メッキを用いた金属配線形成方法
JP2001240960A (ja) * 1999-12-21 2001-09-04 Nippon Sheet Glass Co Ltd 光触媒膜が被覆された物品、その物品の製造方法及びその膜を被覆するために用いるスパッタリングターゲット
KR100338112B1 (ko) * 1999-12-22 2002-05-24 박종섭 반도체 소자의 구리 금속 배선 형성 방법
JP3670238B2 (ja) * 2000-01-07 2005-07-13 株式会社日鉱マテリアルズ 金属めっき方法、前処理剤、それを用いた半導体ウェハー及び半導体装置
JP2001335952A (ja) * 2000-05-31 2001-12-07 Rikogaku Shinkokai 無電解めっき方法、並びに、配線装置およびその製造方法
JP2002004081A (ja) * 2000-06-16 2002-01-09 Learonal Japan Inc シリコンウエハーへの電気めっき方法
US6479902B1 (en) * 2000-06-29 2002-11-12 Advanced Micro Devices, Inc. Semiconductor catalytic layer and atomic layer deposition thereof
JP2002025943A (ja) * 2000-07-12 2002-01-25 Ebara Corp 基板成膜方法
JP2002053971A (ja) * 2000-08-03 2002-02-19 Sony Corp めっき方法及びめっき構造、並びに半導体装置の製造方法及び半導体装置
EP1180553A1 (en) * 2000-08-15 2002-02-20 Air Products And Chemicals, Inc. CVD process for depositing copper on a barrier layer
JP4083968B2 (ja) * 2000-11-02 2008-04-30 株式会社東芝 半導体装置の製造方法
US20020064592A1 (en) * 2000-11-29 2002-05-30 Madhav Datta Electroless method of seed layer depostion, repair, and fabrication of Cu interconnects
US6596344B2 (en) * 2001-03-27 2003-07-22 Sharp Laboratories Of America, Inc. Method of depositing a high-adhesive copper thin film on a metal nitride substrate

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