JP5214092B2 - 触媒を用いた無電解めっきによりパターン化された絶縁体上に金属層を形成する方法 - Google Patents
触媒を用いた無電解めっきによりパターン化された絶縁体上に金属層を形成する方法 Download PDFInfo
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- 239000003054 catalyst Substances 0.000 title claims description 67
- 238000000034 method Methods 0.000 title claims description 65
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- 238000007772 electroless plating Methods 0.000 title description 12
- 239000000463 material Substances 0.000 claims description 106
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 48
- 239000010949 copper Substances 0.000 claims description 48
- 229910052802 copper Inorganic materials 0.000 claims description 48
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- 239000000758 substrate Substances 0.000 claims description 29
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 24
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 18
- 238000009713 electroplating Methods 0.000 claims description 16
- 238000007747 plating Methods 0.000 claims description 16
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- 229910052697 platinum Inorganic materials 0.000 claims description 11
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 1
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
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- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L2221/1089—Stacks of seed layers
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemically Coating (AREA)
- Electrodes Of Semiconductors (AREA)
- Electroplating Methods And Accessories (AREA)
Description
Claims (11)
- 処理チャンバ内において、基板に形成されたパターン化された絶縁体であって、前記基板に形成された金属領域の一部を露出する少なくとも一つの開口部を備えた該パターン化された絶縁体に、第1金属層及び第2金属層からなる金属層を形成するための方法において、
触媒物質を少なくとも一時的に含む気体状の堆積雰囲気において、前記パターン化された絶縁体に前記触媒物質が取り込まれた第1材料層を堆積し、もって前記少なくとも一つの開口部の表面に前記第1材料層が形成されるステップであって、前記気体状の堆積雰囲気は前記処理チャンバに2種類以上の前駆体ガスを供給することによって生成され、前記前駆体ガスの少なくとも1つは前記触媒物質を含むところのステップと、
堆積しようとしている前記金属のイオンを含むめっき液に前記第1材料層を曝して前記第1材料層上に前記第1金属層を形成するステップと、
前記触媒物質を含有する前駆体ガスの流量および供給時間の少なくとも一方を制御することによって、前記第1材料層の表面部分に前記触媒物質を取り込むように前記第1材料層に取り込まれる触媒物質の量を制御するステップと、
電気めっきによって前記第1金属層上に前記第2金属層を形成するステップとを含み、
前記第1材料層は、前記第1材料層で覆われた前記基板部分への前記金属の拡散を実質的に防止するバリア層であり、
前記第1金属層は、前記第2金属層を形成するステップにおいてシード層として作用する、方法。 - 前記触媒物質は、白金又はパラジウムを含んでおり、
前記第1材料層に取り込まれる触媒物質の量を制御するステップは、前記触媒物質を含有する前駆体ガスを2〜10秒の範囲の時間間隔にわたり10〜100sccmの流量で供給し、もって前記第1材料層に対する化学量論的比で0.01の前記触媒物質を前記第1材料層に取り込ませるステップを含む、請求項1記載の方法。 - 前記第1材料層を堆積するステップは、前記第1材料の原子をターゲットからスパッタすることによって前記気体状の堆積雰囲気を生成するステップと、前記触媒物質を含有する前駆体を供給するステップとを含む、請求項1記載の方法。
- 前記気体状の堆積雰囲気中の前記第1材料の原子と前記触媒物質の原子との比率を調整するステップをさらに含む、請求項1記載の方法。
- 前記触媒物質を含有する前駆体ガスは、前記第1材料層が所定の厚さに堆積された後に供給される、請求項1記載の方法。
- 前記触媒物質を含有する前駆体ガスは前記第1材料層の堆積を停止した後に供給される、請求項1または3記載の方法。
- 前記第1材料層を堆積するため少なくとも2種類の異なる前駆体ガスがデジタル制御方式で順次供給される、請求項1記載の方法。
- 前記第1金属層及び前記第2金属層は銅を含む、請求項1記載の方法。
- 前記第1材料層を堆積するステップは、前記第1材料の原子および少なくとも一時的に触媒原子をターゲットからスパッタリングすることによって前記気体状の堆積雰囲気を生成するステップを含む、請求項1または6記載の方法。
- 前記触媒物質は前記ターゲットに実質的に均一に分散している、請求項9記載の方法。
- 前記ターゲットはバリア層の1つ以上の部分および触媒物質の1つ以上の部分から形成され、前記バリア層の1つ以上の部分および前記触媒物質の1つ以上の部分の表面領域の比は、実質的に前記ターゲットから放出されるスパッタ原子の比を決める、請求項9記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10302644.4 | 2003-01-23 | ||
DE10302644A DE10302644B3 (de) | 2003-01-23 | 2003-01-23 | Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum mittels stromloser Abscheidung unter Verwendung eines Katalysators |
US10/602,192 | 2003-06-24 | ||
US10/602,192 US6951816B2 (en) | 2003-01-23 | 2003-06-24 | Method of forming a metal layer over patterned dielectric by electroless deposition using a catalyst |
PCT/US2003/041185 WO2004068576A2 (en) | 2003-01-23 | 2003-12-22 | Method of forming a catalyst containing layer over a patterned dielectric |
Publications (3)
Publication Number | Publication Date |
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JP2006513325A JP2006513325A (ja) | 2006-04-20 |
JP2006513325A5 JP2006513325A5 (ja) | 2009-01-15 |
JP5214092B2 true JP5214092B2 (ja) | 2013-06-19 |
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JP2004567443A Expired - Lifetime JP5214092B2 (ja) | 2003-01-23 | 2003-12-22 | 触媒を用いた無電解めっきによりパターン化された絶縁体上に金属層を形成する方法 |
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JP (1) | JP5214092B2 (ja) |
KR (1) | KR101098568B1 (ja) |
AU (1) | AU2003299875A1 (ja) |
GB (1) | GB2417132B (ja) |
WO (1) | WO2004068576A2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US6943106B1 (en) * | 2004-02-20 | 2005-09-13 | Micron Technology, Inc. | Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling |
JP2006128288A (ja) * | 2004-10-27 | 2006-05-18 | Tokyo Electron Ltd | 成膜方法、半導体装置の製造方法、半導体装置、プログラムおよび記録媒体 |
CN101578394B (zh) * | 2007-07-31 | 2011-08-03 | 日矿金属株式会社 | 通过无电镀形成金属薄膜的镀敷物及其制造方法 |
WO2010087392A1 (ja) * | 2009-01-30 | 2010-08-05 | 日鉱金属株式会社 | バリア機能を有する金属元素と触媒能を有する金属元素との合金膜を有する基板 |
US20220344205A1 (en) * | 2019-09-25 | 2022-10-27 | Tokyo Electron Limited | Substrate liquid processing method and substate liquid processing apparatus |
Family Cites Families (19)
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US4574095A (en) * | 1984-11-19 | 1986-03-04 | International Business Machines Corporation | Selective deposition of copper |
JPH0762545A (ja) * | 1993-08-30 | 1995-03-07 | Mitsubishi Cable Ind Ltd | 配線基板およびその製造方法 |
US5969422A (en) * | 1997-05-15 | 1999-10-19 | Advanced Micro Devices, Inc. | Plated copper interconnect structure |
US6197688B1 (en) * | 1998-02-12 | 2001-03-06 | Motorola Inc. | Interconnect structure in a semiconductor device and method of formation |
US6461675B2 (en) * | 1998-07-10 | 2002-10-08 | Cvc Products, Inc. | Method for forming a copper film on a substrate |
US6380083B1 (en) * | 1998-08-28 | 2002-04-30 | Agere Systems Guardian Corp. | Process for semiconductor device fabrication having copper interconnects |
US6610596B1 (en) * | 1999-09-15 | 2003-08-26 | Samsung Electronics Co., Ltd. | Method of forming metal interconnection using plating and semiconductor device manufactured by the method |
JP2001240960A (ja) * | 1999-12-21 | 2001-09-04 | Nippon Sheet Glass Co Ltd | 光触媒膜が被覆された物品、その物品の製造方法及びその膜を被覆するために用いるスパッタリングターゲット |
KR100338112B1 (ko) * | 1999-12-22 | 2002-05-24 | 박종섭 | 반도체 소자의 구리 금속 배선 형성 방법 |
WO2001049898A1 (fr) * | 2000-01-07 | 2001-07-12 | Nikko Materials Co., Ltd. | Procede de galvanoplastie, agent de pretraitement et tranche de semi-conducteurs et dispositif semi-conducteur utilisant cette derniere |
JP2001335952A (ja) * | 2000-05-31 | 2001-12-07 | Rikogaku Shinkokai | 無電解めっき方法、並びに、配線装置およびその製造方法 |
JP2002004081A (ja) * | 2000-06-16 | 2002-01-09 | Learonal Japan Inc | シリコンウエハーへの電気めっき方法 |
US6479902B1 (en) * | 2000-06-29 | 2002-11-12 | Advanced Micro Devices, Inc. | Semiconductor catalytic layer and atomic layer deposition thereof |
JP2002025943A (ja) * | 2000-07-12 | 2002-01-25 | Ebara Corp | 基板成膜方法 |
JP2002053971A (ja) * | 2000-08-03 | 2002-02-19 | Sony Corp | めっき方法及びめっき構造、並びに半導体装置の製造方法及び半導体装置 |
EP1180553A1 (en) * | 2000-08-15 | 2002-02-20 | Air Products And Chemicals, Inc. | CVD process for depositing copper on a barrier layer |
JP4083968B2 (ja) * | 2000-11-02 | 2008-04-30 | 株式会社東芝 | 半導体装置の製造方法 |
US20020064592A1 (en) * | 2000-11-29 | 2002-05-30 | Madhav Datta | Electroless method of seed layer depostion, repair, and fabrication of Cu interconnects |
US6596344B2 (en) * | 2001-03-27 | 2003-07-22 | Sharp Laboratories Of America, Inc. | Method of depositing a high-adhesive copper thin film on a metal nitride substrate |
-
2003
- 2003-12-22 JP JP2004567443A patent/JP5214092B2/ja not_active Expired - Lifetime
- 2003-12-22 AU AU2003299875A patent/AU2003299875A1/en not_active Abandoned
- 2003-12-22 WO PCT/US2003/041185 patent/WO2004068576A2/en active Application Filing
- 2003-12-22 KR KR1020057013668A patent/KR101098568B1/ko active IP Right Grant
- 2003-12-22 GB GB0513698A patent/GB2417132B/en not_active Expired - Lifetime
Also Published As
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WO2004068576A3 (en) | 2004-09-10 |
KR20050088363A (ko) | 2005-09-05 |
GB2417132B (en) | 2007-04-04 |
GB2417132A (en) | 2006-02-15 |
GB0513698D0 (en) | 2005-08-10 |
WO2004068576A2 (en) | 2004-08-12 |
KR101098568B1 (ko) | 2011-12-26 |
JP2006513325A (ja) | 2006-04-20 |
AU2003299875A1 (en) | 2004-08-23 |
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