TW200422440A - Methods for forming copper interconnect structures by co-plating of noble metals and structures formed thereby - Google Patents

Abstract

A method of forming a copper interconnect, comprising forming an opening in a dielectric layer disposed on a substrate, forming a barrier layer over the opening, forming a seed layer over the metal layer, and forming a copper-noble metal alloy layer by electroplating and/or electroless deposition on the seed layer. The copper-noble metal alloy improves the electrical characteristics and reliability of the copper interconnect.

Description

200422440 ⑴ 玖, description of the invention [Technical field to which the invention belongs] The present invention relates to the field of microelectronic device processing, and more particularly to a method for forming a copper interconnect structure using electroplating and / or electroless technology, and the formed structure. [Prior art] Transistors-well known in this technology-are the building blocks of all integrated circuits. Modern integrated circuits accurately connect millions of densely constructed transistors that perform a variety of functions. In order to achieve this dramatic increase in the density of circuit components', microelectronics manufacturers have been required to reduce the physical size of circuit components proportionally, and use multilayer interconnect structures to connect circuit components to functional circuits. One of the interconnection processes is called a damascene process (FIG. 5), in which dielectric layers 202 and 202 'are deposited on a substrate 200. The through holes 204, 204, and the trenches 206, 206 'are engraved into the dielectric layers 202 and 202'. Metal layers 208 and 208 '-such as copper or inscriptions-are then formed on the through holes 204, 204' and the trenches 206, 2 06 '. This process can be repeated to achieve internal connection of the plurality of metallization layers through the trenches and vias. The use of copper metal in embedded structures has many advantages over previously used metals such as aluminum, for example, its low resistance. One of the techniques used to deposit copper in a damascene structure is through electroless deposition, which is attractive because of its low cost and high deposition quality. During electroless plating, metal deposition occurs in an aqueous solution containing a reducing agent through a chemical reduction reaction, of which -4-(2) (2) 200422440 does not require an external power source. However, electroless plating requires activation of a non-conductive surface, for example, by providing a sub-layer, electroless plating of metal. However, there are problems with using copper as the interconnect metal in a damascene structure. One of the problems is that copper easily diffuses or drifts into the dielectric layers 202, 202 '(refer to FIG. 5 again), and a short circuit is formed between adjacent circuit elements. Therefore, copper interconnect structures must be encapsulated by diffusion barriers such as giant, molybdenum nitride, titanium nitride (TiN), or titanium tungsten (TiW). Unfortunately, the addition of a diffusion barrier layer may increase the effective dielectric constant of the copper interconnect structure, which results in an increase in resistance-capacitance (RC) delay, which deteriorates the electrical properties of the device. Another problem associated with copper metallization is that copper is susceptible to oxidation, especially during subsequent processing steps. Oxidized copper deteriorates the electrical and mechanical properties of the copper interconnects. Therefore, a sealed encapsulation layer is usually used to provide corrosion resistance to the copper layer. The encapsulation material may include silicon carbide (SiC) and silicon nitride (SiN). This encapsulation layer can also be used as an etch stop, which prevents over-etching of the copper layer during subsequent processing steps. However, this encapsulation may also increase the effective dielectric constant of the copper interconnect structure. Another problem encountered with copper metallization is the electromigration of copper atoms at high current densities, which may cause voids in the metal interconnect structure. One way to reduce the amount of electromigration is to alloy copper metal with copper, tin, indium, or silicon; however, this may significantly increase the resistance of copper. Therefore, there is a need for an improved copper interconnect manufacturing process and structure that increases the corrosion resistance and / or oxidation resistance of copper, increases the electromigration resistance, and / or reduces the effective dielectric constant of the copper interconnect structure. -5- (3) 200422440 [Summary of the invention]

In the following detailed description, reference is made to the accompanying drawings, which are exemplified to show specific embodiments in which the invention may be practiced. These examples are detailed enough to enable those skilled in the art to practice the invention. It should be understood that various embodiments of the present invention-although different-need not be mutually exclusive. For example, a particular feature, structure, or characteristic described herein in conjunction with one embodiment can be implemented in other embodiments without departing from the spirit and scope of the invention. In addition, it should be understood that the position or configuration of individual elements in each disclosed embodiment may be modified without departing from the spirit and scope of the invention. Therefore, the following detailed description is not restrictive, and the scope of the present invention is only defined by the full scope of the properly interpreted scope of the subsidiary application patent and the equivalent scope authorized by the scope of the patent application. In the drawings, the same numbers indicate the same or similar functions in several views.

A method for manufacturing a copper interconnect structure is described. The method includes forming an opening in a dielectric layer deposited on a substrate, forming a barrier layer over the opening, forming a sublayer on a metal layer, and forming a copper-precious layer by electroplating and / or electroless spray plating. The metal alloy layer is on the seed layer. The copper and precious metal alloy layer improves the electrical characteristics and reliability of the copper interconnect structure. Then, an etch stop layer or a cladding layer may be formed on the copper alloy layer. [Embodiment] In one embodiment of the method of the present invention, as shown in FIGS. 1 a-1 f, a dielectric layer 104 is formed on a substrate 102 (FIG. 1 a). Substrate 〖〇2 can include s-tree material, such as sand, insulator on sand, germanium, indium antimonide, lead telluride, arsenic-6 > (4) (4) 200422440 indium phosphide, indium phosphide, gallium arsenide or Gallium antimonide. Although a few examples of materials that can form the substrate 102 are described herein, any material that can be used as a base layer upon which a microelectronic device can be built is within the spirit and scope of the present invention. A dielectric layer 104 is formed on the substrate 102. Those skilled in the art will understand that the dielectric layer 104 can also be formed from a variety of materials, thicknesses, or multiple layers. By way of illustration and not limitation, the dielectric layer 104 may include sand dioxide (preferably), organic material, or inorganic material. Although a few examples of materials that can form the dielectric layer 104 are described here, the layers may be made of other materials used to separate and insulate different metal layers. The dielectric layer 104 can be formed on the substrate 102 using conventional deposition methods, such as chemical vapor deposition ("CVD"), low pressure chemical vapor deposition ("LPCVD"), physical vapor deposition ("PVD,"), or atomic layers Deposition ("ALD"). Preferably, a chemical vapor deposition process is used. In this process, metal oxide precursors (eg, metal chlorides) and steam can be fed into the chemical vapor deposition reactor at a selectable flow rate, It is then operated at a selected temperature and pressure to create an atomic smooth interface between the substrate 102 and the dielectric layer 104. The chemical vapor deposition reactor must be operated long enough 'to form the dielectric layer 104 having a desired thickness. In most applications, the 'dielectric layer 104 is about one micron thick, more preferably between about 6,000 angstroms and about 8,000 angstroms thick. The dielectric layer i 04 may have at least one opening 10 05 formed therein ( Figure lb), which contains at least one through hole 106 and at least one trench. According to the traditional mosaic technique known to those skilled in this technology, it can be used for -7- (5) (5) 200422440 to connect to microelectronic devices. Other metal layers in the structure (not shown). Because this step is well known to everyone who is skilled in this technology, it will not be described in more detail here. With the formation of the opening 105, a barrier layer 108 is deposited on the opening 1 〇5 (Figure 1c). Those skilled in this technology will understand that the barrier layer 108 can be formed of various materials, thicknesses, or multiple material layers. By way of example and not limitation, the barrier layer 108 can use traditional Technical deposition, such as physical vapor deposition, atomic layer deposition, traditional chemical vapor deposition, low pressure chemical vapor deposition, or other such methods known to those skilled in the art. In presently preferred embodiments, the barrier layer may include Any of the following materials: giant, tungsten, titanium, ruthenium, molybdenum, and their alloys with nitrogen, silicon, and carbon. Although here are some examples of materials that can be used to form the barrier layer 108, the layers can be used by Manufactured from other materials that prevent metal from diffusing into the barrier layer 108. The barrier layer 108 may be in a range from about 10 angstroms to about 500 angstroms. A thin barrier layer 108 is preferably (at about 100 angstroms) And 50 0 Angstroms) Because the thin barrier layer contributes less to the total resistance of the copper interconnect structure. Then, a sublayer 1 10 can be selectively formed on the barrier layer 108 (Figure 1d), and can contain only copper, Or its alloy with tin, indium, cadmium, aluminum, magnesium, or its alloy with precious metals such as silver, palladium, platinum, rhodium, ruthenium, gold, indium, or hungry precious metals, or the seed layer 110 may contain only precious metals Metal. Those skilled in the art will understand that the seed layer 110 can be formed of various materials, thicknesses, or multiple material layers. In the presently preferred embodiment, the seed layer 10 is between about 10 angstroms and 2,000 Angstrom thick, and contains a copper-precious metal alloy. The atomic percentage of the precious metal in the seed layer is preferably about ten or less (6) (6) 200422440, and most preferably between about 0.1 and 4 atomic percent. The seed layer 1 10 can be formed on the barrier layer 108 using conventional deposition methods, such as traditional chemical vapor deposition, low-pressure chemical vapor deposition, physical vapor deposition, atomic layer deposition, or others known to those skilled in the art. Such methods. Although many examples of materials that can be used to form the seed layer 1 10 are described here, the seed layer 1 10 can be made of other materials used to activate the surface of the diffusion barrier layer to prepare it for the electroless deposition of copper Or electroplated. In a preferred embodiment, the copper deposition process can be performed using a conventional copper plating process, which is well known in the art, where single or dual damascene structures are filled with copper using a direct current (DC) plating process (see Figure 4) ). First, a surface (barrier layer 108 or seed layer 110) is provided for electroplating of copper 118. Second, the surface is exposed to the plating solution 1 1 9. Then, a copper alloy layer 1 12 is formed on the surface 120. In addition, it is well known in this technology that if the surface is a seed layer 1 1 0, the seed layer 1 1 0 may be consumed by the plating process, so that the seed layer 1 1 0 may become continuous with the copper alloy layer 1 1 2 as shown in the figure. 1 f. In addition, it should be understood that copper plating can be directly formed on the barrier layer because the seed layer is selective, so the seed layer may not be present in one embodiment of the present invention (see FIG. 1 f). In the presently preferred embodiment, the plating solution may contain copper ions, sulfuric acid, chloride ions, additives (such as inhibitors, ie, polyethylene glycol, and anti-inhibitors, ie, 'disulfides), precious metal ions Precious metals and complexing agents (such as thiosulfate and peroxodisulfate). Although some examples of materials that may include a plating solution are described here, the solution may contain a precious metal alloy for depositing copper on a surface such as a barrier layer (7) (7) 200422440 108 or a seed layer 1 ι0 (see figure ie with other material on if)-. Alternatively, the deposition of copper can be performed using an electroless deposition process, including any autocatalytic (i.e., no external power applied) deposition via a thin film of a metal salt interacting with a chemical reducing agent. First, it is necessary for such a skilled person ' to prepare or treat a surface, such as the barrier layer 108, to produce an activated surface, i.e., a surface that is susceptible to an electroless deposition process. Methods for providing activation of a surface for electroless deposition may include contact displacement (where the surface is soaked or sprayed with a contact displacement solution containing copper) or the use of a sub-layer (such as a seed layer 1 10). During the electroless deposition, the seed layer 110 (see FIG. 1c) can be used as an activated surface, and electroless deposition is formed thereon. The seed layer 110 is regarded as a region that controls the displacement of the deposited metal from the electroless deposition process because the metal from the electroless deposition solution is deposited only on the seed layer 110. The inherent selectivity of electroless deposition methods results in higher quality metallized films because it improves the uniformity and continuity of electrolessly deposited metal layers. Second, after an activated surface for electroless deposition (the seed layer 110 in the current embodiment of the present invention) has been provided, the activated surface is exposed to the electroless deposition solution using a method including immersing the activated surface in the electroless deposition solution. Medium 'or spray an electroless deposition solution on the activated surface. Finally, a metal-such as the copper alloy layer 112 (see Fig. 1e) of the present invention-is electrolessly deposited on the activated surface. The copper alloy layer 1 1 2 may include the following alloys: copper silver, copper palladium, copper platinum, copper rhodium, copper ruthenium, copper gold, copper indium, and copper. The percentage of precious metals in the alloy is about four percent atomic weight, preferably between about 0.1 and 4 percent of the original -10- (8) (8) 200422440 sub-weight. The intrusion of precious metals into the copper alloy layer Π 2 increases the corrosion resistance of copper because the copper alloy layer 112 is less susceptible to oxidation due to the non-reactivity of the precious metals compared to pure copper. The copper alloy layer 112 is also more resistant to electromigration than pure copper, because the low solubility of precious metals facilitates plugging the particle boundaries of the copper alloy layer 112 with the precious metals, and plugging the copper layer 112, the barrier layer 108, and the etch stop layer 114. (Which can be deposited in a later step, see Figure 2). This prevents the occurrence of one of the major failure paths (short circuits, etc.) of electromigration, which would otherwise occur along particle boundaries and interfaces. In addition, the oxidation resistance of precious metals prevents failure paths from passing through cracked or porous copper oxides, which may form on the top surface of copper alloy layer 112 and at the interface of barrier layer 108-dielectric layer 104. Thus, a method for forming a copper interconnect structure 113 has been disclosed (see Figs. Le and If). It should be understood that according to the method of the present invention, a plurality of metallization layers may be deposited on top of the copper interconnect structure 1 1 3 as shown in FIGS. 2 and 3. After the copper alloy layers 1 1 2, 1 1 2 'are formed as described above, the etch stop layers 1 1 4, 1 14' may be formed on the copper alloy layers 丨 12, 丨 12 '(Fig. 2). The etch stop layers 1 1 4, 1 1 4 ′ may include silicon carbide, silicon nitride, silicon carbon nitride, and other such materials known in the art. Those skilled in the art will understand that the etch stop layers 1 1 4 and 1 1 4 can be formed from a variety of materials, thicknesses, or multiple layers. Although many examples of materials that can be used to form the uranium etch stop layers 1 1 4 and 1 1 4 5 are described here, the layers can be used during subsequent process steps such as in subsequent lithography, etching, and During the cleaning process step-stop the copper alloy layer 1 12 etching of other materials from manufacturing. Because this process step is well known in the art, it will not be described in detail here. Exemplary explanation instead of -11-(9) (9) 200422440 Restriction, etch stop layers 1 1 4, 1 1 4 'can be deposited using conventional techniques, such as physical vapor deposition, atomic layer deposition, traditional chemical vapor deposition, low pressure chemical vapor Deposition or other such methods known to those skilled in the art. The etch stop layers 1 1 4 and 1 1 4 'may be in a range from about 100 angstroms to about 100 angstroms. Thin etch stop layers 1 1 4 and 1 1 4 5 are preferred because the thin layers contribute less to the overall dielectric constant of the copper interconnect structure. In another embodiment, the cladding layers 116, 116 'may be electrolessly deposited on the copper alloy layers 112, 112' instead of the uranium etch stop layers 114, 114, (Fig. 3). The cladding layers 1 1 6 and 1 1 6 'may contain precious metals or their alloys with refracting metals, for example, silver tungsten, palladium tungsten. In addition, the cladding layers 1 1 6 and 1 16 may include an electrolessly deposited alloy of cobalt nickel and a refracting metal and / or a quasi-metal (SP 'boron or phosphorus) thereof. The use of a cladding layer allows the complete elimination of the etch stop layer, because the copper alloy layers 112, 112 and the cladding layers 116, 116, have local corrosion resistance, so the uranium etch stop function is not required. Elimination of the single stop layer reduces the effective dielectric constant of the copper alloy layer, which improves the electrical properties and rate of the transistor device. As mentioned above, the use of electrolessly deposited precious metal copper alloy metallized structures increases the corrosion resistance and oxidation resistance of copper, increases the resistance to electromigration, and reduces the effective dielectric constant of copper interconnect structures. As a result, the reliability and speed of microelectronic devices has greatly increased. It should be understood that the present invention includes both single and dual damascene structures as well as multilayer metallization structures. Although the foregoing description has detailed certain steps and materials that can be used in the method of the present invention, those skilled in the art understand that many modifications and substitutions can be made. Therefore, an attempt is made to treat all such modifications, changes, substitutions and additions as -12-(10) 200422440 as falling within the spirit and scope of the invention as defined by the scope of the appended application patent. In addition, it is understood that fabrication of multiple metal layer structures on top of a substrate, such as a silicon substrate, to produce a silicon device is well known in the art. Therefore, it has been " understood " the figures provided herein illustrate only a portion of an exemplary microelectronic device related to the implementation of the present invention. Therefore, the present invention is not limited to the structure described here.

[Brief description of the drawings] The specification concludes by specifically pointing out and clearly declaring the scope of the patent application of the present invention, and when read in conjunction with the drawings, the advantages of the present invention are easier to confirm from the following description of the present invention, where: 1 a-1 f represents a cross-section of a structure that may be formed when performing one embodiment of the method of the present invention. Figure 2 represents a cross-section of a structure that may be formed when performing one embodiment of the method of the present invention.

Figure 3 represents a cross-section of a structure that may be formed when performing another embodiment of the method of the present invention. FIG. 4 is a flowchart according to an embodiment of the present invention. FIG. 5 is a cross-sectional drawing of a conventional mosaic interconnect structure in this technology. Schematic description 102 Substrate 104 Dielectric layer-13-200422440 (11) 105 Opening 106 Through hole 107 Trench 108 Barrier layer 110 Seed layer 112 Copper alloy layer 1 1 2? Copper alloy layer 113 Copper interconnect structure 114 Etch stop layer 114 '' Etch stop layer 116 Cladding layer 1165 Cladding layer 118 Copper 119 Electroplating solution 120 Surface 200 Substrate 202 Dielectric layer 2025 Dielectric layer 204 through hole 204? Through hole 206 trench 2 06? Trench 208 metal layer 2 0 8 7 metal layer

Claims (1)

(1) (1) 200422440 Scope of patent application 1 · A copper plating method includes: plating a copper alloy layer on a surface by electroplating, and the copper alloy layer substantially comprises copper and a precious metal. 2. The method of claim 1 in which the copper alloy layer is formed by electroplating. 3. The method of claim 1 in which the copper alloy layer is formed by electroless deposition. 4. The method of claim 1 in which the surface includes a sub-layer or a barrier layer. 5. The method of claim 2 in which the seed layer contains less than about 10 ° /. Atomic weight of precious metals. 6. The method of claim 1 wherein the precious metal comprises a copper alloy layer of less than about 4% atomic weight. 7. The method according to item 1 of the scope of patent application, wherein the precious metal essentially comprises a material selected from the group consisting of silver, palladium, platinum, rhodium, ruthenium, gold, indium, starvation, and combinations thereof. 8 · A method for forming copper interconnects, comprising: forming an opening in a dielectric layer deposited on a substrate; forming a barrier layer on the opening; forming a sublayer on a metal layer; and 幵 / forming copper Layered on the seed layer *, the copper alloy contains copper and -weight metals. 9. The method of claim 8 in the scope of patent application, wherein the copper alloy layer is formed by -15- (2) (2) 200422440 plating. I 0 · The method according to item 8 of the patent application scope, wherein the copper alloy layer is formed by electroless deposition. II. The method of claim 8 wherein the precious metal contains less than about 4% atomic weight copper alloy rhenium. 1 2 The method of claim 8 in which the seed layer contains a precious metal of less than about 10% atomic weight. 13. The method according to item 8 of the scope of patent application, wherein the precious metal actually comprises a material selected from the group consisting of silver, palladium, platinum, rhodium, ruthenium, gold, indium, and combinations thereof. I4. The method according to item 8 of the patent application, wherein the seed layer substantially comprises a compound selected from the group consisting of copper, tin, aluminum, magnesium, silver, palladium, platinum, rhodium, ruthenium, gold, indium, hunger, and combinations thereof. Group material. 15. The method according to item 8 of the patent application, wherein the opening in the dielectric layer is a damascene structure. 16. The method according to item 8 of the scope of patent application, wherein the barrier layer may include a material selected from the group consisting of tungsten, titanium, ruthenium, nitrided nitride, tungsten nitride, titanium nitride, nitrided nails, molybdenum sand, 5 Tungsten carbide, thorium thorium, thorium nail, molybdenum carbide, tungsten carbide, titanium carbide, ruthenium carbide and combinations thereof. 17 · The method according to item 8 of the patent application, further comprising forming an etch stop layer. 18 · The method of claim 17 in the scope of patent application, wherein the etch stop layer substantially comprises a material selected from the group consisting of silicon carbide, silicon nitride, and combinations thereof. -16- (3) (3) 200422440 1 9. The method according to item 18 of the scope of patent application, wherein the etch stop layer is formed by chemical vapor deposition and is less than about 1 GG0 Angstrom thick. 2 0. The method of claim 8 including applying a coating layer. 2 1. The method of claim 20 in the scope of patent application, wherein the coating layer substantially comprises a group selected from the group consisting of silver, palladium, platinum, shackles, ruthenium, gold, indium, starvation, tungsten, and combinations thereof. material. 2 2. The method of claim 21, wherein the coating is formed by electroless deposition. 2 3. The method according to item 22 of the scope of patent application, wherein the coating layer substantially comprises a group selected from the group consisting of cobalt, nickel, tungsten, titanium, giant, molybdenum, chromium, thorium, boron, phosphorus, and combinations thereof. Group of materials. 24. A copper internal connection comprising: a dielectric layer having an opening; a barrier layer on the opening; and a copper alloy layer on the barrier layer, the copper alloy layer substantially comprising copper and a precious metal. 2 5 · If the copper inner connection of item 24 of the patent application scope, the precious metal in rhenium contains a copper alloy layer of less than about 4% atomic weight. 26. The copper internal connection of item 25 of the patent application, which further includes forming a cladding layer on the copper alloy layer. 27. If the copper inner connection in the item of the scope of the patent application, each of the cladding layers substantially comprises a group selected from the group consisting of silver, palladium, platinum, rhodium, ruthenium, gold, indium, starvation, tungsten, and combinations thereof. material. -17- (4) 200422440 28. The copper internal connection of item 24 of the scope of patent application, which further includes forming a uranium etch stop layer on the copper alloy layer. 29. The copper internal connection according to item 28 of the patent application scope, wherein the etch stop layer substantially comprises a material selected from the group consisting of silicon carbide, silicon nitride and combinations thereof. -18-