JP2006500857A - 電圧制御発振器プリセット回路 - Google Patents
電圧制御発振器プリセット回路 Download PDFInfo
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- JP2006500857A JP2006500857A JP2004539325A JP2004539325A JP2006500857A JP 2006500857 A JP2006500857 A JP 2006500857A JP 2004539325 A JP2004539325 A JP 2004539325A JP 2004539325 A JP2004539325 A JP 2004539325A JP 2006500857 A JP2006500857 A JP 2006500857A
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- voltage
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- 230000002194 synthesizing effect Effects 0.000 claims abstract description 12
- 230000010355 oscillation Effects 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 238000003786 synthesis reaction Methods 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
- H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Oscillators With Electromechanical Resonators (AREA)
Abstract
Description
Claims (12)
- 入力電圧から発振信号を生成する電圧制御回路を有する周波数合成回路であって、ロックループモードにおいて、前記発振信号と基準信号との間の位相差を表わす誤差信号の制御のもとで動作するよう構成される周波数合成回路と、前記周波数合成回路が前記位相ロックループモードで動作することをディスエーブルにし、その後、各々の第1及び第2入力電圧値に応じて得られる前記発振信号の第1及び第2周波数を決定するよう構成され、更に、2つの前記周波数及び前記基準信号から制御値を生成するよう構成されるデジタル処理装置と、前記制御値に応じて前記入力電圧をプリセット値にプリセットするよう構成されるデジタル/アナログ変換器とを有する回路。
- 前記周波数合成回路が前記ロックループモードで動作する場合に前記デジタル/アナログ変換器がディスエーブルにされることを特徴とする請求項1に記載の回路。
- 前記誤差信号を生成するよう構成される位相周波数検出器と、チャージポンプ回路と、ループフィルタとを更に有し、前記チャージポンプ回路が、前記誤差信号に応じて電流を供給し、前記ループフィルタが、前記発振信号を決定することを特徴とする請求項1に記載の回路。
- 前記デジタル処理装置が、更に、前記第1及び第2周波数並びに前記第1及び第2電圧値から前記電圧制御発振器の特性を決定し、更に、決定された前記特性及び前記基準信号から前記制御値を決定することを特徴とする請求項1に記載の回路。
- 出力が前記電圧制御発振器の入力に接続されるループフィルタを更に有し、前記デジタル/アナログ変換器の出力が前記ループフィルタの入力に接続され、前記デジタル/アナログ変換器が前記ループフィルタの前記入力を前記プリセット値に設定することを特徴とする請求項1に記載の回路。
- 前記デジタル処理装置が、更に、前記第1及び第2周波数、前記第1及び第2電圧値、並びに前記基準信号の前記周波数に基づいて前記電圧制御発振器の特性の線形補間から前記プリセット値を決定し、前記デジタル処理装置が、更に、前記入力電圧の各々の値と対応付けられた制御値を有するルックアップテーブルから前記制御値を決定することを特徴とする請求項1に記載の回路。
- 入力電圧から発振信号を生成する電圧制御回路を有する周波数合成回路であって、ロックループモードにおいて、前記発振信号と基準信号との間の位相差を表わす誤差信号の制御のもとで動作するよう構成される周波数合成回路と、前記周波数合成回路が前記位相ロックループモードで動作することをディスエーブルにし、その後、各々の第1及び第2入力電圧値に応じて得られる前記発振信号の第1及び第2周波数を決定するよう構成され、更に、2つの前記周波数及び前記基準信号からデジタル制御信号を生成するよう構成されるデジタル処理装置と、前記デジタル制御値に応じて前記入力電圧をプリセットするよう構成されるデジタル/アナログ変換器とを有する装置。
- 前記発振信号を用いて変調されたデータ信号を送信する送信モジュールを更に有する請求項7に記載の装置。
- データ信号を受信し、前記発振信号を用いて前記データ信号を復調する受信モジュールを更に有する請求項7に記載の装置。
- ロックループモードで動作するよう適応された周波数合成回路の電圧制御発振器の入力電圧をプリセットする方法であって、前記周波数合成回路がロックループモードで動作することをディスエーブルにし、前記周波数合成回路がディスエーブルにされている間に、第1及び第2入力電圧に対する前記電圧制御発振器の第1及び第2発振周波数を決定するステップと、基準周波数、前記第1及び第2周波数、並びに前記第1及び第2入力電圧の値からプリセット入力電圧を補間するステップとを有し、デジタル/アナログ変換器によって前記入力電圧をプリセット値に設定することを可能にする方法。
- 前記入力電圧が前記プリセット値に設定される場合に前記周波数合成回路が前記ロックループモードで動作することをイネーブルにするステップを更に有する請求項10に記載の方法。
- 更に、前記プリセット入力電圧が周波数分割器の分割比から補間されることを特徴とする請求項10に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/259,012 US6914489B2 (en) | 2002-09-26 | 2002-09-26 | Voltage-controlled oscillator presetting circuit |
US10/259,012 | 2002-09-26 | ||
PCT/IB2003/004095 WO2004030216A1 (en) | 2002-09-26 | 2003-09-15 | Voltage-controlled oscillator presetting circuit |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2006500857A true JP2006500857A (ja) | 2006-01-05 |
JP2006500857A5 JP2006500857A5 (ja) | 2006-11-09 |
JP4742219B2 JP4742219B2 (ja) | 2011-08-10 |
Family
ID=32029408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004539325A Expired - Fee Related JP4742219B2 (ja) | 2002-09-26 | 2003-09-15 | 電圧制御発振器プリセット回路 |
Country Status (10)
Country | Link |
---|---|
US (1) | US6914489B2 (ja) |
EP (1) | EP1547249B1 (ja) |
JP (1) | JP4742219B2 (ja) |
KR (1) | KR101035827B1 (ja) |
CN (1) | CN100344065C (ja) |
AT (1) | ATE506751T1 (ja) |
AU (1) | AU2003260874A1 (ja) |
DE (1) | DE60336832D1 (ja) |
TW (1) | TWI325692B (ja) |
WO (1) | WO2004030216A1 (ja) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100574980B1 (ko) * | 2004-04-26 | 2006-05-02 | 삼성전자주식회사 | 빠른 주파수 락을 위한 위상 동기 루프 |
CN100525072C (zh) * | 2005-02-03 | 2009-08-05 | 中国科学院半导体研究所 | 高精度高线性度数模混合信号环路压控振荡器 |
CN100525071C (zh) * | 2005-02-03 | 2009-08-05 | 中国科学院半导体研究所 | 具有工艺误差补偿的数模混合信号环路压控振荡器 |
US7323944B2 (en) * | 2005-04-11 | 2008-01-29 | Qualcomm Incorporated | PLL lock management system |
US7613268B2 (en) * | 2005-04-23 | 2009-11-03 | Nortel Networks Limited | Method and apparatus for designing a PLL |
US7403063B2 (en) * | 2005-11-23 | 2008-07-22 | Mediatek Inc. | Apparatus and method for tuning center frequency of a filter |
KR100738960B1 (ko) * | 2006-02-22 | 2007-07-12 | 주식회사 하이닉스반도체 | 피엘엘 및 그 제어방법 |
CN101079630B (zh) * | 2006-05-23 | 2010-05-12 | 中兴通讯股份有限公司 | 一种用于实现时钟相位平滑切换的数字锁相环装置及方法 |
US7471126B2 (en) * | 2006-10-18 | 2008-12-30 | Faraday Technology Corp. | Phase locked loop utilizing frequency folding |
JP4374463B2 (ja) * | 2006-12-26 | 2009-12-02 | 日本電波工業株式会社 | 発振周波数制御回路 |
CN101534120B (zh) * | 2009-04-09 | 2011-09-14 | 华为技术有限公司 | 锁相环电路及其充电方法 |
CN101826858B (zh) * | 2010-02-25 | 2012-02-22 | 华为终端有限公司 | 一种展频装置、生成展频时钟信号的方法及数字电路系统 |
US8248167B2 (en) * | 2010-06-28 | 2012-08-21 | Mstar Semiconductor, Inc. | VCO frequency temperature compensation system for PLLs |
TWI419472B (zh) * | 2010-11-16 | 2013-12-11 | Mstar Semiconductor Inc | 鎖相迴路 |
TWI419471B (zh) * | 2010-11-19 | 2013-12-11 | Mstar Semiconductor Inc | 具有校正功能之鎖相迴路及其校正方法 |
CN103259538B (zh) * | 2012-02-15 | 2016-04-06 | 珠海扬智电子科技有限公司 | 具有防骇功能的芯片及其控制方法 |
CN106230434B (zh) * | 2016-07-18 | 2019-01-08 | 北华航天工业学院 | 一种混合锁相环 |
US10566980B2 (en) * | 2018-03-19 | 2020-02-18 | Stmicroelectronics International N.V. | Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop |
US10594325B2 (en) * | 2018-07-06 | 2020-03-17 | Shenzhen GOODIX Technology Co., Ltd. | Fast wakeup for crystal oscillator |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001094422A (ja) * | 1999-08-26 | 2001-04-06 | Alcatel | 位相ロックループ周波数シンセサイザ |
JP2001320274A (ja) * | 2000-05-12 | 2001-11-16 | Kenwood Corp | Pll回路 |
JP2002204162A (ja) * | 2000-12-28 | 2002-07-19 | Kenwood Corp | 周波数シンセサイザ、移動通信装置及び発振信号生成方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4929918A (en) | 1989-06-07 | 1990-05-29 | International Business Machines Corporation | Setting and dynamically adjusting VCO free-running frequency at system level |
US5563552A (en) * | 1994-01-28 | 1996-10-08 | International Business Machines Corporation | System and method for calibrating damping factor of analog PLL |
GB2330258B (en) * | 1997-10-07 | 2001-06-20 | Nec Technologies | Phase locked loop circuit |
DE19906561B4 (de) * | 1999-02-17 | 2005-08-25 | Dosch & Amand Gmbh & Co. Kg | Phasenregelkreis |
US6735181B1 (en) * | 2000-06-26 | 2004-05-11 | Atmel Corporation | Wireless transceiver with subtractive filter compensating both transmit and receive artifacts |
US6459253B1 (en) * | 2000-09-05 | 2002-10-01 | Telefonaktiebolaget Lm Ericsson (Publ) | Bandwidth calibration for frequency locked loop |
US6552618B2 (en) * | 2000-12-13 | 2003-04-22 | Agere Systems Inc. | VCO gain self-calibration for low voltage phase lock-loop applications |
-
2002
- 2002-09-26 US US10/259,012 patent/US6914489B2/en not_active Expired - Lifetime
-
2003
- 2003-09-15 WO PCT/IB2003/004095 patent/WO2004030216A1/en active Application Filing
- 2003-09-15 CN CNB038229307A patent/CN100344065C/zh not_active Expired - Fee Related
- 2003-09-15 DE DE60336832T patent/DE60336832D1/de not_active Expired - Lifetime
- 2003-09-15 AU AU2003260874A patent/AU2003260874A1/en not_active Abandoned
- 2003-09-15 JP JP2004539325A patent/JP4742219B2/ja not_active Expired - Fee Related
- 2003-09-15 EP EP03798305A patent/EP1547249B1/en not_active Expired - Lifetime
- 2003-09-15 KR KR1020057005028A patent/KR101035827B1/ko active IP Right Grant
- 2003-09-15 AT AT03798305T patent/ATE506751T1/de not_active IP Right Cessation
- 2003-09-23 TW TW092126206A patent/TWI325692B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001094422A (ja) * | 1999-08-26 | 2001-04-06 | Alcatel | 位相ロックループ周波数シンセサイザ |
JP2001320274A (ja) * | 2000-05-12 | 2001-11-16 | Kenwood Corp | Pll回路 |
JP2002204162A (ja) * | 2000-12-28 | 2002-07-19 | Kenwood Corp | 周波数シンセサイザ、移動通信装置及び発振信号生成方法 |
Also Published As
Publication number | Publication date |
---|---|
ATE506751T1 (de) | 2011-05-15 |
EP1547249A1 (en) | 2005-06-29 |
CN100344065C (zh) | 2007-10-17 |
DE60336832D1 (de) | 2011-06-01 |
TW200419914A (en) | 2004-10-01 |
US6914489B2 (en) | 2005-07-05 |
US20040061559A1 (en) | 2004-04-01 |
TWI325692B (en) | 2010-06-01 |
WO2004030216A1 (en) | 2004-04-08 |
KR20050070000A (ko) | 2005-07-05 |
KR101035827B1 (ko) | 2011-05-20 |
CN1685614A (zh) | 2005-10-19 |
JP4742219B2 (ja) | 2011-08-10 |
AU2003260874A1 (en) | 2004-04-19 |
EP1547249B1 (en) | 2011-04-20 |
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R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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LAPS | Cancellation because of no payment of annual fees |