JP2006344634A5 - - Google Patents
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- Publication number
- JP2006344634A5 JP2006344634A5 JP2005166609A JP2005166609A JP2006344634A5 JP 2006344634 A5 JP2006344634 A5 JP 2006344634A5 JP 2005166609 A JP2005166609 A JP 2005166609A JP 2005166609 A JP2005166609 A JP 2005166609A JP 2006344634 A5 JP2006344634 A5 JP 2006344634A5
- Authority
- JP
- Japan
- Prior art keywords
- formation region
- transistor formation
- halogen element
- insulating film
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 29
- 230000015572 biosynthetic process Effects 0.000 claims 26
- 229910052736 halogen Inorganic materials 0.000 claims 22
- 150000002367 halogens Chemical class 0.000 claims 22
- 239000000758 substrate Substances 0.000 claims 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 10
- 238000004519 manufacturing process Methods 0.000 claims 7
- 229910052757 nitrogen Inorganic materials 0.000 claims 5
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 2
- 229910052731 fluorine Inorganic materials 0.000 claims 2
- 239000011737 fluorine Substances 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 238000005468 ion implantation Methods 0.000 claims 1
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005166609A JP2006344634A (ja) | 2005-06-07 | 2005-06-07 | Ｃｍｏｓ型半導体装置の製造方法および、ｃｍｏｓ型半導体装置 |
| US11/409,081 US7569890B2 (en) | 2005-06-07 | 2006-04-24 | Manufacturing method of CMOS type semiconductor device, and CMOS type semiconductor device |
| US12/492,648 US7863125B2 (en) | 2005-06-07 | 2009-06-26 | Manufacturing method of CMOS type semiconductor device, and CMOS type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005166609A JP2006344634A (ja) | 2005-06-07 | 2005-06-07 | Ｃｍｏｓ型半導体装置の製造方法および、ｃｍｏｓ型半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006344634A JP2006344634A (ja) | 2006-12-21 |
| JP2006344634A5 true JP2006344634A5 (enExample) | 2008-06-26 |
Family
ID=37493328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005166609A Pending JP2006344634A (ja) | 2005-06-07 | 2005-06-07 | Ｃｍｏｓ型半導体装置の製造方法および、ｃｍｏｓ型半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US7569890B2 (enExample) |
| JP (1) | JP2006344634A (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5153164B2 (ja) * | 2007-03-07 | 2013-02-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| KR101356425B1 (ko) * | 2007-09-20 | 2014-01-28 | 삼성전자주식회사 | 모스 트랜지스터의 열화도 추정 방법 및 회로 특성 열화도추정 방법 |
| JP2010027823A (ja) | 2008-07-18 | 2010-02-04 | Nec Electronics Corp | 半導体装置の製造方法および半導体装置 |
| JP5268792B2 (ja) * | 2009-06-12 | 2013-08-21 | パナソニック株式会社 | 半導体装置 |
| JP5449026B2 (ja) * | 2010-05-24 | 2014-03-19 | パナソニック株式会社 | 半導体装置及びその製造方法 |
| US8431955B2 (en) * | 2010-07-21 | 2013-04-30 | International Business Machines Corporation | Method and structure for balancing power and performance using fluorine and nitrogen doped substrates |
| WO2014190069A1 (en) * | 2013-05-21 | 2014-11-27 | Massachusetts Institute Of Technology | Enhancement-mode transistors with increased threshold voltage |
| US9590048B2 (en) * | 2013-10-31 | 2017-03-07 | Infineon Technologies Austria Ag | Electronic device |
| CN105529267A (zh) * | 2014-10-22 | 2016-04-27 | 中芯国际集成电路制造(上海)有限公司 | 一种mosfet器件及其制造方法、电子装置 |
| US9502307B1 (en) | 2015-11-20 | 2016-11-22 | International Business Machines Corporation | Forming a semiconductor structure for reduced negative bias temperature instability |
| CN114068412A (zh) * | 2021-11-18 | 2022-02-18 | 华虹半导体(无锡)有限公司 | Cmos器件的制造方法 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4847213A (en) * | 1988-09-12 | 1989-07-11 | Motorola, Inc. | Process for providing isolation between CMOS devices |
| JPH08316465A (ja) * | 1995-05-12 | 1996-11-29 | Matsushita Electron Corp | 半導体装置およびその製造方法 |
| US6130164A (en) * | 1997-03-26 | 2000-10-10 | Advanced Micro Devices, Inc. | Semiconductor device having gate oxide formed by selective oxide removal and method of manufacture thereof |
| KR19990060472A (ko) | 1997-12-31 | 1999-07-26 | 구본준 | 반도체소자의 산화막 형성방법 |
| JP2000243960A (ja) * | 1998-12-24 | 2000-09-08 | Sharp Corp | 絶縁ゲート型トランジスタとその製造方法 |
| JP3415546B2 (ja) * | 2000-02-24 | 2003-06-09 | Ｎｅｃエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP4437352B2 (ja) | 2000-02-29 | 2010-03-24 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2001291865A (ja) | 2000-04-10 | 2001-10-19 | Sharp Corp | 絶縁ゲート型トランジスタ及びその製造方法 |
| JP2001351917A (ja) | 2000-06-05 | 2001-12-21 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
| JP2002009280A (ja) * | 2000-06-22 | 2002-01-11 | Sharp Corp | 半導体装置およびその製造方法 |
| KR100354438B1 (ko) * | 2000-12-12 | 2002-09-28 | 삼성전자 주식회사 | 모스 트랜지스터의 실리콘 게르마늄 게이트 폴리 형성방법 및 이를 이용한 씨모스 트랜지스터 형성 방법 |
| US6541321B1 (en) * | 2002-05-14 | 2003-04-01 | Advanced Micro Devices, Inc. | Method of making transistors with gate insulation layers of differing thickness |
| US6699771B1 (en) * | 2002-08-06 | 2004-03-02 | Texas Instruments Incorporated | Process for optimizing junctions formed by solid phase epitaxy |
| JP2004281690A (ja) * | 2003-03-14 | 2004-10-07 | Seiko Epson Corp | 半導体装置及び半導体装置の製造方法 |
| JP4919586B2 (ja) * | 2004-06-14 | 2012-04-18 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
| US7227201B2 (en) * | 2004-08-27 | 2007-06-05 | Texas Instruments Incorporated | CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers |
| JP4559938B2 (ja) * | 2004-11-08 | 2010-10-13 | パナソニック株式会社 | 半導体装置の製造方法 |
| US7514310B2 (en) * | 2004-12-01 | 2009-04-07 | Samsung Electronics Co., Ltd. | Dual work function metal gate structure and related method of manufacture |
-
2005
- 2005-06-07 JP JP2005166609A patent/JP2006344634A/ja active Pending
-
2006
- 2006-04-24 US US11/409,081 patent/US7569890B2/en active Active
-
2009
- 2009-06-26 US US12/492,648 patent/US7863125B2/en active Active
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