JP2006344634A - Cmos型半導体装置の製造方法および、cmos型半導体装置 - Google Patents

Cmos型半導体装置の製造方法および、cmos型半導体装置 Download PDF

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Publication number
JP2006344634A
JP2006344634A JP2005166609A JP2005166609A JP2006344634A JP 2006344634 A JP2006344634 A JP 2006344634A JP 2005166609 A JP2005166609 A JP 2005166609A JP 2005166609 A JP2005166609 A JP 2005166609A JP 2006344634 A JP2006344634 A JP 2006344634A
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Japan
Prior art keywords
semiconductor substrate
insulating film
gate insulating
semiconductor device
halogen element
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JP2005166609A
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Japanese (ja)
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JP2006344634A5 (enExample
Inventor
Shinpei Tsujikawa
真平 辻川
Yasuhiko Akamatsu
泰彦 赤松
Koji Umeda
浩司 梅田
Jiro Yoshigami
二郎 由上
Seiji Mizutani
斉治 水谷
Masao Inoue
真雄 井上
Junichi Tsuchimoto
淳一 土本
Koji Nomura
幸司 野村
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Renesas Technology Corp
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Renesas Technology Corp
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Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2005166609A priority Critical patent/JP2006344634A/ja
Priority to US11/409,081 priority patent/US7569890B2/en
Publication of JP2006344634A publication Critical patent/JP2006344634A/ja
Publication of JP2006344634A5 publication Critical patent/JP2006344634A5/ja
Priority to US12/492,648 priority patent/US7863125B2/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181Manufacturing their gate insulating layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2005166609A 2005-06-07 2005-06-07 Cmos型半導体装置の製造方法および、cmos型半導体装置 Pending JP2006344634A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2005166609A JP2006344634A (ja) 2005-06-07 2005-06-07 Cmos型半導体装置の製造方法および、cmos型半導体装置
US11/409,081 US7569890B2 (en) 2005-06-07 2006-04-24 Manufacturing method of CMOS type semiconductor device, and CMOS type semiconductor device
US12/492,648 US7863125B2 (en) 2005-06-07 2009-06-26 Manufacturing method of CMOS type semiconductor device, and CMOS type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005166609A JP2006344634A (ja) 2005-06-07 2005-06-07 Cmos型半導体装置の製造方法および、cmos型半導体装置

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JP2006344634A true JP2006344634A (ja) 2006-12-21
JP2006344634A5 JP2006344634A5 (enExample) 2008-06-26

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US (2) US7569890B2 (enExample)
JP (1) JP2006344634A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008218852A (ja) * 2007-03-07 2008-09-18 Renesas Technology Corp 半導体装置の製造方法
WO2010143332A1 (ja) * 2009-06-12 2010-12-16 パナソニック株式会社 半導体装置及びその製造方法
US8088677B2 (en) 2008-07-18 2012-01-03 Renesas Electronics Corporation Method of manufacturing semiconductor device, and semiconductor device
JP2014241421A (ja) * 2010-07-21 2014-12-25 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation トランジスタ・デバイス、集積回路デバイス、集積回路の設計方法および製造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101356425B1 (ko) * 2007-09-20 2014-01-28 삼성전자주식회사 모스 트랜지스터의 열화도 추정 방법 및 회로 특성 열화도추정 방법
JP5449026B2 (ja) * 2010-05-24 2014-03-19 パナソニック株式会社 半導体装置及びその製造方法
US9704959B2 (en) * 2013-05-21 2017-07-11 Massachusetts Institute Of Technology Enhancement-mode transistors with increased threshold voltage
US9590048B2 (en) * 2013-10-31 2017-03-07 Infineon Technologies Austria Ag Electronic device
CN105529267A (zh) * 2014-10-22 2016-04-27 中芯国际集成电路制造(上海)有限公司 一种mosfet器件及其制造方法、电子装置
US9502307B1 (en) 2015-11-20 2016-11-22 International Business Machines Corporation Forming a semiconductor structure for reduced negative bias temperature instability
CN114068412A (zh) * 2021-11-18 2022-02-18 华虹半导体(无锡)有限公司 Cmos器件的制造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316465A (ja) * 1995-05-12 1996-11-29 Matsushita Electron Corp 半導体装置およびその製造方法
JP2000243960A (ja) * 1998-12-24 2000-09-08 Sharp Corp 絶縁ゲート型トランジスタとその製造方法
JP2001237325A (ja) * 2000-02-24 2001-08-31 Nec Corp 半導体装置の製造方法
JP2002009280A (ja) * 2000-06-22 2002-01-11 Sharp Corp 半導体装置およびその製造方法
JP2002217312A (ja) * 2000-12-12 2002-08-02 Samsung Electronics Co Ltd Mosトランジスタのゲルマニウムがドーピングされたポリシリコンゲートの形成方法及びこれを利用したcmosトランジスタの形成方法
JP2004281690A (ja) * 2003-03-14 2004-10-07 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
JP2006156954A (ja) * 2004-11-08 2006-06-15 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4847213A (en) * 1988-09-12 1989-07-11 Motorola, Inc. Process for providing isolation between CMOS devices
US6130164A (en) * 1997-03-26 2000-10-10 Advanced Micro Devices, Inc. Semiconductor device having gate oxide formed by selective oxide removal and method of manufacture thereof
KR19990060472A (ko) 1997-12-31 1999-07-26 구본준 반도체소자의 산화막 형성방법
JP4437352B2 (ja) 2000-02-29 2010-03-24 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP2001291865A (ja) 2000-04-10 2001-10-19 Sharp Corp 絶縁ゲート型トランジスタ及びその製造方法
JP2001351917A (ja) 2000-06-05 2001-12-21 Toshiba Corp 半導体装置の製造方法及び半導体装置
US6541321B1 (en) * 2002-05-14 2003-04-01 Advanced Micro Devices, Inc. Method of making transistors with gate insulation layers of differing thickness
US6699771B1 (en) * 2002-08-06 2004-03-02 Texas Instruments Incorporated Process for optimizing junctions formed by solid phase epitaxy
JP4919586B2 (ja) * 2004-06-14 2012-04-18 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US7227201B2 (en) * 2004-08-27 2007-06-05 Texas Instruments Incorporated CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers
US7514310B2 (en) * 2004-12-01 2009-04-07 Samsung Electronics Co., Ltd. Dual work function metal gate structure and related method of manufacture

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316465A (ja) * 1995-05-12 1996-11-29 Matsushita Electron Corp 半導体装置およびその製造方法
JP2000243960A (ja) * 1998-12-24 2000-09-08 Sharp Corp 絶縁ゲート型トランジスタとその製造方法
JP2001237325A (ja) * 2000-02-24 2001-08-31 Nec Corp 半導体装置の製造方法
JP2002009280A (ja) * 2000-06-22 2002-01-11 Sharp Corp 半導体装置およびその製造方法
JP2002217312A (ja) * 2000-12-12 2002-08-02 Samsung Electronics Co Ltd Mosトランジスタのゲルマニウムがドーピングされたポリシリコンゲートの形成方法及びこれを利用したcmosトランジスタの形成方法
JP2004281690A (ja) * 2003-03-14 2004-10-07 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
JP2006156954A (ja) * 2004-11-08 2006-06-15 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008218852A (ja) * 2007-03-07 2008-09-18 Renesas Technology Corp 半導体装置の製造方法
US8088677B2 (en) 2008-07-18 2012-01-03 Renesas Electronics Corporation Method of manufacturing semiconductor device, and semiconductor device
WO2010143332A1 (ja) * 2009-06-12 2010-12-16 パナソニック株式会社 半導体装置及びその製造方法
JP2010287782A (ja) * 2009-06-12 2010-12-24 Panasonic Corp 半導体装置及びその製造方法
JP2014241421A (ja) * 2010-07-21 2014-12-25 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation トランジスタ・デバイス、集積回路デバイス、集積回路の設計方法および製造方法

Also Published As

Publication number Publication date
US20060273401A1 (en) 2006-12-07
US7863125B2 (en) 2011-01-04
US20090263945A1 (en) 2009-10-22
US7569890B2 (en) 2009-08-04

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