JP2005537672A - 格子調整半導体基板の形成 - Google Patents

格子調整半導体基板の形成 Download PDF

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Publication number
JP2005537672A
JP2005537672A JP2004533596A JP2004533596A JP2005537672A JP 2005537672 A JP2005537672 A JP 2005537672A JP 2004533596 A JP2004533596 A JP 2004533596A JP 2004533596 A JP2004533596 A JP 2004533596A JP 2005537672 A JP2005537672 A JP 2005537672A
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sige layer
sige
layer
dislocations
insulating means
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Japanese (ja)
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JP2005537672A5 (enExample
Inventor
アダム， ダニエル ケープウェル，
ティモシー， ジョン グラスビー，
エバン， ヒューバート， クレスウェル パーカー，
テレンス ホエール，
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ユニバーシティー オブ ワーウィク
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Publication of JP2005537672A publication Critical patent/JP2005537672A/ja
Publication of JP2005537672A5 publication Critical patent/JP2005537672A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
JP2004533596A 2002-09-03 2003-08-12 格子調整半導体基板の形成 Pending JP2005537672A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0220438.6A GB0220438D0 (en) 2002-09-03 2002-09-03 Formation of lattice-turning semiconductor substrates
PCT/GB2003/003514 WO2004023536A1 (en) 2002-09-03 2003-08-12 Formation of lattice-tuning semiconductor substrates

Publications (2)

Publication Number Publication Date
JP2005537672A true JP2005537672A (ja) 2005-12-08
JP2005537672A5 JP2005537672A5 (enExample) 2008-12-18

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Family Applications (1)

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JP2004533596A Pending JP2005537672A (ja) 2002-09-03 2003-08-12 格子調整半導体基板の形成

Country Status (8)

Country Link
US (1) US7179727B2 (enExample)
EP (1) EP1540715A1 (enExample)
JP (1) JP2005537672A (enExample)
KR (1) KR20050038037A (enExample)
CN (1) CN100364052C (enExample)
AU (1) AU2003251376A1 (enExample)
GB (1) GB0220438D0 (enExample)
WO (1) WO2004023536A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109358A (ja) * 2008-10-02 2010-05-13 Sumitomo Chemical Co Ltd 半導体デバイス用基板、半導体デバイス装置、設計システム、製造方法、および設計方法
WO2010134334A1 (ja) * 2009-05-22 2010-11-25 住友化学株式会社 半導体基板、電子デバイス、半導体基板の製造方法及び電子デバイスの製造方法
WO2017090703A1 (ja) * 2015-11-27 2017-06-01 国立大学法人東京大学 Ｇｅ単結晶薄膜の製造方法及び光デバイス

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WO2006011107A1 (en) * 2004-07-22 2006-02-02 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
GB2418531A (en) * 2004-09-22 2006-03-29 Univ Warwick Formation of lattice-tuning semiconductor substrates
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
EP1911086A2 (en) 2005-07-26 2008-04-16 Amberwave Systems Corporation Solutions integrated circuit integration of alternative active area materials
US7638842B2 (en) 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
WO2007112066A2 (en) * 2006-03-24 2007-10-04 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication
US7476606B2 (en) * 2006-03-28 2009-01-13 Northrop Grumman Corporation Eutectic bonding of ultrathin semiconductors
EP2062290B1 (en) 2006-09-07 2019-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction using aspect ratio trapping
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
WO2008051503A2 (en) 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US8304805B2 (en) * 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US9508890B2 (en) * 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
JP2010538495A (ja) * 2007-09-07 2010-12-09 アンバーウェーブ・システムズ・コーポレーション 多接合太陽電池
KR20100094460A (ko) * 2007-12-28 2010-08-26 스미또모 가가꾸 가부시키가이샤 반도체 기판, 반도체 기판의 제조 방법 및 전자 디바이스
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
CN102160145B (zh) 2008-09-19 2013-08-21 台湾积体电路制造股份有限公司 通过外延层过成长的元件形成
US20100072515A1 (en) * 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
CN102379046B (zh) 2009-04-02 2015-06-17 台湾积体电路制造股份有限公司 从晶体材料的非极性平面形成的器件及其制作方法

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US5158907A (en) * 1990-08-02 1992-10-27 At&T Bell Laboratories Method for making semiconductor devices with low dislocation defects
JPH04315419A (ja) * 1991-04-12 1992-11-06 Nec Corp 元素半導体基板上の絶縁膜／化合物半導体積層構造
JPH06260427A (ja) * 1993-03-05 1994-09-16 Nec Corp 半導体膜の選択成長方法
JP2002359189A (ja) * 2001-05-31 2002-12-13 Mitsubishi Materials Silicon Corp 半導体基板と電界効果型トランジスタ並びにＳｉＧｅ層の形成方法及びこれを用いた歪みＳｉ層の形成方法と電界効果型トランジスタの製造方法
JP2004055943A (ja) * 2002-07-23 2004-02-19 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法

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EP1036412A1 (en) 1997-09-16 2000-09-20 Massachusetts Institute Of Technology CO-PLANAR Si AND Ge COMPOSITE SUBSTRATE AND METHOD OF PRODUCING SAME
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JP3587081B2 (ja) 1999-05-10 2004-11-10 豊田合成株式会社 Ｉｉｉ族窒化物半導体の製造方法及びｉｉｉ族窒化物半導体発光素子
EP1192646B1 (en) 1999-06-25 2008-08-13 Massachusetts Institute Of Technology Cyclic thermal anneal for dislocation reduction
JP4406995B2 (ja) * 2000-03-27 2010-02-03 パナソニック株式会社 半導体基板および半導体基板の製造方法
JP4269541B2 (ja) 2000-08-01 2009-05-27 株式会社Ｓｕｍｃｏ 半導体基板と電界効果型トランジスタ並びにＳｉＧｅ層の形成方法及びこれを用いた歪みＳｉ層の形成方法と電界効果型トランジスタの製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5158907A (en) * 1990-08-02 1992-10-27 At&T Bell Laboratories Method for making semiconductor devices with low dislocation defects
JPH04315419A (ja) * 1991-04-12 1992-11-06 Nec Corp 元素半導体基板上の絶縁膜／化合物半導体積層構造
JPH06260427A (ja) * 1993-03-05 1994-09-16 Nec Corp 半導体膜の選択成長方法
JP2002359189A (ja) * 2001-05-31 2002-12-13 Mitsubishi Materials Silicon Corp 半導体基板と電界効果型トランジスタ並びにＳｉＧｅ層の形成方法及びこれを用いた歪みＳｉ層の形成方法と電界効果型トランジスタの製造方法
JP2004055943A (ja) * 2002-07-23 2004-02-19 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109358A (ja) * 2008-10-02 2010-05-13 Sumitomo Chemical Co Ltd 半導体デバイス用基板、半導体デバイス装置、設計システム、製造方法、および設計方法
WO2010134334A1 (ja) * 2009-05-22 2010-11-25 住友化学株式会社 半導体基板、電子デバイス、半導体基板の製造方法及び電子デバイスの製造方法
JP2011009718A (ja) * 2009-05-22 2011-01-13 Sumitomo Chemical Co Ltd 半導体基板、電子デバイス、半導体基板の製造方法及び電子デバイスの製造方法
US8890213B2 (en) 2009-05-22 2014-11-18 Sumitomo Chemical Company, Limited Semiconductor wafer, electronic device, a method of producing semiconductor wafer, and method of producing electronic device
WO2017090703A1 (ja) * 2015-11-27 2017-06-01 国立大学法人東京大学 Ｇｅ単結晶薄膜の製造方法及び光デバイス
JP2017098493A (ja) * 2015-11-27 2017-06-01 国立大学法人 東京大学 Ｇｅ単結晶薄膜の製造方法及び光デバイス

Also Published As

Publication number Publication date
EP1540715A1 (en) 2005-06-15
CN1714427A (zh) 2005-12-28
GB0220438D0 (en) 2002-10-09
CN100364052C (zh) 2008-01-23
US20050245055A1 (en) 2005-11-03
KR20050038037A (ko) 2005-04-25
US7179727B2 (en) 2007-02-20
WO2004023536A1 (en) 2004-03-18
AU2003251376A1 (en) 2004-03-29

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