JP2005513774A - Ｎチャネルトランジスタおよびｐチャネルトランジスタのそれぞれを最適化する、異なるスペーサを形成する方法 - Google Patents

Ｎチャネルトランジスタおよびｐチャネルトランジスタのそれぞれを最適化する、異なるスペーサを形成する方法 Download PDF

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JP2005513774A
JP2005513774A JP2003553602A JP2003553602A JP2005513774A JP 2005513774 A JP2005513774 A JP 2005513774A JP 2003553602 A JP2003553602 A JP 2003553602A JP 2003553602 A JP2003553602 A JP 2003553602A JP 2005513774 A JP2005513774 A JP 2005513774A
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Prior art keywords
channel transistor
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source
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forming
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Pending
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JP2003553602A
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Japanese (ja)
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JP2005513774A5 (https=
Inventor
ジュ ドン−ハイウク
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2005513774A publication Critical patent/JP2005513774A/ja
Publication of JP2005513774A5 publication Critical patent/JP2005513774A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP2003553602A 2001-12-14 2002-12-11 Ｎチャネルトランジスタおよびｐチャネルトランジスタのそれぞれを最適化する、異なるスペーサを形成する方法 Pending JP2005513774A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/014,426 US6562676B1 (en) 2001-12-14 2001-12-14 Method of forming differential spacers for individual optimization of n-channel and p-channel transistors
PCT/US2002/039782 WO2003052799A2 (en) 2001-12-14 2002-12-11 A method of forming differential spacers for individual optimization of n-channel and p-channel transistors

Publications (2)

Publication Number Publication Date
JP2005513774A true JP2005513774A (ja) 2005-05-12
JP2005513774A5 JP2005513774A5 (https=) 2006-02-02

Family

ID=21765406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003553602A Pending JP2005513774A (ja) 2001-12-14 2002-12-11 Ｎチャネルトランジスタおよびｐチャネルトランジスタのそれぞれを最適化する、異なるスペーサを形成する方法

Country Status (8)

Country Link
US (1) US6562676B1 (https=)
EP (1) EP1454342A2 (https=)
JP (1) JP2005513774A (https=)
KR (1) KR100941742B1 (https=)
CN (1) CN1307689C (https=)
AU (1) AU2002359686A1 (https=)
TW (1) TWI260731B (https=)
WO (1) WO2003052799A2 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010509776A (ja) * 2006-11-10 2010-03-25 ラム リサーチ コーポレーション 除去可能なスペーサ
WO2010140244A1 (ja) * 2009-06-05 2010-12-09 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

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US6828219B2 (en) * 2002-03-22 2004-12-07 Winbond Electronics Corporation Stacked spacer structure and process
US7416927B2 (en) * 2002-03-26 2008-08-26 Infineon Technologies Ag Method for producing an SOI field effect transistor
US6894353B2 (en) * 2002-07-31 2005-05-17 Freescale Semiconductor, Inc. Capped dual metal gate transistors for CMOS process and method for making the same
US6677201B1 (en) * 2002-10-01 2004-01-13 Texas Instruments Incorporated Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide semiconductor transistors
US6969646B2 (en) * 2003-02-10 2005-11-29 Chartered Semiconductor Manufacturing Ltd. Method of activating polysilicon gate structure dopants after offset spacer deposition
US6967143B2 (en) * 2003-04-30 2005-11-22 Freescale Semiconductor, Inc. Semiconductor fabrication process with asymmetrical conductive spacers
US7192876B2 (en) * 2003-05-22 2007-03-20 Freescale Semiconductor, Inc. Transistor with independent gate structures
US20050059260A1 (en) * 2003-09-15 2005-03-17 Haowen Bu CMOS transistors and methods of forming same
US7033897B2 (en) * 2003-10-23 2006-04-25 Texas Instruments Incorporated Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology
JP4796747B2 (ja) * 2003-12-25 2011-10-19 富士通セミコンダクター株式会社 Ｃｍｏｓ半導体装置の製造方法
US20050275034A1 (en) * 2004-04-08 2005-12-15 International Business Machines Corporation A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performance
US7687861B2 (en) * 2005-10-12 2010-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Silicided regions for NMOS and PMOS devices
DE102009021490B4 (de) * 2009-05-15 2013-04-04 Globalfoundries Dresden Module One Llc & Co. Kg Mehrschrittabscheidung eines Abstandshaltermaterials zur Reduzierung der Ausbildung von Hohlräumen in einem dielektrischen Material einer Kontaktebene eines Halbleiterbauelements
DE102010064284B4 (de) * 2010-12-28 2016-03-31 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Verfahren zur Herstellung eines Transistors mit einer eingebetteten Sigma-förmigen Halbleiterlegierung mit erhöhter Gleichmäßigkeit
US20130026575A1 (en) * 2011-07-28 2013-01-31 Synopsys, Inc. Threshold adjustment of transistors by controlled s/d underlap
US10038063B2 (en) * 2014-06-10 2018-07-31 International Business Machines Corporation Tunable breakdown voltage RF FET devices
JP6275559B2 (ja) 2014-06-13 2018-02-07 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10361282B2 (en) * 2017-05-08 2019-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a low-K spacer

Citations (5)

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JPH09167804A (ja) * 1995-12-15 1997-06-24 Hitachi Ltd 半導体装置及びその製造方法
JPH09172176A (ja) * 1995-11-21 1997-06-30 Texas Instr Inc <Ti> Ｍｏｓデバイス製造方法
JP2000307015A (ja) * 1999-04-22 2000-11-02 Oki Electric Ind Co Ltd デュアルゲートｃｍｏｓｆｅｔの製造方法
JP2001110913A (ja) * 1999-10-06 2001-04-20 Nec Corp 半導体装置の製造方法
JP2001516154A (ja) * 1997-09-05 2001-09-25 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 個別に最適化されたｎチャネルおよびｐチャネルトランジスタ性能のための除去可能なサイドウォールスペーサを用いるｃｍｏｓプロセス

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KR100186514B1 (ko) * 1996-06-10 1999-04-15 문정환 반도체 소자의 격리영역 형성방법
JP3114654B2 (ja) * 1997-06-05 2000-12-04 日本電気株式会社 半導体装置の製造方法
US5943565A (en) * 1997-09-05 1999-08-24 Advanced Micro Devices, Inc. CMOS processing employing separate spacers for independently optimized transistor performance
US6124610A (en) * 1998-06-26 2000-09-26 Advanced Micro Devices, Inc. Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant
US5981325A (en) * 1999-04-26 1999-11-09 United Semiconductor Corp. Method for manufacturing CMOS
KR20010065744A (ko) * 1999-12-30 2001-07-11 박종섭 모스형 트랜지스터 제조방법
TW459294B (en) * 2000-10-26 2001-10-11 United Microelectronics Corp Self-aligned offset gate structure and its manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172176A (ja) * 1995-11-21 1997-06-30 Texas Instr Inc <Ti> Ｍｏｓデバイス製造方法
JPH09167804A (ja) * 1995-12-15 1997-06-24 Hitachi Ltd 半導体装置及びその製造方法
JP2001516154A (ja) * 1997-09-05 2001-09-25 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 個別に最適化されたｎチャネルおよびｐチャネルトランジスタ性能のための除去可能なサイドウォールスペーサを用いるｃｍｏｓプロセス
JP2000307015A (ja) * 1999-04-22 2000-11-02 Oki Electric Ind Co Ltd デュアルゲートｃｍｏｓｆｅｔの製造方法
JP2001110913A (ja) * 1999-10-06 2001-04-20 Nec Corp 半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010509776A (ja) * 2006-11-10 2010-03-25 ラム リサーチ コーポレーション 除去可能なスペーサ
WO2010140244A1 (ja) * 2009-06-05 2010-12-09 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5374585B2 (ja) * 2009-06-05 2013-12-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9449883B2 (en) 2009-06-05 2016-09-20 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
CN1307689C (zh) 2007-03-28
US6562676B1 (en) 2003-05-13
KR100941742B1 (ko) 2010-02-11
AU2002359686A8 (en) 2003-06-30
TW200303069A (en) 2003-08-16
WO2003052799A3 (en) 2003-08-14
CN1605115A (zh) 2005-04-06
KR20040064305A (ko) 2004-07-16
AU2002359686A1 (en) 2003-06-30
TWI260731B (en) 2006-08-21
EP1454342A2 (en) 2004-09-08
WO2003052799A2 (en) 2003-06-26

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