JP2005256128A - めっき方法 - Google Patents
めっき方法 Download PDFInfo
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- JP2005256128A JP2005256128A JP2004071983A JP2004071983A JP2005256128A JP 2005256128 A JP2005256128 A JP 2005256128A JP 2004071983 A JP2004071983 A JP 2004071983A JP 2004071983 A JP2004071983 A JP 2004071983A JP 2005256128 A JP2005256128 A JP 2005256128A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
【解決手段】 配線基板の半田接続用の端子である銅のランド部4b上に、無電解Ni−Pめっき層13aを形成し、その上に無電解Pdめっき層13bを形成し、その上に無電解Auめっき層を形成する。無電解Ni−Pめっき層13a上に無電解Pdめっき層13bを形成する工程では、下地の無電解Ni−Pめっき層13aから無電解Pdめっき液中へのニッケルの溶出量が5×10-6kg/m2以下となるようにする。無電解Ni−Pめっき層13aと無電解Pdめっき層13bの界面には、10nm以上のボイドは形成されない。その後、配線基板に半導体チップを搭載し、ワイヤボンディングを行い、樹脂封止し、配線基板のランド部4bに半田ボールを接続して、半導体装置を製造する。
【選択図】 図19
Description
2 配線基板
2a 主面
2b 主面
3 半導体チップ
3a 電極
4a ランド部
4b ランド部
5 ボンディングワイヤ
6 封止樹脂
7 半田ボール
11 導体層
12 半田レジスト層
12a 開口部
13 めっき層
13a 無電解Ni−Pめっき層
13b 無電解Pdめっき層
13c 無電解Auめっき層
14 導体層
15 接合材
21 配線基板
21a 主面
21b 主面
21c 基板領域
31 実装基板
31a 主面
32 ランド部
33 半田レジスト層
34 めっき層
41 配線基板
41c 基板領域
42 めっき用配線
43 半導体装置
44 配線基板
51 合金層
52 リン濃縮層
61 ボイド
61a ボイド
71 ツール
72 ツール
75 半導体装置
76 実装基板
77 ロッド
78 歪みゲージ
Claims (5)
- (a)銅を主成分とする導体層上に、リンを含有するニッケルめっき層を無電解めっき法を用いて形成する工程、
(b)前記リンを含有するニッケルめっき層上に無電解めっき法を用いてパラジウムめっき層を形成する工程、を有し、
前記(b)工程において、前記リンを含有するニッケルめっき層から、前記パラジウムめっき層を形成するためのパラジウムめっき液中へのニッケルの溶出量が5×10-6kg/m2以下であることを特徴とするめっき方法。 - (a)半田接続用の端子である銅を主成分とする導体層上に、リンを含有するニッケルめっき層を無電解めっき法を用いて形成する工程、
(b)前記リンを含有するニッケルめっき層上に無電解めっき法を用いてパラジウムめっき層を形成する工程、を有し、
前記(b)工程において、前記リンを含有するニッケルめっき層から、前記パラジウムめっき層を形成するためのパラジウムめっき液中へのニッケルの溶出量が5×10-6kg/m2以下であることを特徴とするめっき方法。 - (a)銅を主成分とする導体層上に、リンを含有するニッケルめっき層を無電解めっき法を用いて形成する工程、
(b)前記リンを含有するニッケルめっき層上に無電解めっき法を用いてパラジウムめっき層を形成する工程、を有し、
前記(b)工程において、前記リンを含有するニッケルめっき層から、前記パラジウムめっき層を形成するためのパラジウムめっき液中へのニッケルの溶出量が5×10-6kg/m2以下であり、前記リンを含有するニッケルめっき層と前記パラジウムめっき層との界面に10nm以上のボイドが形成されないことを特徴とするめっき方法。 - (a)銅を主成分とする導体層上に、リンを含有するニッケルめっき層を無電解めっき法を用いて形成する工程、
(b)前記リンを含有するニッケルめっき層上に無電解めっき法を用いてパラジウムめっき層を形成する工程、
(c)前記パラジウムめっき層上に無電解めっき法を用いて金めっき層を形成する工程、を有し、
前記(b)工程において、前記リンを含有するニッケルめっき層から、前記パラジウムめっき層を形成するためのパラジウムめっき液中へのニッケルの溶出量が5×10-6kg/m2以下であることを特徴とするめっき方法。 - (a)銅を主成分とする導体層上に、リンを含有するニッケルめっき層を無電解めっき法を用いて形成する工程、
(b)前記リンを含有するニッケルめっき層上に無電解めっき法を用いてパラジウムめっき層を形成する工程、
(c)前記パラジウムめっき層上に無電解めっき法を用いて金めっき層を形成する工程、
(d)前記金めっき層上に半田を形成する工程、を有し、
前記(b)工程において、前記リンを含有するニッケルめっき層から、前記パラジウムめっき層を形成するためのパラジウムめっき液中へのニッケルの溶出量が5×10-6kg/m2以下であることを特徴とするめっき方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004071983A JP4719424B2 (ja) | 2004-03-15 | 2004-03-15 | パッド |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004071983A JP4719424B2 (ja) | 2004-03-15 | 2004-03-15 | パッド |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005256128A true JP2005256128A (ja) | 2005-09-22 |
JP4719424B2 JP4719424B2 (ja) | 2011-07-06 |
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Application Number | Title | Priority Date | Filing Date |
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JP2004071983A Expired - Lifetime JP4719424B2 (ja) | 2004-03-15 | 2004-03-15 | パッド |
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JP (1) | JP4719424B2 (ja) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007158331A (ja) * | 2005-11-30 | 2007-06-21 | Freescale Semiconductor Inc | 半導体デバイスのパッケージング方法 |
KR100840444B1 (ko) * | 2006-03-03 | 2008-06-20 | 니혼 엘렉트로플레이팅 엔지니어스 가부시키가이샤 | 전자부품 |
WO2010050094A1 (ja) * | 2008-10-30 | 2010-05-06 | パナソニック株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
JP2011258597A (ja) * | 2010-06-04 | 2011-12-22 | Sumitomo Bakelite Co Ltd | 金メッキ金属微細パターン付き基材、プリント配線板、半導体装置、及び、それらの製造方法 |
US8097962B2 (en) | 2008-05-09 | 2012-01-17 | Panasonic Corporation | Semiconductor device |
JP2014194063A (ja) * | 2013-03-29 | 2014-10-09 | Jx Nippon Mining & Metals Corp | めっき物 |
KR20190020831A (ko) * | 2016-10-05 | 2019-03-04 | 고지마 가가쿠 야쿠힌 가부시키가이샤 | 무전해 팔라듐/금도금 프로세스 |
US10840188B2 (en) | 2018-08-07 | 2020-11-17 | Toshiba Memory Corporation | Semiconductor device |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08209359A (ja) * | 1995-02-07 | 1996-08-13 | Sumitomo Metal Ind Ltd | Icパッケージ |
JPH10284640A (ja) * | 1997-02-07 | 1998-10-23 | Matsushita Electron Corp | 半導体装置用ステム |
JPH11140659A (ja) * | 1997-11-05 | 1999-05-25 | Hitachi Chem Co Ltd | 半導体搭載用基板とその製造方法 |
JP2001358164A (ja) * | 2000-06-13 | 2001-12-26 | Ne Chemcat Corp | 無電解多層めっき皮膜が形成された電極及びその製造方法 |
JP2002057444A (ja) * | 2000-08-08 | 2002-02-22 | Kyocera Corp | 配線基板 |
JP2003129252A (ja) * | 2001-10-16 | 2003-05-08 | Yamato Denki Kogyo Kk | 無電解めっき液、無電解めっき方法、回路基板の製造方法 |
JP2004055624A (ja) * | 2002-07-16 | 2004-02-19 | Murata Mfg Co Ltd | 基板の製造方法 |
-
2004
- 2004-03-15 JP JP2004071983A patent/JP4719424B2/ja not_active Expired - Lifetime
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08209359A (ja) * | 1995-02-07 | 1996-08-13 | Sumitomo Metal Ind Ltd | Icパッケージ |
JPH10284640A (ja) * | 1997-02-07 | 1998-10-23 | Matsushita Electron Corp | 半導体装置用ステム |
JPH11140659A (ja) * | 1997-11-05 | 1999-05-25 | Hitachi Chem Co Ltd | 半導体搭載用基板とその製造方法 |
JP2001358164A (ja) * | 2000-06-13 | 2001-12-26 | Ne Chemcat Corp | 無電解多層めっき皮膜が形成された電極及びその製造方法 |
JP2002057444A (ja) * | 2000-08-08 | 2002-02-22 | Kyocera Corp | 配線基板 |
JP2003129252A (ja) * | 2001-10-16 | 2003-05-08 | Yamato Denki Kogyo Kk | 無電解めっき液、無電解めっき方法、回路基板の製造方法 |
JP2004055624A (ja) * | 2002-07-16 | 2004-02-19 | Murata Mfg Co Ltd | 基板の製造方法 |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007158331A (ja) * | 2005-11-30 | 2007-06-21 | Freescale Semiconductor Inc | 半導体デバイスのパッケージング方法 |
KR100840444B1 (ko) * | 2006-03-03 | 2008-06-20 | 니혼 엘렉트로플레이팅 엔지니어스 가부시키가이샤 | 전자부품 |
US8097962B2 (en) | 2008-05-09 | 2012-01-17 | Panasonic Corporation | Semiconductor device |
US8907468B2 (en) | 2008-05-09 | 2014-12-09 | Panasonic Corporation | Semiconductor device |
CN102124564A (zh) * | 2008-10-30 | 2011-07-13 | 松下电器产业株式会社 | 非易失性半导体存储装置及其制造方法 |
JPWO2010050094A1 (ja) * | 2008-10-30 | 2012-03-29 | パナソニック株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
US8445883B2 (en) | 2008-10-30 | 2013-05-21 | Panasonic Corporation | Nonvolatile semiconductor memory device and manufacturing method thereof |
WO2010050094A1 (ja) * | 2008-10-30 | 2010-05-06 | パナソニック株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
JP2011258597A (ja) * | 2010-06-04 | 2011-12-22 | Sumitomo Bakelite Co Ltd | 金メッキ金属微細パターン付き基材、プリント配線板、半導体装置、及び、それらの製造方法 |
JP2014194063A (ja) * | 2013-03-29 | 2014-10-09 | Jx Nippon Mining & Metals Corp | めっき物 |
KR20190020831A (ko) * | 2016-10-05 | 2019-03-04 | 고지마 가가쿠 야쿠힌 가부시키가이샤 | 무전해 팔라듐/금도금 프로세스 |
KR102066379B1 (ko) | 2016-10-05 | 2020-01-14 | 고지마 가가쿠 야쿠힌 가부시키가이샤 | 무전해 팔라듐/금도금 프로세스 |
US10840188B2 (en) | 2018-08-07 | 2020-11-17 | Toshiba Memory Corporation | Semiconductor device |
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