JP2005244101A - 半導体装置及びそのプログラミング方法 - Google Patents
半導体装置及びそのプログラミング方法 Download PDFInfo
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- JP2005244101A JP2005244101A JP2004054910A JP2004054910A JP2005244101A JP 2005244101 A JP2005244101 A JP 2005244101A JP 2004054910 A JP2004054910 A JP 2004054910A JP 2004054910 A JP2004054910 A JP 2004054910A JP 2005244101 A JP2005244101 A JP 2005244101A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【解決手段】 フューズリンクFLは、第1の端子N1と第2の端子N2の相互間に配置される。第1の端子N1、第2の端子N2、及びフューズリンクFLは、ポリシリコン層13と、その上の金属元素を含む層14とを有し、フューズリンクFLの少なくとも一部は非晶質シリコン層である。
【選択図】 図1
Description
"A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS Logic Process" IEDM 97, 855-858 "Electrically Programmable Fuse (eFUSE) Using Electromigration in Silicides" IEEE Electron Device Letters, Vol. 23, No. 9, September 2002
図14乃至図19は、第2の実施形態を示している。尚、図14乃至図19において、図1、図2と同一部分には同一符号を付す。
図20乃至図24は、第3の実施形態を示している。第1の実施形態において説明したe-フューズ11は、プログラムの前後で大きな抵抗比を持つことが必要であり、プログラム後にサリサイド層が消失した領域をつくりだすことが必要不可欠である。しかし、プログラム後、電圧供給を切った瞬間に、金属元素を偏在させていたクーロン力がなくなるため、金属元素は拡散しはじめる。フューズリンクFLの温度の下がり方が遅く、フューズリンクFLが固化する時間よりも、金属元素の拡散時間の方が早い場合、金属元素はフューズリンクFL内に拡散し、プログラム前後での大きな抵抗比は得られなくなる。このため、e-フューズの信頼性が低下することが懸念される。
Claims (11)
- 第1の端子、第2の端子、及び前記第1、第2の端子の相互間に配置されたフューズリンクを有する半導体装置であって、
前記第1の端子、及び前記第2の端子は、ポリシリコン層と、その上の金属元素を含む層とを有し、
前記フューズリンクの少なくとも一部は非晶質シリコン層であることを特徴とする半導体装置。 - 前記非晶質シリコン層の前記第1の端子側に前記金属元素が偏在していることを特徴とする請求項1に記載の半導体装置
- 第1の端子、第2の端子、及び前記第1、第2の端子の相互間に配置されたフューズリンクを有する半導体装置であって、
前記第1の端子、第2の端子、及び前記フューズリンクは、ポリシリコン層と、その上の金属元素を含む層とを有し、
前記フューズリンクの通電後において、前記ポリシリコン層の少なくとも一部は非晶質シリコン層に変化することを特徴とする半導体装置。 - 前記フューズリンクの通電後において、前記金属元素が前記第1の端子側に偏在し、前記偏在する金属元素と前記第2の端子との間の前記ポリシリコン層は前記非晶質シリコン層に変化することを特徴とする請求項3記載の半導体装置。
- 前記フューズリンクの通電後において、前記第1の端子、第2の端子は前記ポリシリコン層のままであることを特徴とする請求項4記載の半導体装置。
- 第1の端子、第2の端子、及び前記第1、第2の端子の相互間に配置されたフューズリンクを具備し、前記第1の端子、第2の端子、及び前記フューズリンクは、ポリシリコン層と、その上の金属元素を含む層とを有する半導体装置のプログラミング方法であって、
前記フューズリンクに電流を供給することにより、前記フューズリンクの少なくとも一部のポリシリコン層を融解し、この融解されたポリシリコン層の前記第1の端子側に前記金属元素を偏在させることを特徴とする半導体装置のプログラミング方法。 - 前記偏在された金属元素と前記第2の端子との間の前記フューズリンクに接続された第3の端子とを具備することを特徴とする請求項1又は3記載の半導体装置。
- 前記第3の端子はデータの読み出し用端子であることを特徴とする請求項7記載の半導体装置。
- 前記フューズリンクの固化速度は、前記偏在した金属元素の拡散速度より速いことを特徴とする請求項6記載の半導体装置のプログラミング方法。
- 前記第2の端子は、前記第1の端子より熱伝導率が高いことを特徴とする請求項1又は3記載の半導体装置。
- 前記第3の端子は、プログラム時に前記第2の端子への電流供給後に電流が供給されることを特徴とする請求項7記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2004054910A JP4127678B2 (ja) | 2004-02-27 | 2004-02-27 | 半導体装置及びそのプログラミング方法 |
US10/851,143 US7368801B2 (en) | 2004-02-27 | 2004-05-24 | Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same |
US12/099,422 US8105886B2 (en) | 2004-02-27 | 2008-04-08 | Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same |
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JP2004054910A JP4127678B2 (ja) | 2004-02-27 | 2004-02-27 | 半導体装置及びそのプログラミング方法 |
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JP2005244101A true JP2005244101A (ja) | 2005-09-08 |
JP4127678B2 JP4127678B2 (ja) | 2008-07-30 |
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JP (1) | JP4127678B2 (ja) |
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JP2009295673A (ja) * | 2008-06-03 | 2009-12-17 | Nec Electronics Corp | 電気ヒューズ、半導体装置、および電気ヒューズの切断方法 |
JP2010118646A (ja) * | 2008-11-13 | 2010-05-27 | Taiwan Semiconductor Manufacturing Co Ltd | 集積回路デバイスのヒューズ構造 |
JP2018170455A (ja) * | 2017-03-30 | 2018-11-01 | エイブリック株式会社 | 半導体装置 |
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US20080258256A1 (en) | 2008-10-23 |
US8105886B2 (en) | 2012-01-31 |
US7368801B2 (en) | 2008-05-06 |
US20050189613A1 (en) | 2005-09-01 |
JP4127678B2 (ja) | 2008-07-30 |
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