US20070189053A1 - Electrical fuse device based on a phase-change memory element and corresponding programming method - Google Patents

Electrical fuse device based on a phase-change memory element and corresponding programming method Download PDF

Info

Publication number
US20070189053A1
US20070189053A1 US11/625,178 US62517807A US2007189053A1 US 20070189053 A1 US20070189053 A1 US 20070189053A1 US 62517807 A US62517807 A US 62517807A US 2007189053 A1 US2007189053 A1 US 2007189053A1
Authority
US
United States
Prior art keywords
terminal
element
region
fuse
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/625,178
Inventor
Fabio Pellizzer
Innocenzo Tortorelli
Agostino Pirovano
Roberto Bez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to EP06425025.1 priority Critical
Priority to EP20060425025 priority patent/EP1811564B1/en
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Assigned to STMICROELECTRONICS S.R.L. reassignment STMICROELECTRONICS S.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BEZ, ROBERTO, PELLIZZER, FABIO, PIROVANO, AGOSTINO, TORTORELLI, INNOCENZO
Publication of US20070189053A1 publication Critical patent/US20070189053A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/24Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures
    • H01L27/2436Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising multi-terminal selection components, e.g. transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/06Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/122Device geometry
    • H01L45/1233Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/1253Electrodes
    • H01L45/126Electrodes adapted for resistive heating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L45/00Solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof
    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/141Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H01L45/144Tellurides, e.g. GeSbTe
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a calcogenic material, for example GST.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to an electrical fuse device based on a phase-change memory element and to a corresponding programming method, in particular for a read-only memory (ROM) of the one-time-programmable (OTP) type, to which the following description will make reference, without this implying any loss in generality.
  • 2. Description of the Related Art
  • As is known, in the manufacturing process of integrated circuits, one-time-programmable ROMs find a wide range of applications for permanent storage of information, or for forming permanent connections within integrated circuits. For example, these memories can be used for programming redundant elements in order to replace identical elements that have proven faulty during an electrical testing (operation known as EWS—Electrical Wafer Sorting), prior to carrying out packaging or soldering of the integrated circuits on the board, or else for storage of basic information regarding the integrated circuit, such as identifier codes or calibration information. In particular, the aforesaid information must be stored in a permanent way in order to be recovered after the packaging or soldering operations.
  • In order to produce the aforesaid memories using semiconductor technology, the use of E2PROM (Electrically Erasable Programmable Read-Only Memory) devices, fuse devices and anti-fuse devices has been proposed. However, for reasons that will be briefly set forth, the solutions referred to have some problems that do not make their use totally satisfactory within modern integrated devices.
  • In particular, E2PROM devices require oxide layers having a large thickness (for example, 7 nm) to prevent high leakage currents and sustain a charge stored on a corresponding floating terminal. The scales of integration required by modern integrated circuits do not always enable use of such large oxide thicknesses. Furthermore, the use of E2PROM devices in any case involves a high area occupation.
  • The fuse devices commonly used for the applications referred to above are programmed using a laser, which is used to cut a connection after the fuse device has been manufactured. Laser programming entails an additional process step, extraneous to semiconductor technology, and moreover calls for a perfect alignment of the laser with respect to the fuse device to be programmed.
  • Anti-fuse devices are typically based on the perforation of metal-insulator-metal structures to obtain low-resistance paths. Said devices require high programming voltages, and consequently involve high breaking voltages of the programming circuits associated thereto. Furthermore, said devices are generally of a horizontal type and involve a high area occupation.
  • Other types of semiconductor fuse devices that can be electrically altered, for example based on polysilicon resistors, have been proposed, for example in the U.S. Pat. No. 6,337,507 and in the patent application No. US 2003/0218492. However, none of said devices is optimized in terms of costs, manufacturing times, and programming times (which should be as short as possible).
  • Phase-change memories (PCMs) are moreover known, which exploit, for storage of information, the characteristics of materials that have the property of switching between phases having different electrical characteristics. For example, said materials can switch between a disorderly, amorphous phase and an orderly, crystalline or polycrystalline phase, and the two phases are associated to resistivities having considerably different values, and consequently to different values of a stored datum. Currently, the elements of Group VI of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), referred to as calcogenides or calcogenic materials, may advantageously be used to obtain phase-change memory cells. The currently most promising calcogenide is formed by an alloy of Ge, Sb and Te, generically referred to as GST (for example, Ge2Sb2Te5).
  • The phase changes are obtained by locally increasing the temperature of the cells of calcogenic material by means of resistive electrodes (generally known as heaters) set in contact with the region of calcogenic material. A selection device (for example, a MOSFET or a bipolar transistor), is connected to the heater and is configured to enable passage of a programming electrical current through the heater. Said electrical current, by the Joule effect, generates the temperatures necessary for phase change. In particular, since the minimization of the area of contact between the heater and the region of calcogenic material is a primary requisite in such devices, in order to ensure repeatability of the programming operations, the heaters generally have sublithographic sections (i.e., dimensions smaller than the dimensions that can be achieved with current lithographic techniques, for example smaller than 100 nm, down to approximately 5-20 nm).
  • A wide range of manufacturing processes have been proposed to obtain phase-change memory cells, and the configurations of the resulting memory cells are different, in particular as regards coupling between the heater and a corresponding calcogenic region. For example, a microtrench architecture is described in U.S. Pat. No. 6,891,747, while a lance-shaped or ring-shaped tubular architecture is described in U.S. patent application Ser. No. 11/398,858, filed on Apr. 6, 2006.
  • Although advantageous as regards performance and manufacturing costs, PCMs cannot be used in the applications described above. In fact, the high temperatures that are generated during the processes of packaging or soldering on the board can lead to the change of state of previously programmed memory cells and the consequent loss of the stored information. In particular, the possibility exists that memory cells in the amorphous state will switch to the crystalline state on account of said high temperatures.
  • BRIEF SUMMARY OF THE INVENTION
  • One embodiment of the present invention is a fuse device (in particular for one-time-programmable memory elements) that enables the aforesaid disadvantages and problems to be overcome.
  • According to one embodiment of the present invention, a fuse device includes a fuse element having a first terminal and a second terminal, and an electrically breakable region arranged between said first and second terminals and configured to undergo breaking as a result of the supply of a programming electrical quantity, wherein said electrically breakable region comprises phase-change material.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • For a better understanding of the present invention, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached plate of drawings, wherein:
  • FIG. 1 is a schematic top plan view of a semiconductor fuse device according to a first embodiment of the present invention, with parts removed for greater clarity;
  • FIG. 2 is a cross-sectional view of a portion of the fuse device of FIG. 1 taken along the line II-II, in which a phase-change fuse element is illustrated, in a first operating condition;
  • FIG. 3 is a view similar to that of FIG. 2 regarding a second operating condition of the phase-change fuse element;
  • FIGS. 4-6 show graphs regarding electrical quantities associated to the fuse element of FIGS. 2 and 3;
  • FIG. 7 is a view similar to that of FIG. 1, illustrating a variant of the fuse device;
  • FIG. 8 is a view similar to that of FIG. 7, illustrating a further variant of the fuse device;
  • FIG. 9 is a top-plan view of a second embodiment of the fuse device; and
  • FIG. 10 is a cross-sectional view of the fuse device of FIG. 9, taken along the line X-X;
  • FIG. 11 is a top-plan view of a third embodiment of the fuse device;
  • FIG. 12 shows a cross-sectional view of the fuse device of FIG. 11, taken along the line XII-XII;
  • FIG. 13 is a top-plan view of a fourth embodiment of the fuse device;
  • FIG. 14 shows a cross-sectional view of the fuse device of FIG. 13, taken along the line XIV-XIV; and
  • FIG. 15 shows a simplified block diagram of a one-time-programmable storage device.
  • DETAILED DESCRIPTION OF THE INVENTION
  • One embodiment of the present invention envisages use of a phase-change memory element to provide a semiconductor fuse device. The phase-change memory element is programmed for this purpose in two stable states: a low-resistivity closed state (for example corresponding to a “1”), and an open state (for example corresponding to a “0”). In particular, the open state is obtained by physical breaking of a region of calcogenic material of the phase-change memory element, via application of a given electrical quantity (in particular, via the passage of a high electrical current). In this manner, the information associated to both states are stable and not modifiable, for example by soldering or packaging of a corresponding integrated circuit.
  • In detail, and as illustrated in FIGS. 1 and 2, a fuse device 1 according to a first embodiment of the present invention, comprises a fuse element 2 (as will be clarified hereinafter, based on a phase-change memory element), and a selector element 3, which is electrically connected to the fuse element 2 and is configured to enable programming of the fuse element 2. In particular, by way of example, the selector element 3 illustrated in FIG. 1 is an N-channel MOSFET of a planar type. It is clear, however, that other selector elements could be used in an altogether equivalent way, for example any FET (vertical MOSFET, JFET, FinFET, etc.), or else a BJT or a BiFET. Furthermore, FIG. 1 and the following figures illustrate a phase-change memory element having a microtrench architecture. Once again, it is clear that other structures could be used in an altogether equivalent way, for example of the wall or tubular type.
  • In detail, the selector element 3 is provided with: a first current-conduction region (in particular, a current-input region), in the example a drain region 4, and a second current-conduction region (in particular, a current-output region), in the example a source region 5, which are formed, in a known way, within a substrate 6 of semiconductor material (in particular silicon); and a control region, in the example, a gate region 7, set above the substrate 6 between the drain region 4 and source region 5, and partially overlapping them. The aforesaid regions are coated with a respective silicidation region 8, and contact elements 9 a, 9 b, in particular plugs, made, for example, of tungsten surrounded by a Ti/TiN multilayer, extend vertically with respect to the substrate 6, from the drain region 4 and the source region 5, respectively.
  • As illustrated in detail in FIG. 2, the fuse element 2 has a vertical structure and comprises a bottom electrode 10, made, for example, of tungsten (W), surrounded by first barrier regions 11, for example constituted by a Ti/TiN multilayer. In particular, the bottom electrode 10 is made by an end portion of a contact element 9 a associated to the drain region 4 of the selector element 3, preferably a contact element arranged in a central position with respect to the drain region 4 so that the fuse element 2 is set above the drain region.
  • A heater 12 is placed on, and in contact with, the bottom electrode 10. The heater 12, as may be seen in FIG. 1, extends along the periphery of an approximately rectangular area, and has a first long portion 12 a and a second long portion 12 b, and a first short portion 12 c and a second short portion 12 d, said long portions and short portions being orthogonal to one another. Each of said portions 12 a-12 d (as illustrated for example in the next FIG. 10) has a channel-shaped structure, and is made by a metallic coating, for example of TiSiN, which forms respective side walls and a respective bottom surface, and by a dielectric filling material. Contact between the bottom electrode 10 and the bottom wall of the heater 12 occurs at a central area of the first long portion 12 a of the heater 12. The second long portion 12 b is instead set outside the drain region 5.
  • A phase-change memory element 13 (referred to in what follows as PCM element 13) is set above the heater 12, in particular above the first long portion 12 a thereof, in a position vertically corresponding to the bottom electrode 10. In detail, the PCM element 13 comprises a calcogenic region 15, made of phase-change material, for example GST (Ge2Sb2Te5), and a second barrier region, made, for example, of Ti/TiN, on the calcogenic region 15. In particular, the second barrier region constitutes a top electrode 16 of the fuse element 2. The PCM element 13 extends longitudinally on an approximately rectangular area (approximately parallel to the first and second short portions 12 c, 12 d of the heating element 12) crossing the long portion 12 a of the heating element 12. Moreover, the PCM element 13 is formed (in a known way) with the microtrench technique, and the calcogenic region 15 contacts the walls of the central area of the first long portion 12 a of the heater 12 only at a central depression having a cross section with sublithographic dimensions. The area of contact is a storage area 15 a (and, as will be clarified hereinafter, an electrically breakable area) of the fuse device 1. A closing region 17, made, for example, of silicon nitride, surrounds the PCM element 13 and covers the heater 12 at the top. In addition, an insulation region 19 surrounds and electrically insulates the fuse element 2.
  • In use, via purposely provided electrical contacts (not illustrated), the top electrode 16 is connected to a high-voltage line Vcc, for example to the supply line of the fuse device 1, and the source region 5, via the corresponding contact elements 9 b, is connected to a reference-voltage line GND of the fuse device 1. When enabled by a control signal supplied to the gate region 7, a programming current consequently passes through the fuse element 2 from the top electrode 16 to the bottom electrode 10, traversing the calcogenic region 15 and the storage area 15 a, and then flows through the selector element 3 from the drain region 4 to the source region 5.
  • According to one embodiment of the present invention, the open state of the fuse element 2 is programmed by applying a current and a voltage having a value such as to cause physical breaking of the storage area 15 a. For this purpose, a programming pulse is applied having a duration, for example, of between 100 ns and 1 μs, with a current of, for example, 2.5 mA, and a voltage of, for example, 2.5 V. As illustrated in FIG. 3, said programming pulse causes breaking of the storage area 15 a, and creation of a void 20, which interrupts the electrical connection between the top electrode 16 and the bottom electrode 10 of the fuse element 2 (creating the open state, or high-resistance state). In detail, the void 20 extends in part in the calcogenic region 15 and in part in the heater 12. As illustrated in FIGS. 4 and 5, relating to experimental tests conducted by the applicant with a fuse device 1 built with a 180-nm technology and with programming pulses of 300 ns, breaking of the storage area 15 a is obtained using voltages having a value of between approximately 2 V and 3 V (preferably 2.5 V), and currents having a value of between approximately 2 mA and 3 mA (preferably 2.5 mA).
  • The closed state of the fuse element 2 is instead programmed by applying to the storage area 15 a a triangular voltage pulse (FIG. 6), for example having a duration of 1 μs and an amplitude of 700 μA. Said pulse causes melting of the calcogenic material (at a temperature of approximately 600° C.) and subsequent slow cooling thereof, which leads to its crystallization. Alternatively, a single crystallization pulse can be applied, or else a sequence of pulses having decreasing amplitudes. Typically, the crystallization procedure has a duration of between 1 and 10 μs.
  • Given the high values of current used in the breaking operations of the fuse device 1, one embodiment of the present invention envisages exploitation of the so-called “ballast” effect to prevent the known effects of “crowding” of the current and of thermal “run-away” of the selector element 3. In a per se known manner, the ballast effect leads to a greater uniformity of the current distribution, and occurs as the resistance increases along the path of the current.
  • For the above purpose (see FIG. 7), according to a first variant, the PCM element 13 is arranged above the second long portion 12 b of the heater 12 at a distance from the contact elements 9 a associated to the drain region 4. The electrical contact with the PCM element 13, and in particular with the storage area 15 a, is in any case guaranteed by the presence of metallic material on the side walls and on the bottom surface of the heater 12, and by its continuity. However, advantageously, the heating element represents a series resistance to the passage of the programming current.
  • According to a further variant (illustrated in FIG. 8), the series resistance in the path of the programming current, and hence the aforesaid ballast effect, can be further increased by removing the silicidation regions 8 on the source and drain regions (thus creating an additional series resistance on both the source and drain contacts), and possibly moving the contact elements 9 a of the drain region 4 away from the gate region 7 (as indicated by the arrow in the figure).
  • In any case, the configuration of the fuse device 1 previously described envisages the passage of the programming current in the fuse element 2 from the top electrode 16 to the bottom one 10. Experimental tests conducted by the applicant have, however, demonstrated an even better repeatability of the programming operations of the fuse element when the direction of the flow of the programming current is reversed. For this purpose, according to further embodiments of the present invention, alternative configurations of the fuse device 1 are proposed, which share the feature of envisaging a flow of the programming current from the bottom electrode 10 to the top electrode 16 of the fuse element 2.
  • A second embodiment, illustrated in FIGS. 9 and 10, envisages again the use of a selector element 3 of the planar N-channel MOSFET type, but in this case the bottom electrode 10 of the fuse element 2 is connected to the source region 5 of the selector element 3.
  • In detail, the selector element 3 has an active area 22, having P-type conductivity, made within the substrate 6 (having a P-doping) and isolated by means of isolation trenches 23, for example using the Shallow-Trench Isolation (STI) technique. The drain region 4 and the source region 5 are provided within the active area 22; in detail, the drain region 4 comprises a first drain strip 4 a and a second drain strip 4 b, which extend in a first direction x parallel to one another, and the source region 5 comprises a source strip extending in the first direction x between the drain strips 4 a, 4 b. In addition, electrical contacts 24 (illustrated in FIG. 9) contact the drain strips 4 a, 4 b. The gate region 7 is constituted by a polysilicon rectangular ring structure, which has long portions set between the drain region and the source region, and short portions, which extend in a second direction y, orthogonal to the first direction x, and are set outside the active area 22, where they are contacted by electrical gate contacts. In addition to the fuse element 2, the fuse device 1 comprises two pairs of “dummy” elements 25, arranged laterally to the fuse element 2. Each “dummy” element has the same structure as the fuse element 2, but is not electrically connected and is hence not crossed by current during the programming steps. The presence of the dummy elements 25, however, enables uniform operation of the fuse element 2.
  • With reference in particular to FIG. 10, a contact element 9 a, associated to the drain region 4, for example a line of tungsten extending in the first direction x, is electrically connected, via the electrical contacts 24, to the high-voltage line Vcc (in a way not illustrated), while a contact element 9 b, similar to the contact element 9 a and associated to the source region 5, is connected to the heater 12 of the fuse element 2 (thus constituting its bottom electrode 10). In particular, the heater 12 has a rectangular shape, contained in the direction y by the long portions of the gate region 7, and is again constituted by a metallic coating 26, for example of TiSiN, forming respective side walls and a respective bottom surface, and by a dielectric filling material 27. The PCM element 13 is set above the heater 12, and has a rectangular shape extending in the second direction y, starting from a central area of the heater 12 towards the second drain strip 4 b, overstepping the gate region 7. Contact plugs (so-called “vias 0”) 28 electrically connect the top electrode 16 to a first metallization 29 (level-1 metal) that runs in the second direction y over the entire active area 22. The first metallization 29 is also connected to the reference-voltage line GND of the fuse device 1.
  • In use, the programming current flows from the supply line Vcc to the drain region 4, and then to the source region 5. From the source region 5 it flows to the bottom electrode 10, and then through the PCM element 13 (and in particular the storage area 15 a) to the top electrode 16, up to the reference-voltage line GND. In particular, the bottom electrode 10 is set at a potential higher than that of the top electrode 16, and, as desired, the current flows from the bottom electrode to the top one.
  • Said arrangement is therefore advantageous for improving the repeatability of the programming operations, but feels, however, the body effect occurring in the N-channel MOSFET, due to the voltage increase of the source region 5.
  • To solve the above problem, a third embodiment (FIGS. 11-12), envisages a configuration substantially similar to the one described with reference to FIGS. 9-10, with the difference that a P-channel planar MOSFET is used for the selector element 3. In this case, the active area is constituted by a well 30 of N type within a substrate of P type, and the drain region 4 and source region 5 are also doped with a P-type doping. Said solution has the advantage of not feeling the body effect; however, as is known, the use of P-channel transistors, given the same area occupation, entails the generation of currents of lower value as compared to the use of N-channel transistors.
  • A fourth embodiment (illustrated in FIGS. 13-14) envisages again the use of a selector element 3 of an N-channel MOSFET type, and at the same time enables elimination of the body effect.
  • In detail, the drain region 4 and the source region 5 are in this case constituted by respective strips extending in the first direction x, and the gate region 7 is also constituted by a strip, which is set between the source and drain regions and carries respective gate contacts at its ends, outside the active area 22.
  • As illustrated in detail in FIG. 14, a contact element 9 b associated to the source region 5 is connected, via a first plug 32, for example made of tungsten surrounded by a Ti/TiN multilayer, to a first metallization 29, connected in turn to the reference-voltage line GND. A contact element 9 a associated to the drain region 4 is instead connected, via a second plug 34, to a second metallization 35 (constituting an internal node). The second metallization 35 extends in the first direction x, until it reaches the top electrode 16 of the fuse element 2, to which it is connected via a third plug 36 (so-called “via 0”). The bottom electrode of the fuse element 2 is instead connected to a connection line 38, for example made of tungsten, provided above the substrate 6, in a position corresponding to an isolation trench 23. A fourth plug 39 connects the connection line 38 (which also extends in the first direction x) to a third metallization 40, connected to the high-voltage line Vcc.
  • In use, the programming current flows from the supply line Vcc to the connection line 38 (the bottom electrode of the fuse element), then through the PCM element 13 (and in particular the storage area 15 a) and the top electrode 16; from this it flows through the second metallization 35 to the drain region 4, then to the source region 5, and finally to the reference-voltage line GND. In particular, also in this case, the current flows advantageously from the bottom electrode 10 to the top electrode 16.
  • According to said configuration, the fuse element 2 is not vertically aligned to one of the current-conduction regions of the selector element 3, as in the preceding solutions, but is shifted laterally (in the second direction y). Said configuration consequently entails a greater area occupation as compared to the preceding solutions. At the same time, it does not feel the body effect, in so far as the source region 5 is connected to the reference-voltage line GND.
  • As illustrated in FIG. 15, the fuse device 1 can advantageously be used as a memory element of a one-time-programmable ROM storage device 50. In particular, the ROM storage device 50 comprises a bank of programmable fuses 52 comprising a plurality of fuse devices (each made as described previously), and a purposely provided programming circuit 54, coupled to the bank of programmable fuses 52 to carry out programming thereof.
  • The advantages of the fuse device and of the corresponding programming method are clear from the foregoing description.
  • In any case, it is emphasized that the fuse device has reduced costs and area occupation, and small programming times (less than 10 μs, if both “0” and “1” data are programmed; less than 100 ns if only the “0” datum is programmed, as described hereinafter). Furthermore, it does not require either additional process steps with respect to the classic steps of the semiconductor industry (as, instead, is required for example by the laser-programmed fuses), or thick oxide layers (as, instead, is required by the E2PROMs). The described structures also have a vertical structure, and a small overall encumbrance.
  • The electrical alteration of the fuse device is highly repeatable, thanks to the fact that the area of contact between the PCM element and the heater has small (i.e., sublithographic) dimensions, which are controllable with extreme precision. Said repeatability is further increased in the arrangements envisaging a flow of current in the fuse element 2 from the bottom electrode 10 to the top electrode 16.
  • Amongst the various embodiments described, particularly advantageous is the one that envisages the use of a P-channel selector transistor.
  • Furthermore, tests conducted by the applicant have demonstrated the capability of the fuse device to maintain the programmed data, even after baking at 250° C. for 24 hours.
  • In addition, it is reasonable to expect that the breaking currents and voltages will follow the same scaling law as PCM memory cells (described, for example, in “Scaling Analysis of Phase-Change Memory Technology”, Pirovano et al., IEDM Tech. Dig., pp. 699-702, 2003). In particular, the breaking voltage will remain practically constant, whilst the programming current will decrease linearly as the scale of integration used in the manufacturing process decreases. Advantageously, this will enable fuse devices (inclusive of the fuse element and the corresponding selector element) to be made that are increasingly compact with scaling-down of the technology used.
  • Finally, it is clear that modifications and variations can be made to what is described and illustrated herein, without thereby departing from the scope of the present invention, as defined in the annexed claims.
  • In particular, the programming of the closed state (corresponding to the “1” value) is not strictly necessary in so far as, as is known, storage elements made of virgin calcogenic material are already crystalline (low-resistivity state), and remain crystalline even after operations such as on-board packaging and soldering (consequently, the information associated to the crystalline state is stable). However, it may be advantageous to program, as described previously, also the closed state, to obtain higher values of conductivity (and so facilitate the operations of reading, for example using sense amplifiers).
  • Finally, it is emphasized that programming of the fuse element 2 can be achieved via selector elements different from the ones illustrated (for example using BJTs).
  • All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.

Claims (31)

1. A fuse device, comprising:
a fuse element having a first terminal; a second terminal; a phase-change region, including an electrically breakable region of phase-change material configured to undergo breaking as a result of the supply of a programming electrical quantity; and a heating element of conductive material in contact with said first terminal, said electrically breakable region being arranged at a contact area between said heating element and said phase-change region; and
a selector element electrically connected to said fuse element and configured to enable the supply of said programming electrical quantity to said fuse element.
2. The fuse device according to claim 1, wherein said phase-change material is a calcogenic material, in particular GST.
3. The fuse device according to claim 1, wherein said contact area is at a bottom side of the phase-change region and the second terminal contacts a top side of the phase-change region, the fuse device further comprising an electrical connection element connecting the selector element to the phase-change region via the second terminal.
4. The fuse device according to claim 1, wherein said selector element is a transistor element having a current input terminal and a current output terminal.
5. The fuse device according to claim 4, wherein said selector element is configured to enable supply to said electrically breakable region of a programming pulse with a current comprised between 2 mA and 3 mA, a voltage comprised between 2 V and 3 V, and a duration comprised between 100 ns and 1 μs.
6. The fuse device according to claim 4, wherein said heating element has a rectangular ring shape having a first long side and a second long side including conductive material, said first long side being arranged above said selector element and said second long side being spaced apart from said selector element; and wherein said electrically breakable region is in contact with said second long side, and said current input terminal is connected to said first long side.
7. The fuse device according to claim 4, wherein said first terminal is connected to said current output terminal, said second terminal is connected to a first line set at a first potential, and said current input terminal is connected to a second line set at a second potential, higher than said first potential.
8. The fuse device according to claim 7, wherein said selector element is a P-channel planar MOSFET.
9. The fuse device according to claim 4, wherein said current input terminal is connected to said second terminal, said current output terminal is connected to a first line set at a first potential, and said first terminal is connected to a second line set at a second potential, higher than said first potential.
10. The fuse device according to claim 9, wherein said selector element is formed in a substrate of semiconductor material, and said first terminal is in contact with a first connection line provided above said substrate, the fuse device further comprising: first contact elements connecting said current input terminal to a second connection line of conductive material; second contact elements connecting said second connection line to said second terminal; and third contact elements connecting said first connection line to said second line.
11. The fuse device according to claim 1, wherein said fuse element has a vertical structure, and said electrically breakable region has a cross section with sublithographic dimensions.
12. The fuse device according to claim 1, wherein, in at least one operating condition, said first terminal has a voltage higher than a voltage of said second terminal, and said programming electrical quantity comprises a programming current flowing from said first terminal to said second terminal.
13. The fuse device according to claim 1, wherein the contact area is laterally spaced apart from the selector element.
14. The fuse device according to claim 1, wherein the heater element is a vertically-arranged thin film of conductive material that contacts the phase-change region at the contact area, which has a sublithographic dimension.
15. A one-time-programmable storage device, comprising
a plurality of fuse devices, each fuse device including:
a fuse element having a first terminal; a second terminal; a phase-change region, including an electrically breakable region of phase-change material configured to undergo breaking as a result of the supply of a programming electrical quantity; and a heating element of conductive material in contact with said first terminal, said electrically breakable region being arranged at a contact area between said heating element and said phase-change region; and
a selector element electrically connected to said fuse element and configured to enable the supply of said programming electrical quantity to said fuse element.
16. The storage device according to claim 15, further comprising a programming circuit configured to supply to at least one of said fuse devices said programming electrical quantity.
17. The storage device according to claim 15, wherein said contact area is at a bottom side of the phase-change region and the second terminal contacts a top side of the phase-change region, the fuse device further comprising an electrical connection element connecting the selector element to the phase-change region via the second terminal.
18. The storage device according to claim 15, wherein said selector element is configured to enable supply to said electrically breakable region of a programming pulse with a current comprised between 2 mA and 3 mA, a voltage comprised between 2 V and 3 V, and a duration comprised between 100 ns and 1 μs.
19. The storage device according to claim 15, wherein said selector element is a transistor element having a current input terminal and a current output terminal, and wherein said heating element has a rectangular ring shape having a first long side and a second long side including conductive material, said first long side being arranged above said selector element and said second long side being spaced apart from said selector element; and wherein said electrically breakable region is in contact with said second long side, and said current input terminal is connected to said first long side.
20. The storage device according to claim 15, wherein said selector element is a P-channel planar MOSFET.
21. The storage device according to claim 15, wherein said selector element is a transistor element having a current input terminal and a current output terminal, and wherein said selector element is formed in a substrate of semiconductor material, and said first terminal is in contact with a first connection line provided above said substrate, the fuse device further comprising: first contact elements connecting said current input terminal to a second connection line of conductive material; second contact elements connecting said second connection line to said second terminal; and third contact elements connecting said first connection line to said second line.
22. The storage device according to claim 15, wherein said fuse element has a vertical structure, and said electrically breakable region has a cross section with sublithographic dimensions.
23. The storage device according to claim 15, wherein the contact area is laterally spaced apart from the selector element.
24. A method for programming a fuse device provided with a fuse element having a first terminal; a second terminal; a phase-change region, including an electrically breakable region of phase-change material arranged between said first and second terminals; and a heating element of conductive material in contact with said first terminal, said electrically breakable region being arranged at a contact area between said heating element and said phase-change region, the method comprising breaking said electrically breakable region, wherein breaking said electrically breakable region comprises supplying to said phase-change material a programming electrical quantity such as to cause breaking thereof, wherein supplying the programming electrical quantity comprises supplying a programming current flowing between said first terminal and said second terminal so as to form a void in said electrically breakable region.
25. The method according to claim 24, wherein supplying the programming electrical quantity comprises supplying to said electrically breakable region a programming pulse with a current comprised between 2 A and 3 A, a voltage comprised between 2 V and 3 V, and a duration comprised between 100 ns and 1 μs.
26. The method according to claim 24, wherein supplying a programming electrical quantity comprises supplying a programming current flowing from said first terminal to said second terminal so as to form the void in said electrically breakable region.
27. The method according to claim 24, further comprising programming said electrically breakable region in a first low-resistivity operating condition, so as to electrically connect said first and second terminals, and programming said electrically breakable region in a second high-resistivity operating condition, so as to electrically disconnect said first terminal from said second terminal; programming in said second high-resistivity operating condition comprising said step of breaking said electrically breakable region.
28. A process for manufacturing a fuse device, comprising:
forming a fuse element using steps including:
forming a first terminal and a second terminal; and
forming an electrically breakable region between said first terminal and said second terminal, wherein forming the electrically breakable region comprises forming a region of phase-change material; and
forming a heating element of conductive material in contact with said first terminal, said electrically breakable region being arranged at a contact area between said heating element and said electrically breakable region; and
forming a selector element electrically connected to said fuse element and configured to enable the supply of said programming electrical quantity to said fuse element.
29. The process according to claim 28, wherein said contact area is at a bottom side of the phase-change region and the second terminal contacts a top side of the phase-change region, the process further comprising forming an electrical connection element connecting the selector element to the phase-change region via the second terminal.
30. The process according to claim 28, wherein said selector element is a transistor element having a current input terminal and a current output terminal, and wherein said heating element has a rectangular ring shape having a first long side and a second long side including conductive material, the process further comprising arranging said first long side above said selector element and spacing apart said second long side from said selector element; and wherein said electrically breakable region is in contact with said second long side, and said current input terminal is connected to said first long side.
31. The process according to claim 28, wherein the contact area is laterally spaced apart from the selector element.
US11/625,178 2006-01-20 2007-01-19 Electrical fuse device based on a phase-change memory element and corresponding programming method Abandoned US20070189053A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06425025.1 2006-01-20
EP20060425025 EP1811564B1 (en) 2006-01-20 2006-01-20 Electrical fuse device based on a phase-change memory element and corresponding programming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/212,080 US8410527B2 (en) 2006-01-20 2011-08-17 Electrical fuse device based on a phase-change memory element and corresponding programming method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/212,080 Division US8410527B2 (en) 2006-01-20 2011-08-17 Electrical fuse device based on a phase-change memory element and corresponding programming method

Publications (1)

Publication Number Publication Date
US20070189053A1 true US20070189053A1 (en) 2007-08-16

Family

ID=36581783

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/625,178 Abandoned US20070189053A1 (en) 2006-01-20 2007-01-19 Electrical fuse device based on a phase-change memory element and corresponding programming method
US13/212,080 Active US8410527B2 (en) 2006-01-20 2011-08-17 Electrical fuse device based on a phase-change memory element and corresponding programming method

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/212,080 Active US8410527B2 (en) 2006-01-20 2011-08-17 Electrical fuse device based on a phase-change memory element and corresponding programming method

Country Status (3)

Country Link
US (2) US20070189053A1 (en)
EP (1) EP1811564B1 (en)
DE (1) DE602006012793D1 (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090008636A1 (en) * 2007-07-04 2009-01-08 Byung-Ho Lee Semiconductor device and method for fabricating the same
US20090196113A1 (en) * 2008-02-01 2009-08-06 You-Chul Jeong Fuse circuit and semiconductor memory device including the same
US20100073122A1 (en) * 2008-09-17 2010-03-25 Stmicroelectronics, Inc. Dual thin film precision resistance trimming
US20100072453A1 (en) * 2008-07-23 2010-03-25 Hong-Sik Jeong Phase-Changeable Fuse Elements and Memory Devices Containing Phase-Changeable Fuse Elements and Memory Cells Therein
US20130049168A1 (en) * 2011-08-23 2013-02-28 Jie-Ning Yang Resistor and manufacturing method thereof
US8400257B2 (en) 2010-08-24 2013-03-19 Stmicroelectronics Pte Ltd Via-less thin film resistor with a dielectric cap
US8436426B2 (en) 2010-08-24 2013-05-07 Stmicroelectronics Pte Ltd. Multi-layer via-less thin film resistor
US8558654B2 (en) 2008-09-17 2013-10-15 Stmicroelectronics (Grenoble 2) Sas Vialess integration for dual thin films—thin film resistor and heater
US8569734B2 (en) 2010-08-04 2013-10-29 Micron Technology, Inc. Forming resistive random access memories together with fuse arrays
US20130286711A1 (en) * 2012-04-27 2013-10-31 Macronix International Co., Ltd. Blocking current leakage in a memory array
DE102012210124A1 (en) * 2012-06-15 2013-12-19 Robert Bosch Gmbh Composite component and method for producing a composite component
US8659085B2 (en) 2010-08-24 2014-02-25 Stmicroelectronics Pte Ltd. Lateral connection for a via-less thin film resistor
US8786396B2 (en) 2008-09-17 2014-07-22 Stmicroelectronics Pte. Ltd. Heater design for heat-trimmed thin film resistors
US8809861B2 (en) 2010-12-29 2014-08-19 Stmicroelectronics Pte Ltd. Thin film metal-dielectric-metal transistor
US8885390B2 (en) 2011-11-15 2014-11-11 Stmicroelectronics Pte Ltd Resistor thin film MTP memory
US8927909B2 (en) 2010-10-11 2015-01-06 Stmicroelectronics, Inc. Closed loop temperature controlled circuit to improve device stability
US9129964B2 (en) 2013-04-26 2015-09-08 International Business Machines Corporation Programmable electrical fuse
US9159413B2 (en) 2010-12-29 2015-10-13 Stmicroelectronics Pte Ltd. Thermo programmable resistor based ROM

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2045814A1 (en) * 2007-10-03 2009-04-08 STMicroelectronics S.r.l. Method and device for irreversibly programming and reading nonvolatile memory cells
US8923666B2 (en) 2012-05-16 2014-12-30 International Business Machines Corporation Electrically controlled optical fuse and method of fabrication
US9793378B2 (en) 2013-05-31 2017-10-17 Stmicroelectronics, Inc. Fin field effect transistor device with reduced overlap capacitance and enhanced mechanical stability
US9337143B2 (en) 2014-01-27 2016-05-10 Globalfoundries Inc. E-fuse structure with methods of fusing the same and monitoring material leakage
US9263218B2 (en) 2014-05-23 2016-02-16 Nuvoton Technology Corporation Variable resistance memory cell based electrically resettable fuse device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337507B1 (en) * 1995-09-29 2002-01-08 Intel Corporation Silicide agglomeration fuse device with notches to enhance programmability
US6448576B1 (en) * 2001-08-30 2002-09-10 Bae Systems Information And Electronic Systems Integration, Inc. Programmable chalcogenide fuse within a semiconductor device
US6579760B1 (en) * 2002-03-28 2003-06-17 Macronix International Co., Ltd. Self-aligned, programmable phase change memory
US20030209746A1 (en) * 2002-05-07 2003-11-13 Hideki Horii Integrated circuit memory devices having memory cells therein that utilize phase-change materials to support non-volatile data retention and methods of forming same
US20030218492A1 (en) * 2002-05-24 2003-11-27 Intel Corporation Static, low-voltage fuse-based cell with high-voltage programming
US20040057271A1 (en) * 2002-09-25 2004-03-25 Ward Parkinson Method of operating programmable resistant element
US6816404B2 (en) * 2001-12-27 2004-11-09 Stmicroelectronics S.R.L. Architecture of a phase-change nonvolatile memory array
US6891747B2 (en) * 2002-02-20 2005-05-10 Stmicroelectronics S.R.L. Phase change memory cell and manufacturing method thereof using minitrenches
US20050185444A1 (en) * 2004-02-25 2005-08-25 Soo-Guil Yang Phase-changeable memory device and method of manufacturing the same
US20070051936A1 (en) * 2005-04-08 2007-03-08 Stmicroelectronics S.R.I. Phase change memory cell with tubular heater and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6545903B1 (en) * 2001-12-17 2003-04-08 Texas Instruments Incorporated Self-aligned resistive plugs for forming memory cell with phase change material
US6744088B1 (en) * 2002-12-13 2004-06-01 Intel Corporation Phase change memory device on a planar composite layer
US20060056227A1 (en) * 2004-09-10 2006-03-16 Parkinson Ward D One time programmable phase change memory

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337507B1 (en) * 1995-09-29 2002-01-08 Intel Corporation Silicide agglomeration fuse device with notches to enhance programmability
US6448576B1 (en) * 2001-08-30 2002-09-10 Bae Systems Information And Electronic Systems Integration, Inc. Programmable chalcogenide fuse within a semiconductor device
US6816404B2 (en) * 2001-12-27 2004-11-09 Stmicroelectronics S.R.L. Architecture of a phase-change nonvolatile memory array
US6891747B2 (en) * 2002-02-20 2005-05-10 Stmicroelectronics S.R.L. Phase change memory cell and manufacturing method thereof using minitrenches
US6579760B1 (en) * 2002-03-28 2003-06-17 Macronix International Co., Ltd. Self-aligned, programmable phase change memory
US20030209746A1 (en) * 2002-05-07 2003-11-13 Hideki Horii Integrated circuit memory devices having memory cells therein that utilize phase-change materials to support non-volatile data retention and methods of forming same
US20030218492A1 (en) * 2002-05-24 2003-11-27 Intel Corporation Static, low-voltage fuse-based cell with high-voltage programming
US20040057271A1 (en) * 2002-09-25 2004-03-25 Ward Parkinson Method of operating programmable resistant element
US20050185444A1 (en) * 2004-02-25 2005-08-25 Soo-Guil Yang Phase-changeable memory device and method of manufacturing the same
US20070051936A1 (en) * 2005-04-08 2007-03-08 Stmicroelectronics S.R.I. Phase change memory cell with tubular heater and manufacturing method thereof

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7867804B2 (en) * 2007-07-04 2011-01-11 Dongbu Hitek Co., Ltd. Semiconductor device and method for fabricating the same
US20090008636A1 (en) * 2007-07-04 2009-01-08 Byung-Ho Lee Semiconductor device and method for fabricating the same
US20090196113A1 (en) * 2008-02-01 2009-08-06 You-Chul Jeong Fuse circuit and semiconductor memory device including the same
US7978549B2 (en) * 2008-02-01 2011-07-12 Samsung Electronics Co., Ltd. Fuse circuit and semiconductor memory device including the same
US8305822B2 (en) 2008-02-01 2012-11-06 Samsung Electronics Co., Ltd. Fuse circuit and semiconductor memory device including the same
US20100072453A1 (en) * 2008-07-23 2010-03-25 Hong-Sik Jeong Phase-Changeable Fuse Elements and Memory Devices Containing Phase-Changeable Fuse Elements and Memory Cells Therein
US8242876B2 (en) 2008-09-17 2012-08-14 Stmicroelectronics, Inc. Dual thin film precision resistance trimming
US20100073122A1 (en) * 2008-09-17 2010-03-25 Stmicroelectronics, Inc. Dual thin film precision resistance trimming
US8786396B2 (en) 2008-09-17 2014-07-22 Stmicroelectronics Pte. Ltd. Heater design for heat-trimmed thin film resistors
US8493171B2 (en) 2008-09-17 2013-07-23 Stmicroelectronics, Inc. Dual thin film precision resistance trimming
US8558654B2 (en) 2008-09-17 2013-10-15 Stmicroelectronics (Grenoble 2) Sas Vialess integration for dual thin films—thin film resistor and heater
US9735354B2 (en) 2010-08-04 2017-08-15 Micron Technology, Inc. Forming resistive random access memories together with fuse arrays
US9136471B2 (en) 2010-08-04 2015-09-15 Micron Technology, Inc. Forming resistive random access memories together with fuse arrays
US8569734B2 (en) 2010-08-04 2013-10-29 Micron Technology, Inc. Forming resistive random access memories together with fuse arrays
US9356237B2 (en) 2010-08-04 2016-05-31 Micron Technology, Inc. Forming resistive random access memories together with fuse arrays
US8436426B2 (en) 2010-08-24 2013-05-07 Stmicroelectronics Pte Ltd. Multi-layer via-less thin film resistor
US8659085B2 (en) 2010-08-24 2014-02-25 Stmicroelectronics Pte Ltd. Lateral connection for a via-less thin film resistor
US8400257B2 (en) 2010-08-24 2013-03-19 Stmicroelectronics Pte Ltd Via-less thin film resistor with a dielectric cap
US9165853B2 (en) 2010-10-11 2015-10-20 Stmicroelectronics Asia Pacific Pte. Ltd. Closed loop temperature controlled circuit to improve device stability
US8927909B2 (en) 2010-10-11 2015-01-06 Stmicroelectronics, Inc. Closed loop temperature controlled circuit to improve device stability
US10206247B2 (en) 2010-10-11 2019-02-12 Stmicroelectronics, Inc. Closed loop temperature controlled circuit to improve device stability
US9159413B2 (en) 2010-12-29 2015-10-13 Stmicroelectronics Pte Ltd. Thermo programmable resistor based ROM
US8809861B2 (en) 2010-12-29 2014-08-19 Stmicroelectronics Pte Ltd. Thin film metal-dielectric-metal transistor
US8981527B2 (en) * 2011-08-23 2015-03-17 United Microelectronics Corp. Resistor and manufacturing method thereof
US20130049168A1 (en) * 2011-08-23 2013-02-28 Jie-Ning Yang Resistor and manufacturing method thereof
US8885390B2 (en) 2011-11-15 2014-11-11 Stmicroelectronics Pte Ltd Resistor thin film MTP memory
US20130286711A1 (en) * 2012-04-27 2013-10-31 Macronix International Co., Ltd. Blocking current leakage in a memory array
US9001550B2 (en) * 2012-04-27 2015-04-07 Macronix International Co., Ltd. Blocking current leakage in a memory array
DE102012210124A1 (en) * 2012-06-15 2013-12-19 Robert Bosch Gmbh Composite component and method for producing a composite component
US9129964B2 (en) 2013-04-26 2015-09-08 International Business Machines Corporation Programmable electrical fuse

Also Published As

Publication number Publication date
US8410527B2 (en) 2013-04-02
EP1811564B1 (en) 2010-03-10
DE602006012793D1 (en) 2010-04-22
EP1811564A1 (en) 2007-07-25
US20110298087A1 (en) 2011-12-08

Similar Documents

Publication Publication Date Title
EP0323078B1 (en) Electrically-programmable low-impedance anti-fuse element
US8129706B2 (en) Structures and methods of a bistable resistive random access memory
US7423300B2 (en) Single-mask phase change memory element
US7993957B2 (en) Phase change memory cell and manufacturing method thereof using minitrenches
US5391518A (en) Method of making a field programmable read only memory (ROM) cell using an amorphous silicon fuse with buried contact polysilicon and metal electrodes
US6894305B2 (en) Phase-change memory devices with a self-heater structure
US6914255B2 (en) Phase change access device for memories
US7910910B2 (en) Phase-change memory cell and method of fabricating the phase-change memory cell
US7183141B1 (en) Reversible field-programmable electric interconnects
US9406349B2 (en) Memory elements and cross point switches and arrays for same using nonvolatile nanotube blocks
US7514362B2 (en) Integrated circuit including sub-lithographic structures
EP1820226B1 (en) Dielectric antifuse for electro-thermally programmable device
CN100456512C (en) Phase change memory devices with contact surface area to a phase changeable material defined by a sidewall of an electrode hole and methods of forming the same
US7161167B2 (en) Lateral phase change memory
US7728318B2 (en) Nonvolatile phase change memory cell having a reduced contact area
US20070274121A1 (en) Multi-level memory cell having phase change element and asymmetrical thermal boundary
US7601995B2 (en) Integrated circuit having resistive memory cells
US6816404B2 (en) Architecture of a phase-change nonvolatile memory array
US7956358B2 (en) I-shaped phase change memory cell with thermal isolation
US20050122771A1 (en) Memory device and method of operating same
EP2509076B1 (en) Electronic device such as a selector
KR100944354B1 (en) Phase change memory cell and method of formation
DE60224622T2 (en) One-time programmable memory
US8105886B2 (en) Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same
US20030062595A1 (en) One time programmable fuse/anti-fuse combination based memory cell

Legal Events

Date Code Title Description
AS Assignment

Owner name: STMICROELECTRONICS S.R.L., ITALY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PELLIZZER, FABIO;TORTORELLI, INNOCENZO;PIROVANO, AGOSTINO;AND OTHERS;REEL/FRAME:019153/0946

Effective date: 20070205

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION