JP2004529500A5 - - Google Patents

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Publication number
JP2004529500A5
JP2004529500A5 JP2003500974A JP2003500974A JP2004529500A5 JP 2004529500 A5 JP2004529500 A5 JP 2004529500A5 JP 2003500974 A JP2003500974 A JP 2003500974A JP 2003500974 A JP2003500974 A JP 2003500974A JP 2004529500 A5 JP2004529500 A5 JP 2004529500A5
Authority
JP
Japan
Prior art keywords
bit line
memory cell
providing
conductive material
cell array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003500974A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004529500A (ja
Filing date
Publication date
Priority claimed from EP01113178A external-priority patent/EP1263050A1/en
Priority claimed from EP01113179A external-priority patent/EP1263051A1/en
Application filed filed Critical
Priority claimed from PCT/EP2002/005805 external-priority patent/WO2002097890A2/en
Publication of JP2004529500A publication Critical patent/JP2004529500A/ja
Publication of JP2004529500A5 publication Critical patent/JP2004529500A5/ja
Pending legal-status Critical Current

Links

JP2003500974A 2001-05-30 2002-05-27 メモリセルアレイ内のビットラインコンタクト Pending JP2004529500A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP01113178A EP1263050A1 (en) 2001-05-30 2001-05-30 Bitline contacts in a memory cell array
EP01113179A EP1263051A1 (en) 2001-05-30 2001-05-30 Bitline contacts in a memory cell array
PCT/EP2002/005805 WO2002097890A2 (en) 2001-05-30 2002-05-27 Bitline contacts in a memory cell array

Publications (2)

Publication Number Publication Date
JP2004529500A JP2004529500A (ja) 2004-09-24
JP2004529500A5 true JP2004529500A5 (enExample) 2005-07-21

Family

ID=26076602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003500974A Pending JP2004529500A (ja) 2001-05-30 2002-05-27 メモリセルアレイ内のビットラインコンタクト

Country Status (6)

Country Link
US (1) US7008849B2 (enExample)
EP (1) EP1390981A2 (enExample)
JP (1) JP2004529500A (enExample)
IL (1) IL159112A0 (enExample)
TW (1) TW556326B (enExample)
WO (1) WO2002097890A2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6794764B1 (en) * 2003-03-05 2004-09-21 Advanced Micro Devices, Inc. Charge-trapping memory arrays resistant to damage from contact hole information
JPWO2007000808A1 (ja) * 2005-06-28 2009-01-22 スパンション エルエルシー 半導体装置およびその製造方法
US7977218B2 (en) * 2006-12-26 2011-07-12 Spansion Llc Thin oxide dummy tiling as charge protection
US11631680B2 (en) 2018-10-18 2023-04-18 Applied Materials, Inc. Methods and apparatus for smoothing dynamic random access memory bit line metal
US10700072B2 (en) 2018-10-18 2020-06-30 Applied Materials, Inc. Cap layer for bit line resistance reduction
US10903112B2 (en) 2018-10-18 2021-01-26 Applied Materials, Inc. Methods and apparatus for smoothing dynamic random access memory bit line metal

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4390971A (en) * 1978-03-20 1983-06-28 Texas Instruments Incorporated Post-metal programmable MOS read only memory
US5168334A (en) * 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
US5308777A (en) * 1993-07-28 1994-05-03 United Microelectronics Corporation Mask ROM process
JPH07307388A (ja) * 1994-02-04 1995-11-21 Advanced Micro Devices Inc トランジスタのアレイおよびその形成方法
US5455535A (en) * 1994-03-03 1995-10-03 National Semiconductor Corporation Rail to rail operational amplifier intermediate stage
US5471416A (en) * 1994-11-14 1995-11-28 National Semiconductor Corporation Method of programming a CMOS read only memory at the second metal layer in a two-metal process
US5815433A (en) * 1994-12-27 1998-09-29 Nkk Corporation Mask ROM device with gate insulation film based in pad oxide film and/or nitride film
GB2298739B (en) * 1995-03-07 1999-02-17 Hyundai Electronics Ind Method of making a mask ROM
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
JP3420694B2 (ja) * 1996-12-27 2003-06-30 株式会社東芝 スタンダードセル方式の集積回路
DE69636738D1 (de) * 1996-12-27 2007-01-11 St Microelectronics Srl Kontaktstruktur für elektronische EPROM oder flash EPROM Halbleiterschaltungen und ihr Herstellungsverfahren
US5915203A (en) * 1997-06-10 1999-06-22 Vlsi Technology, Inc. Method for producing deep submicron interconnect vias
US5966603A (en) * 1997-06-11 1999-10-12 Saifun Semiconductors Ltd. NROM fabrication method with a periphery portion
US5963465A (en) * 1997-12-12 1999-10-05 Saifun Semiconductors, Ltd. Symmetric segmented memory array architecture
US6133095A (en) * 1999-02-04 2000-10-17 Saifun Semiconductors Ltd. Method for creating diffusion areas for sources and drains without an etch step
KR20010018728A (ko) * 1999-08-21 2001-03-15 김영환 마스크 롬의 제조 방법
US6124192A (en) * 1999-09-27 2000-09-26 Vanguard International Semicondutor Corporation Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs

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