JP2004529500A - メモリセルアレイ内のビットラインコンタクト - Google Patents

メモリセルアレイ内のビットラインコンタクト Download PDF

Info

Publication number
JP2004529500A
JP2004529500A JP2003500974A JP2003500974A JP2004529500A JP 2004529500 A JP2004529500 A JP 2004529500A JP 2003500974 A JP2003500974 A JP 2003500974A JP 2003500974 A JP2003500974 A JP 2003500974A JP 2004529500 A JP2004529500 A JP 2004529500A
Authority
JP
Japan
Prior art keywords
bit line
memory cell
cell array
conductive material
providing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003500974A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004529500A5 (enExample
Inventor
グリート シュヴーベ，
カエ−ホーン ワン，
クラウス フェルトナー，
フォン カミーンスキ エラルト シュタイン
Original Assignee
インフィネオン テクノロジーズ アクチェンゲゼルシャフト
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP01113178A external-priority patent/EP1263050A1/en
Priority claimed from EP01113179A external-priority patent/EP1263051A1/en
Application filed by インフィネオン テクノロジーズ アクチェンゲゼルシャフト filed Critical インフィネオン テクノロジーズ アクチェンゲゼルシャフト
Publication of JP2004529500A publication Critical patent/JP2004529500A/ja
Publication of JP2004529500A5 publication Critical patent/JP2004529500A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2003500974A 2001-05-30 2002-05-27 メモリセルアレイ内のビットラインコンタクト Pending JP2004529500A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP01113178A EP1263050A1 (en) 2001-05-30 2001-05-30 Bitline contacts in a memory cell array
EP01113179A EP1263051A1 (en) 2001-05-30 2001-05-30 Bitline contacts in a memory cell array
PCT/EP2002/005805 WO2002097890A2 (en) 2001-05-30 2002-05-27 Bitline contacts in a memory cell array

Publications (2)

Publication Number Publication Date
JP2004529500A true JP2004529500A (ja) 2004-09-24
JP2004529500A5 JP2004529500A5 (enExample) 2005-07-21

Family

ID=26076602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003500974A Pending JP2004529500A (ja) 2001-05-30 2002-05-27 メモリセルアレイ内のビットラインコンタクト

Country Status (6)

Country Link
US (1) US7008849B2 (enExample)
EP (1) EP1390981A2 (enExample)
JP (1) JP2004529500A (enExample)
IL (1) IL159112A0 (enExample)
TW (1) TW556326B (enExample)
WO (1) WO2002097890A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2007000808A1 (ja) * 2005-06-28 2009-01-22 スパンション エルエルシー 半導体装置およびその製造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6794764B1 (en) * 2003-03-05 2004-09-21 Advanced Micro Devices, Inc. Charge-trapping memory arrays resistant to damage from contact hole information
US7977218B2 (en) * 2006-12-26 2011-07-12 Spansion Llc Thin oxide dummy tiling as charge protection
US11631680B2 (en) 2018-10-18 2023-04-18 Applied Materials, Inc. Methods and apparatus for smoothing dynamic random access memory bit line metal
US10700072B2 (en) 2018-10-18 2020-06-30 Applied Materials, Inc. Cap layer for bit line resistance reduction
US10903112B2 (en) 2018-10-18 2021-01-26 Applied Materials, Inc. Methods and apparatus for smoothing dynamic random access memory bit line metal

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4390971A (en) * 1978-03-20 1983-06-28 Texas Instruments Incorporated Post-metal programmable MOS read only memory
US5168334A (en) * 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
US5308777A (en) * 1993-07-28 1994-05-03 United Microelectronics Corporation Mask ROM process
JPH07307388A (ja) * 1994-02-04 1995-11-21 Advanced Micro Devices Inc トランジスタのアレイおよびその形成方法
US5455535A (en) * 1994-03-03 1995-10-03 National Semiconductor Corporation Rail to rail operational amplifier intermediate stage
US5471416A (en) * 1994-11-14 1995-11-28 National Semiconductor Corporation Method of programming a CMOS read only memory at the second metal layer in a two-metal process
US5815433A (en) * 1994-12-27 1998-09-29 Nkk Corporation Mask ROM device with gate insulation film based in pad oxide film and/or nitride film
GB2298739B (en) * 1995-03-07 1999-02-17 Hyundai Electronics Ind Method of making a mask ROM
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
JP3420694B2 (ja) * 1996-12-27 2003-06-30 株式会社東芝 スタンダードセル方式の集積回路
DE69636738D1 (de) * 1996-12-27 2007-01-11 St Microelectronics Srl Kontaktstruktur für elektronische EPROM oder flash EPROM Halbleiterschaltungen und ihr Herstellungsverfahren
US5915203A (en) * 1997-06-10 1999-06-22 Vlsi Technology, Inc. Method for producing deep submicron interconnect vias
US5966603A (en) * 1997-06-11 1999-10-12 Saifun Semiconductors Ltd. NROM fabrication method with a periphery portion
US5963465A (en) * 1997-12-12 1999-10-05 Saifun Semiconductors, Ltd. Symmetric segmented memory array architecture
US6133095A (en) * 1999-02-04 2000-10-17 Saifun Semiconductors Ltd. Method for creating diffusion areas for sources and drains without an etch step
KR20010018728A (ko) * 1999-08-21 2001-03-15 김영환 마스크 롬의 제조 방법
US6124192A (en) * 1999-09-27 2000-09-26 Vanguard International Semicondutor Corporation Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2007000808A1 (ja) * 2005-06-28 2009-01-22 スパンション エルエルシー 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP1390981A2 (en) 2004-02-25
US20040120198A1 (en) 2004-06-24
WO2002097890A2 (en) 2002-12-05
TW556326B (en) 2003-10-01
IL159112A0 (en) 2004-05-12
US7008849B2 (en) 2006-03-07
WO2002097890A3 (en) 2003-10-16

Similar Documents

Publication Publication Date Title
KR100871574B1 (ko) 트윈 ｍｏｎｏｓ 셀 제조 방법 및 어레이 구조
JP4388266B2 (ja) ストラップ領域及び周辺論理デバイス領域を有するフローティングゲートメモリセルの半導体アレーを形成する方法
US7361537B2 (en) Method of fabricating recess channel array transistor
USRE46890E1 (en) Method of forming semiconductor device having contact pad on source/drain region in peripheral circuit area
JP4086790B2 (ja) 非揮発性メモリーとその製造方法
US20080064206A1 (en) Method of manufacturing a semiconductor memory device
US7422939B2 (en) Semiconductor device having one-time programmable ROM and method of fabricating the same
US6211012B1 (en) Method of fabricating an ETOX flash memory
US20090114973A1 (en) Method for forming self-aligned contacts and local interconnects simultaneously
US6893921B2 (en) Nonvolatile memories with a floating gate having an upward protrusion
US8952536B2 (en) Semiconductor device and method of fabrication
US6849553B2 (en) Method of manufacturing semiconductor device
KR100682149B1 (ko) 게이트 전극 구조물 제조 방법, 콘택트 배열 제조 방법 및전계 효과 트랜지스터 배열 제조 방법
US20050077563A1 (en) Semiconductor memory cell having a trench and a planar selection transistor and method for producing the same
US6486033B1 (en) SAC method for embedded DRAM devices
US7008849B2 (en) Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts
EP1263051A1 (en) Bitline contacts in a memory cell array
US20080305595A1 (en) Methods of forming a semiconductor device including openings
US20070087496A1 (en) Non-volatile memory devices including fuse covered field regions
US6995060B2 (en) Fabrication of integrated circuit elements in structures with protruding features
US7172939B1 (en) Method and structure for fabricating non volatile memory arrays
KR100681286B1 (ko) 리세스된 채널을 갖는 반도체 장치의 제조 방법
CN101154633A (zh) 半导体存储装置的生产方法及半导体存储装置
TW202218121A (zh) 具有鰭式場效電晶體(finfet)結構的分離閘非揮發性記憶體單元、高壓(hv)與邏輯裝置及其製造方法
US20080146014A1 (en) Self aligned contact

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060922

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061102

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20070202

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20070216

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070502

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080319