JP2004048012A - 細かいピッチの、高アスペクト比を有するチップ配線用構造体及び相互接続方法 - Google Patents

細かいピッチの、高アスペクト比を有するチップ配線用構造体及び相互接続方法 Download PDF

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Publication number
JP2004048012A
JP2004048012A JP2003193323A JP2003193323A JP2004048012A JP 2004048012 A JP2004048012 A JP 2004048012A JP 2003193323 A JP2003193323 A JP 2003193323A JP 2003193323 A JP2003193323 A JP 2003193323A JP 2004048012 A JP2004048012 A JP 2004048012A
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metal
column
coating
windows
layer
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Japanese (ja)
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JP2004048012A5 (https=
Inventor
Diane Arbuthnot
ダイアン アーバスノット
Jeff R Emmett
ジェフ アール エメット
Gonzalo Amador
ゴンザロ アマダー
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Texas Instruments Inc
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Texas Instruments Inc
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251Changing the shapes of bumps
    • H10W72/01255Changing the shapes of bumps by using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251Changing the shapes of bumps
    • H10W72/01257Changing the shapes of bumps by reflowing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01271Cleaning, e.g. oxide removal or de-smearing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01931Manufacture or treatment of bond pads using blanket deposition
    • H10W72/01938Manufacture or treatment of bond pads using blanket deposition in gaseous form, e.g. by CVD or PVD
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01951Changing the shapes of bond pads
    • H10W72/01953Changing the shapes of bond pads by etching
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • H10W72/01971Cleaning, e.g. oxide removal
    • HELECTRICITY
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07231Techniques
    • H10W72/07236Soldering or alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221Structures or relative sizes
    • H10W72/222Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • HELECTRICITY
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221Structures or relative sizes
    • H10W72/225Bumps having a filler embedded in a matrix
    • HELECTRICITY
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231Shapes
    • H10W72/234Cross-sectional shape, i.e. in side view
    • HELECTRICITY
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • HELECTRICITY
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • H10W72/245Dispositions, e.g. layouts of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core
    • HELECTRICITY
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/252Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/253Materials not comprising solid metals or solid metalloids, e.g. polymers or ceramics
    • HELECTRICITY
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/923Bond pads having multiple stacked layers
    • HELECTRICITY
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
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    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
JP2003193323A 2002-07-15 2003-07-08 細かいピッチの、高アスペクト比を有するチップ配線用構造体及び相互接続方法 Pending JP2004048012A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/195,273 US20040007779A1 (en) 2002-07-15 2002-07-15 Wafer-level method for fine-pitch, high aspect ratio chip interconnect

Publications (2)

Publication Number Publication Date
JP2004048012A true JP2004048012A (ja) 2004-02-12
JP2004048012A5 JP2004048012A5 (https=) 2006-08-24

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JP2003193323A Pending JP2004048012A (ja) 2002-07-15 2003-07-08 細かいピッチの、高アスペクト比を有するチップ配線用構造体及び相互接続方法

Country Status (3)

Country Link
US (1) US20040007779A1 (https=)
EP (1) EP1387402A3 (https=)
JP (1) JP2004048012A (https=)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7642647B2 (en) 2004-05-20 2010-01-05 Nec Electronics Corporation Semiconductor device
JP2010508673A (ja) * 2006-10-31 2010-03-18 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 終端アルミニウム金属層のないメタライゼーション層積層体
JP2011228704A (ja) * 2010-04-19 2011-11-10 General Electric Co <Ge> マクロピンハイブリッド相互接続アレイ及びその製造方法
KR101208758B1 (ko) 2009-11-05 2012-12-05 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 구리 필라 범프를 형성하는 메카니즘
KR101283432B1 (ko) 2012-11-27 2013-07-08 민선미 철도차량 검수용 이동식 상부 작업대
US9293433B2 (en) 2013-12-10 2016-03-22 Shinko Electric Industries Co., Ltd. Intermetallic compound layer on a pillar between a chip and substrate
JP2018529238A (ja) * 2015-09-11 2018-10-04 クァン ケ フリップチップのパッケージ方法

Families Citing this family (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US20040084206A1 (en) * 2002-11-06 2004-05-06 I-Chung Tung Fine pad pitch organic circuit board for flip chip joints and board to board solder joints and method
TWI317548B (en) * 2003-05-27 2009-11-21 Megica Corp Chip structure and method for fabricating the same
TWI221335B (en) * 2003-07-23 2004-09-21 Advanced Semiconductor Eng IC chip with improved pillar bumps
US7394161B2 (en) * 2003-12-08 2008-07-01 Megica Corporation Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
TWI230989B (en) * 2004-05-05 2005-04-11 Megic Corp Chip bonding method
US7465654B2 (en) * 2004-07-09 2008-12-16 Megica Corporation Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
US8022544B2 (en) * 2004-07-09 2011-09-20 Megica Corporation Chip structure
US8067837B2 (en) * 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
US7452803B2 (en) * 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US7547969B2 (en) 2004-10-29 2009-06-16 Megica Corporation Semiconductor chip with passivation layer comprising metal interconnect and contact pads
US7332422B2 (en) * 2005-01-05 2008-02-19 Chartered Semiconductor Manufacturing, Ltd. Method for CuO reduction by using two step nitrogen oxygen and reducing plasma treatment
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
TWI330863B (en) * 2005-05-18 2010-09-21 Megica Corp Semiconductor chip with coil element over passivation layer
US7582556B2 (en) 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
CN102157494B (zh) * 2005-07-22 2013-05-01 米辑电子股份有限公司 线路组件
US8148822B2 (en) * 2005-07-29 2012-04-03 Megica Corporation Bonding pad on IC substrate and method for making the same
US8399989B2 (en) * 2005-07-29 2013-03-19 Megica Corporation Metal pad or metal bump over pad exposed by passivation layer
US7335536B2 (en) * 2005-09-01 2008-02-26 Texas Instruments Incorporated Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
US7397121B2 (en) * 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
KR100804392B1 (ko) * 2005-12-02 2008-02-15 주식회사 네패스 반도체 패키지 및 그 제조 방법
US8421227B2 (en) * 2006-06-28 2013-04-16 Megica Corporation Semiconductor chip structure
JP4270282B2 (ja) * 2007-01-23 2009-05-27 セイコーエプソン株式会社 半導体装置の製造方法
US8193636B2 (en) * 2007-03-13 2012-06-05 Megica Corporation Chip assembly with interconnection by metal bump
US7919859B2 (en) * 2007-03-23 2011-04-05 Intel Corporation Copper die bumps with electromigration cap and plated solder
EP1978559A3 (en) * 2007-04-06 2013-08-28 Hitachi, Ltd. Semiconductor device
US7964961B2 (en) * 2007-04-12 2011-06-21 Megica Corporation Chip package
US20080251927A1 (en) * 2007-04-13 2008-10-16 Texas Instruments Incorporated Electromigration-Resistant Flip-Chip Solder Joints
US8558379B2 (en) 2007-09-28 2013-10-15 Tessera, Inc. Flip chip interconnection with double post
US8269345B2 (en) * 2007-10-11 2012-09-18 Maxim Integrated Products, Inc. Bump I/O contact for semiconductor device
JP5363839B2 (ja) * 2008-05-12 2013-12-11 田中貴金属工業株式会社 バンプ及び該バンプの形成方法並びに該バンプが形成された基板の実装方法
US7855137B2 (en) * 2008-08-12 2010-12-21 International Business Machines Corporation Method of making a sidewall-protected metallic pillar on a semiconductor substrate
CN102484081A (zh) * 2009-07-02 2012-05-30 弗利普芯片国际有限公司 用于垂直柱互连的方法和结构
US9627254B2 (en) 2009-07-02 2017-04-18 Flipchip International, Llc Method for building vertical pillar interconnect
KR20110036450A (ko) * 2009-10-01 2011-04-07 삼성전기주식회사 플립칩용 기판의 제조방법 및 이를 이용하여 제조한 플립칩용 기판
TWI370532B (en) * 2009-11-12 2012-08-11 Ind Tech Res Inst Chip package structure and method for fabricating the same
US8431492B2 (en) 2010-02-02 2013-04-30 Sandisk 3D Llc Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same
US20110186989A1 (en) 2010-02-04 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Bump Formation Process
US20110227216A1 (en) * 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices
US8703546B2 (en) * 2010-05-20 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Activation treatments in plating processes
US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8283781B2 (en) * 2010-09-10 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having pad structure with stress buffer layer
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US8664760B2 (en) * 2011-05-30 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Connector design for packaging integrated circuits
US8610285B2 (en) 2011-05-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC packaging structures and methods with a metal pillar
US8373282B2 (en) * 2011-06-16 2013-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package with reduced stress on solder balls
US9184144B2 (en) * 2011-07-21 2015-11-10 Qualcomm Incorporated Interconnect pillars with directed compliance geometry
US9324667B2 (en) 2012-01-13 2016-04-26 Freescale Semiconductor, Inc. Semiconductor devices with compliant interconnects
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
US9082828B2 (en) * 2012-10-24 2015-07-14 Applied Materials, Inc. Al bond pad clean method
US9053990B2 (en) * 2012-10-25 2015-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Bump interconnection techniques
US20150048499A1 (en) * 2013-08-16 2015-02-19 Macrotech Technology Inc. Fine-pitch pillar bump layout structure on chip
US20150171039A1 (en) * 2013-12-13 2015-06-18 Chipmos Technologies Inc. Redistribution layer alloy structure and manufacturing method thereof
US20150276945A1 (en) 2014-03-25 2015-10-01 Oy Ajat Ltd. Semiconductor bump-bonded x-ray imaging device
US9412686B2 (en) * 2014-08-26 2016-08-09 United Microelectronics Corp. Interposer structure and manufacturing method thereof
JP6436531B2 (ja) * 2015-01-30 2018-12-12 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
US10163661B2 (en) 2015-06-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
JP6653383B2 (ja) * 2016-05-16 2020-02-26 株式会社アルバック 内部応力制御膜の形成方法
KR102678759B1 (ko) * 2016-10-14 2024-06-27 삼성전자주식회사 반도체 소자
TWI910033B (zh) 2016-10-27 2025-12-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件
US10833036B2 (en) 2018-12-27 2020-11-10 Texas Instruments Incorporated Interconnect for electronic device
JP7319808B2 (ja) * 2019-03-29 2023-08-02 ローム株式会社 半導体装置および半導体パッケージ
US10957664B2 (en) * 2019-05-29 2021-03-23 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN116848631A (zh) 2020-12-30 2023-10-03 美商艾德亚半导体接合科技有限公司 具有导电特征的结构及其形成方法
US11908790B2 (en) * 2021-01-06 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Chip structure with conductive via structure and method for forming the same

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0684546B2 (ja) * 1984-10-26 1994-10-26 京セラ株式会社 電子部品
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US5251806A (en) * 1990-06-19 1993-10-12 International Business Machines Corporation Method of forming dual height solder interconnections
US5059553A (en) * 1991-01-14 1991-10-22 Ibm Corporation Metal bump for a thermal compression bond and method for making same
US5334804A (en) * 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
JP2716336B2 (ja) * 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
US5470787A (en) * 1994-05-02 1995-11-28 Motorola, Inc. Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same
US5466635A (en) * 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
ATE210895T1 (de) * 1995-03-20 2001-12-15 Unitive Int Ltd Löthöcker-herstellungsverfahren und strukturen mit einer titan-sperrschicht
US5801446A (en) * 1995-03-28 1998-09-01 Tessera, Inc. Microelectronic connections with solid core joining units
US5796591A (en) * 1995-06-07 1998-08-18 International Business Machines Corporation Direct chip attach circuit card
TW318321B (https=) * 1995-07-14 1997-10-21 Matsushita Electric Industrial Co Ltd
JPH10125685A (ja) * 1996-10-16 1998-05-15 Casio Comput Co Ltd 突起電極およびその形成方法
KR100234694B1 (ko) * 1996-10-29 1999-12-15 김영환 비지에이 패키지의 제조방법
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
JP3352352B2 (ja) * 1997-03-31 2002-12-03 新光電気工業株式会社 めっき装置、めっき方法およびバンプの形成方法
US6025649A (en) * 1997-07-22 2000-02-15 International Business Machines Corporation Pb-In-Sn tall C-4 for fatigue enhancement
US6285085B1 (en) * 1997-08-13 2001-09-04 Citizen Watch Co., Ltd. Semiconductor device, method of fabricating the same and structure for mounting the same
JP3699828B2 (ja) * 1997-10-06 2005-09-28 シャープ株式会社 液晶表示素子およびその製造方法
US5975408A (en) * 1997-10-23 1999-11-02 Lucent Technologies Inc. Solder bonding of electrical components
JP3654485B2 (ja) * 1997-12-26 2005-06-02 富士通株式会社 半導体装置の製造方法
US6107180A (en) * 1998-01-30 2000-08-22 Motorola, Inc. Method for forming interconnect bumps on a semiconductor die
US6245583B1 (en) * 1998-05-06 2001-06-12 Texas Instruments Incorporated Low stress method and apparatus of underfilling flip-chip electronic devices
KR100643105B1 (ko) * 1998-05-06 2006-11-13 텍사스 인스트루먼츠 인코포레이티드 플립-칩 전자 디바이스를 언더필링하는 저응력 방법 및 장치
JPH11345837A (ja) * 1998-05-06 1999-12-14 Texas Instr Inc <Ti> アンダフィリングのフリップチップ電子デバイスの歪み低減方法及びその装置
JP3960445B2 (ja) * 1998-10-12 2007-08-15 新光電気工業株式会社 半導体装置とその製造方法
US6271107B1 (en) * 1999-03-31 2001-08-07 Fujitsu Limited Semiconductor with polymeric layer
JP3387083B2 (ja) * 1999-08-27 2003-03-17 日本電気株式会社 半導体装置及びその製造方法
US6312830B1 (en) * 1999-09-02 2001-11-06 Intel Corporation Method and an apparatus for forming an under bump metallization structure
US6372622B1 (en) * 1999-10-26 2002-04-16 Motorola, Inc. Fine pitch bumping with improved device standoff and bump volume
KR100345035B1 (ko) * 1999-11-06 2002-07-24 한국과학기술원 무전해 도금법을 이용한 고속구리배선 칩 접속용 범프 및 ubm 형성방법
JP2001185845A (ja) * 1999-12-15 2001-07-06 Internatl Business Mach Corp <Ibm> 電子部品の製造方法及び該電子部品
US6346469B1 (en) * 2000-01-03 2002-02-12 Motorola, Inc. Semiconductor device and a process for forming the semiconductor device
KR100319813B1 (ko) * 2000-01-03 2002-01-09 윤종용 유비엠 언더컷을 개선한 솔더 범프의 형성 방법
GB0001918D0 (en) * 2000-01-27 2000-03-22 Marconi Caswell Ltd Flip-chip bonding arrangement
US6620720B1 (en) * 2000-04-10 2003-09-16 Agere Systems Inc Interconnections to copper IC's
US6578754B1 (en) * 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6492197B1 (en) * 2000-05-23 2002-12-10 Unitive Electronics Inc. Trilayer/bilayer solder bumps and fabrication methods therefor
KR100407448B1 (ko) * 2000-06-12 2003-11-28 가부시키가이샤 히타치세이사쿠쇼 전자 기기 및 반도체 장치
US6426281B1 (en) * 2001-01-16 2002-07-30 Taiwan Semiconductor Manufacturing Company Method to form bump in bumping technology
EP1368458A2 (en) * 2001-02-26 2003-12-10 Pharma Pacific Pty. Ltd. Interferon-alpha induced gene
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US6596611B2 (en) * 2001-05-01 2003-07-22 Industrial Technology Research Institute Method for forming wafer level package having serpentine-shaped electrode along scribe line and package formed
US20040130034A1 (en) * 2001-06-13 2004-07-08 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package
US6683375B2 (en) * 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
US6649507B1 (en) * 2001-06-18 2003-11-18 Taiwan Semiconductor Manufacturing Company Dual layer photoresist method for fabricating a mushroom bumping plating structure
US20030006062A1 (en) * 2001-07-06 2003-01-09 Stone William M. Interconnect system and method of fabrication
US6605524B1 (en) * 2001-09-10 2003-08-12 Taiwan Semiconductor Manufacturing Company Bumping process to increase bump height and to create a more robust bump structure
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
TW200423344A (en) * 2002-12-31 2004-11-01 Texas Instruments Inc Composite metal column for mounting semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7642647B2 (en) 2004-05-20 2010-01-05 Nec Electronics Corporation Semiconductor device
JP2010508673A (ja) * 2006-10-31 2010-03-18 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 終端アルミニウム金属層のないメタライゼーション層積層体
KR101208758B1 (ko) 2009-11-05 2012-12-05 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 구리 필라 범프를 형성하는 메카니즘
US8659155B2 (en) 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
JP2011228704A (ja) * 2010-04-19 2011-11-10 General Electric Co <Ge> マクロピンハイブリッド相互接続アレイ及びその製造方法
KR101283432B1 (ko) 2012-11-27 2013-07-08 민선미 철도차량 검수용 이동식 상부 작업대
US9293433B2 (en) 2013-12-10 2016-03-22 Shinko Electric Industries Co., Ltd. Intermetallic compound layer on a pillar between a chip and substrate
JP2018529238A (ja) * 2015-09-11 2018-10-04 クァン ケ フリップチップのパッケージ方法
US10985300B2 (en) 2015-09-11 2021-04-20 Quan Ke Encapsulation method for flip chip

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