CN102484081A - 用于垂直柱互连的方法和结构 - Google Patents

用于垂直柱互连的方法和结构 Download PDF

Info

Publication number
CN102484081A
CN102484081A CN201080037577XA CN201080037577A CN102484081A CN 102484081 A CN102484081 A CN 102484081A CN 201080037577X A CN201080037577X A CN 201080037577XA CN 201080037577 A CN201080037577 A CN 201080037577A CN 102484081 A CN102484081 A CN 102484081A
Authority
CN
China
Prior art keywords
post
scolder
soldering paste
stacked
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201080037577XA
Other languages
English (en)
Inventor
居伊·F·布格斯
安东尼·库尔蒂斯
迈克尔·E·约翰逊
吉恩·斯托特
西奥多·G·特斯耶尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FlipChip International LLC
Original Assignee
FlipChip International LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FlipChip International LLC filed Critical FlipChip International LLC
Publication of CN102484081A publication Critical patent/CN102484081A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11474—Multilayer masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/11505—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H01L2224/11903—Multiple masking steps using different masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/13294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8184—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance

Abstract

在晶圆级芯片尺寸封装以及倒装芯片封装和组件中，在垂直柱上形成有焊料盖。在一个实施例中，所述垂直柱叠置在半导体衬底上。将可掺杂有至少一种微量元素的焊膏涂敷至该柱形结构的顶表面上。在涂敷焊膏之后执行回流工艺以形成焊料盖。

Description

用于垂直柱互连的方法和结构
相关申请
本申请要求2009年7月2日递交的、系列号为61/222,839(标题为METHOD FOR BUILDIG CU PILLAR INTERCONNECT(构造铜柱互连的方法))的美国临时申请的优先权，将该申请整体结合于此作为参考。
技术领域
本公开一般地涉及用于半导体器件的结构、装置、系统、以及方法，并且更具体地，涉及用于电子晶圆级芯片尺寸封装以及倒装芯片封装和组件的结构、装置、系统、以及方法。
背景技术
作为垂直互连技术中的一种类型，可通过本领域普通技术人员熟知的铜柱凸块形成技术将铜柱凸块施加至半导体芯片或其他微电子器件接合焊盘。铜柱凸块设置在芯片/器件上，而该芯片/器件仍然保持其晶圆形式。所有基于焊料的倒装芯片和/或芯片尺寸封装(CSP)类的互连(凸块)都要求适合的凸块下金属层(UBM)用作晶圆/衬底金属化层与焊料凸块本身之间的粘接层/扩散阻挡层。假如利用可靠的/可制造的方法在晶圆上形成焊料凸块，那么该柱凸块(铜、金、或其他金属/合金)就具有用作功能性UBM的可能性。
与常规焊料凸块或CSP互连相比，铜柱凸块提供了刚性的竖直结构。在需要控制两个表面(例如器件与其相关衬底)之间的间隔(standoff)的应用中，铜柱凸块用作固定间隔以控制该间距，同时该焊料执行这两个表面之间的接头连接。对该间隔的控制对整个系统性能和可靠性是至关重要的。与等同倒装芯片或CSP焊料凸块结构相比，铜(Cu)柱凸块结构还提供了改进的热传递和电阻率。
在微电子工业中，铜(Cu)柱凸块结构有可能成为用于特定市场的节约成本的、可靠的互连选择。不过，需要可靠且低成本的可制造方法，以用于形成这些多用途的固定间隔凸块结构。大部分柱凸块制造法采用可限定光掩膜材料电镀铜柱结构，随后是电镀焊料。电镀焊料是缓慢且昂贵的工艺，这需要大量的工艺控制并且将焊料严格限制在单金属或二元焊料合金的狭窄供应内。通常，在制造环境中，很难控制电镀超过一种的二元焊料合金以形成柱凸块的焊料部分。然而，在半导体工业中，期望采用各种多元素合金或掺杂有微量元素的合金，以改进用于目标应用或最终用途的互连的可靠性。
附图说明
根据以下说明和附图，将会更好地理解本公开的这些以及其他特征、方面、以及优势，附图中相同的标号表示同样的元件。
图1示出了根据本公开至少一个实施例的具有输入/输出(I/O)接合焊盘104的晶圆衬底102的一部分的横截面图。该图示出了钝化层103和介电层105。在一个实施例中，介电层105是聚合物层。该图还示出了沉积的电镀种子层106和双重目的的光致抗蚀掩膜材料108，接着进行图案化曝光以及显影(develop)。如以下所述，这形成了用于随后的铜(或其他金属)镀敷及焊膏印刷工艺所需的孔110。
图2示出了根据本公开至少一个实施例的镀铜之后的柱体202的横截面图，其中预留孔110的上部分204以用于焊膏印刷；
图3示出了根据本公开至少一个实施例的在将焊膏300印刷至孔中之后的横截面图。这使得能够利用具有各种微量元素选项的多元素焊料合金，以改进焊料的可靠性；
图4示出了根据本公开至少一个实施例的焊料回流之后的横截面图，其中焊膏已在铜(Cu)柱202顶部上形成半球形焊料凸块402；
图5示出了根据本公开的至少一个实施例的横截面图，示出了种子层106的在剥去光致抗蚀材料并且蚀刻去除非柱体镀敷部分之后的完成部分；
图6示出了根据本公开的至少一个实施例，示出了具有相应板606或其他衬底的组装铜(Cu)柱凸块的横截面图。在组装至板或衬底606上的焊盘604之后，焊料盖402提供了焊料连接602。在组装过程中提供了底部填充或二次成型(overmolding)605；
图7示出了根据本公开的至少一个实施例，示出了用在可选实施例中的本公开方法的一个变型，其中，许多选项之一是采用多层光致抗蚀(108、702)和/或其他抗蚀型材料，以在柱状结构和焊料量中产生变化，以便得到期望的柱和焊料三维参数。在一个特定实施例中，光致抗蚀层702具有多个孔，并且每个孔用于限定焊膏300的叠置在特定柱202上的一部分的尺寸。每个柱202具有由光致抗蚀层108中多个孔中相应的一个孔限定的尺寸。因此，焊膏300的横向尺寸大于柱202。在其他实施例中，如可针对期望特定互连应用所期望的，每个光致抗蚀层108和702中的高度和孔尺寸，以调整柱金属和层叠的焊料材料的相对体积。
此处阐述的范例示出了特定实施例，不应以任何方式将这种范例阐释为限制性的。
具体实施方式
在以下的描述中，陈述了大量细节，以便提供更透彻的说明。不过，本领域普通技术人员显而易见的是，在没有这些特定细节的情况下也可以实现本公开的方法和结构。在其他实例中，未详细描述众所周知的特征，以不会造成不必要的使本公开难以理解。
在此处讨论的不同实施例中，本公开提供了加强的基于焊料的晶圆焊盘形成技术，其具有可变化高度的凸块下金属层(UBM)，从而提供功能性垂直互连结构，该互连结构可用于将半导体芯片或其他微电子器件连接至电路板，或连接至用于二维(2D)和三维(3D)封装方案中使用的其他衬底。
本发明公开了用于形成垂直柱202上焊料盖402的可靠且可制造的方法。在一个实施例中，公开了一种方法，该方法通过采用双重目的的光致抗蚀工艺，提供了一种能够显著简化制造流程，并且降低垂直互连结构制造成本的途径，其中双重目的的光致抗蚀工艺既用作电镀模式，又用作随后的焊膏原位图案模板。在另一个实施例中，公开了一种方法，该方法用于将不同焊膏印刷至垂直柱结构的顶部，接着回流以形成焊料盖402。在又一个实施例中，公开了一种使用焊膏的方法，该方法也包括在焊膏中使用各种多元素合金以及微量元素(trace element，痕量元素)的方法，从而能够增强焊料盖402的可靠性或性能。
在一个或多个实施例中，这些方法应用于铜柱202和各种尺寸和形状的其他垂直互连方案，包括但不限于，采用以下金属形成柱202：铜及其合金、金及其合金、镍及其合金、以及银及其合金。铜(Cu)柱202还可以包括可润湿焊料盖涂饰(未示出)，其包括但不仅限于：Ni、NiAu、NiPdAu、NiPd、Pd以及NiSn。
在一些实施例中，这些方法可以用于形成附接至输入/输出(I/O)焊垫104的铜(Cu)柱凸块结构，或者用作离开重新分布的接合焊盘的附接结构。
在一些实施例中，使用印刷的焊膏300，与采用镀敷焊料的在先方法相比，其使得成品的焊料合金的范围更大。在一个或多个实施例中，焊膏300是以下合金/金属之一：SnPb合金、SnPbCu合金、SnAgCu合金、AuGe合金、AuSn合金、AuSi合金、SnSb合金、SnSbBi合金、PbSnSb合金、PbInSb合金、PbIn合金、PbSnAg合金、SnAg合金、PbSb合金、SnInAg合金、SnCu合金、PbAg合金、PbSbGa合金、SnAs合金、SnGe合金、ZnAl合金、CdAg合金、GeAl合金、AuIn合金、AgAuGe合金、AlSi合金、AlSiCu合金、AgCdZnCu合金、以及AgCuZnSn合金。也可以使用其他焊膏材料。
在一些实施例中，该方法还可包括沉积在“原位”孔中的任意焊料烧结合金，例如Ag烧结材料。此外，多个实施例采用了印刷焊膏300，其允许这样的成品选项，在焊料中具有各种微量元素，包括但不仅限于，Bi、Ni、Sb、Fe、Al、In、以及Pb。在可选实施例中，焊膏300是单一金属焊料。例如，焊膏可以是Sn。像此处针对焊料合金所述的掺杂一样，该单一金属焊料可掺杂有一种或多种微量元素。
采用这些方法产生的柱202和焊料盖402的结构可以具有，例如5微米(μm)与400微米(μm)的范围之间的总高度，以及低至10微米(μm)的斜度(pitch)。
利用这些方法产生的柱202的x和y二维极限(即垂直和水平极限)可使得柱202例如小至5微米(μm)以及大至2.0毫米(mm)。在其他实施例中，利用这些方法产生的柱体202具有大至5.0毫米(mm)的x和y二维极限。
在一个或多个实施例中，本公开的采用具有不同迭代的垂直互连结构上的焊膏形成焊料凸块的方法如下所述：
步骤1.通过常规方法(即喷溅、蒸发、化学镀、等等)沉积金属种子层106，以提供连续的种子层106用于电化学镀。
在一个实施例中，已预先在钝化层103上形成介电层105(例如聚合物层)。已预先图案化介电层105以便形成开口，以露出接合焊盘104的相应部分，以使种子层106的部分可与每个接合焊盘104的顶表面接触。
步骤2.在晶圆/衬底102的整个表面上涂敷光致抗蚀层108或其他抗蚀型材料。这可以通过干薄膜层压、或旋涂或喷涂法实现。
在其他实施例中，光致抗蚀层108可以是通过涂敷两层或更多层光致抗蚀层形成的光致抗蚀堆叠，每层都具有相同尺寸的孔(即光致抗蚀堆叠的孔尺寸)。在一个实施例中，这两层或多层光致抗蚀层在相同的工艺步骤中显影。在可选实施例中，每个光致抗蚀层都能独立地显影。
步骤3.在该实施例中，通常基于设计，使紫外线(UV)穿过适当的光掩膜曝光而限定光致抗蚀层108，但孔的形成不局限于UV曝光/显影形成孔，并且孔的形成还可包括但不限于，激光烧蚀、干蚀刻、和/或剥离工艺。
对于该方法的可选实施例，可以涂敷多层光致抗蚀材料或其他抗蚀型材料，以在相同的抗蚀剂堆叠中形成不同的孔高和孔尺寸，该孔高和孔尺寸能够促进不同的柱形结构和在柱形结构顶部印刷不同的焊料量。
步骤4.使覆盖种子层106的光致抗蚀层108显影，或者对其开口，形成敞口的“原位”孔110，以用于柱202的镀敷以及随后的焊膏印刷。
步骤5.将柱202电镀至光致抗蚀层108中形成的孔110中的种子金属层106上。
步骤6.将焊膏300印刷在光致抗蚀模板中的“原位”孔110的上部分204中，并且焊膏300覆盖铜柱202的顶部。印刷的焊膏300的总深度的范围可以为，例如在2微米(μm)与200微米(μm)之间。可选地，还可以使用金属模板以便进一步限定区域，该区域为将焊料涂敷在“原位”光致抗蚀材料中及上方的柱凸块结构上。
步骤7.接着，使具有印刷焊膏300布置在位的晶圆或其他衬底102回流并且冷却，在铜柱202顶部上形成焊料盖402。
步骤8.剥离或以其他方式去除“原位”光致抗蚀模板材料。
步骤9.将未镀敷的种子层106选择性地蚀刻掉，留下盖有焊料的独立柱202。
步骤10.在晶圆或其他衬底上可执行二次回流，以最优化凸块形状。此外，可以利用压印或压平工艺，进一步降低超出作为现有技术一部分的已开发的铜(Cu)柱技术的凸块至凸块分辨率。
利用本领域普通技术人员已知的处理方法和工具设备通过光学成像、镀敷、以及焊料焊盘形成工艺执行所有步骤1-10。在可选实施例中，可以在不使用介电层105的情况下执行以上步骤。更具体地，在这些可选实施例中，从未形成介电层105并且最终的结构中不存在介电层105。种子层106(例如通过沉积)直接形成在钝化层103和接合焊盘104上。
应该说明的是，预先已有他人使用电镀形成柱上焊料的互连结构。APS、Casio、以及RFMD都已经将铜柱电镀在器件上的互连盘上，并且接着将电镀焊料盖施加至柱顶部以用于器件与连接衬底之间的互连材料。APS的在先专利包括以下专利：US 6,732,913、US 6,681,982、以及US6,592,019。此外，倒装芯片国际公司(FCI)先前已经利用“原位”光致抗蚀材料来限定预先形成的UBM(不是由相同的光致抗蚀层限定)上的焊料开口。不过，这些现有方法中都没有使用如此处所述的用于镀敷和印刷焊膏的双重目的光致抗蚀工艺。
可以期望使用本公开的部分实施例来提供用于高功率应用以及用于倒装芯片应用中一致的间距的受控皱缩的互连方案，尤其用于系统封装应用中，该系统封装应用中可期望最大的元件密度以及避免用于底部填充的“保持在外(keep-out)”区。
以上公开的多个其他实施例可包括以下方法和结构(以下编仅为便于参考)：
1.一种使用在焊料合金中掺杂有任意种微量元素的焊膏的方法，其中，所述焊料合金用于形成铜柱的任意现有或新方法，并且具体地，利用掺杂的焊膏对铜柱“封顶”。
2.一种使用任意种合金的焊膏的方法，该合金用于形成铜柱的任意现有或新方法，并且具体地，利用焊膏对铜柱“封顶”以形成焊料盖。
3.一种形成覆盖有焊料的垂直柱结构的方法，该方法基于使用双重目的的“原位”光致抗蚀工艺或其他类型抗蚀剂材料，其中该抗蚀剂既用作电镀模具又用作随后的焊膏图案模板。
4.一种形成覆盖有焊料的垂直柱结构的方法，该方法基于将焊膏合金印刷在垂直柱结构的顶部上，随后进行回流处理。该焊膏可以包括任意尺寸范围(包括毫微颗粒)的焊料颗粒。
5.在一个实施例中，通过使用多元素焊膏合金可以进一步改进基于印刷焊膏合金形成覆盖有焊料的垂直柱结构的方法，通过现有技术列示的镀敷方法不易于实现使用多元素焊膏合金。这些多元素焊料合金能够改进用于垂直互连的焊料和/或金属间化物的可靠性或性能。
6.一种形成覆盖有焊料的垂直柱结构的方法，该方法基于将焊膏合金印刷在垂直柱结构的顶部上，随后进行回流处理，其中焊料合金中掺杂有不同微量元素(例如，但不仅限于，Bi、Ni、Sb、Fe、Al、In、以及Pb)。这些掺杂的焊料合金能够改进用于垂直互连的焊料和/或金属间化物的可靠性或性能。
7.采用双重目的光致抗蚀工艺并且将焊膏印刷在柱形结构顶部上的方法使得制造成本低于常规镀敷焊料方法，这是由于工艺时间更快，并且与焊料镀敷相比，焊料印刷减少了所需的工艺控制。
8.双重目的抗蚀剂方法的可选实施例可包括多层抗蚀剂材料，所述抗蚀剂材料具有一个或多个曝光或以其他方法开设的抗蚀剂孔，可以涂敷该抗蚀剂材料以在相同的抗蚀剂堆叠中形成不同的孔高和孔尺寸，该孔高和孔尺寸能够促进不同的柱形结构以及将不同的焊料量印刷在柱形结构的顶部。
9.这些不同种类的覆盖有焊料的柱形结构可以结合到3D晶圆级封装应用中，在所述应用中需要可变高度的z-轴互连。
在一个实施例中，一种方法包括：形成第一和第二垂直柱，每个柱都叠置在相应的焊料焊盘上，其中相应的焊料焊盘叠置在半导体衬底上，并且每个第一柱和第二柱均具有不同高度；形成具有第一孔和第二孔的至少一个光致抗蚀层；并且在每一个第一柱和第二柱的顶表面上涂敷焊料，其中第一柱上的焊料由第一孔限定，并且第二柱上的焊料由第二孔限定。
10.将焊膏印刷在柱形柱结构顶部的方法不仅可以用于“原位”光致抗蚀中的孔中，而且可以利用金属模板来完成，其中将焊膏涂敷在“原位”光致抗蚀中和上方的柱凸块结构上方，这使得涂敷焊料量更具有多面性。
11.与现有技术中提出的常规镀敷法相比，采用用于制造柱凸块的双重目的抗蚀剂的方法改进了总体柱/焊料的高度均匀性。由于在衬底上存在高度均匀性的差异，在对该结构的铜(Cu)柱部分进行镀敷之后，通过填重“原位”孔的剩余高度，印刷的焊料有助于对任何高度变化进行平坦化，从而调和任何变化。对于常规柱凸块镀敷法，柱的镀敷的焊料部分会在晶圆或其他衬底上在高度均匀性方面延伸出任意差值。
12.在形成垂直柱之后，可以执行涂敷一层或多层光致抗蚀材料或其他抗蚀剂材料以用于最终焊膏填充的工艺步骤。
13.可以在形成垂直结构且随后对铜(Cu)柱结构进行机械或化学校平之后，执行涂敷一层或多层光致抗蚀材料或其他抗蚀剂材料以用于最终焊膏填充的工艺步骤，或者使用机械模板涂敷焊膏的工艺步骤。这会在焊膏沉积之前使铜(Cu)柱或其他金属柱形结构平坦化。
14.这些方法适用于铜柱凸块状结构以及不同尺寸和形状的其他垂直互连方案，这些垂直互连方案包括但不仅限于以下金属：铜及其合金、金及其合金、镍及其合金、以及银及其合金。铜(Cu)柱还可以包括可润湿焊料盖涂饰，该可润湿焊料盖涂饰包括但不仅限于：Ni、NiAu、NiPdAu、NiPd、Pd、以及NiSn。
15.这些方法能够形成不同形状的垂直互连，包括但不仅限于，圆形、矩形、八边形、等等。
仍是在另一个实施例中，提供了一种方法，该方法包括形成第一和第二垂直柱，每个柱体都叠置在相应的接合焊盘上，其中该相应的接合焊盘叠置在半导体衬底上；形成具有第一孔和第二孔的至少一个光致抗蚀层；将焊料涂敷在每一个第一和第二柱的顶表面上，其中第一柱上的焊料由第一孔限定，并且第二柱上的焊料由第二孔限定；以及执行回流，以在第一柱上形成第一焊料盖，并且在第二柱上形成第二焊料盖，其中第一柱和第一焊料盖的组合高度大于第二柱和第二焊料盖的组合高度。在一个实施例中，该至少一个光致抗蚀层是单层光致抗蚀层或多层光致抗蚀堆叠。在一个实施例中，第一柱和第一焊料盖的组合高度比第二柱和第二焊料盖的组合高度高出至少约5微米。
虽然此处公开了某些示例性实施例和方法，从以上所述公开中，本领域普通技术人员显而易见的是，在不背离本公开的真实精神和范围的前提下，可以对所述实施例和方法做出变型和修改。

Claims (32)

1.一种方法，包括：
形成叠置在接合焊盘上的垂直柱，其中所述接合焊盘叠置在一半导体衬底上；以及
在所述柱的顶表面上涂敷焊膏，其中所述焊膏由至少一个光致抗蚀层限定。
2.根据权利要求1所述的方法，其中，所述柱由至少一个光致抗蚀层限定。
3.根据权利要求1所述的方法，其中：
所述至少一个光致抗蚀层具有第一孔以限定所述焊膏；
所述柱由另外的光致抗蚀层中的第二孔限定；
所述至少一个光致抗蚀层形成得叠置在所述另外的光致抗蚀层上；并且
所述第一孔具有的横向尺寸大于所述第二孔。
4.根据权利要求1所述的方法，其中，所述焊膏是焊料合金或单一金属焊料，并且所述焊膏掺杂有至少一种微量元素。
5.根据权利要求4所述的方法，其中，所述至少一种微量元素是Bi、Ni、Sb、Fe、Al、In和Pb中的至少一种。
6.根据权利要求1所述的方法，其中，所述焊膏是多元素焊料合金。
7.根据权利要求1所述的方法，进一步包括在涂敷焊膏之后执行回流，以便在所述垂直柱的顶部上形成焊料盖。
8.根据权利要求1所述的方法，其中，所述垂直柱是多个垂直柱之一，并且所述方法进一步包括在涂敷所述焊膏之前使所述多个垂直柱平坦化。
9.根据权利要求1所述的方法，其中，所述垂直柱是多个垂直柱之一，并且所述多个垂直柱中每一个对应于可变高度的z-轴互连。
10.根据权利要求1所述的方法，其中，所述垂直柱为铜的。
11.根据权利要求10所述的方法，其中，所述垂直柱包括由Ni、NiAu、NiPdAu、NiPd、Pd、以及NiSn之一形成的可润湿焊料盖涂饰。
12.根据权利要求1所述的方法，其中，所述垂直柱是铜、铜合金、金、金合金、镍、镍合金、银、以及银合金中之一。
13.根据权利要求1所述的方法，其中，所述垂直柱的形状选自以下之一：圆形、矩形、以及八边形。
14.根据权利要求1所述的方法，其中，所述焊膏是焊料合金或单一金属焊料。
15.根据权利要求1所述的方法，进一步包括在形成所述垂直柱之前形成叠置在所述接合焊盘上的一种子层。
16.根据权利要求15所述的方法，进一步包括在形成所述垂直柱之前形成叠置在所述种子层上的所述至少一个光致抗蚀层。
17.根据权利要求1所述的方法，进一步包括：
在形成所述垂直柱之前形成叠置在所述接合焊盘上的一介电层且在所述介电层中提供一开口以露出所述接合焊盘的一部分；以及
形成叠置在所述介电层上的一种子层。
18.根据权利要求17所述的方法，其中，所述介电层是聚合物层。
19.根据权利要求1所述的方法，进一步包括利用金属模板限定一区域，其中，所述焊膏的一部分被涂敷在所述至少一个光致抗蚀层上方的所述垂直柱上。
20.根据权利要求1所述的方法，其中，所述至少一个光致抗蚀层是以下之一：单一光致抗蚀层；以及多个光致抗蚀层，其中每个所述光致抗蚀层均具有相同尺寸的孔。
21.根据权利要求1所述的方法，其中，所述涂敷焊膏包括印刷所述焊膏。
22.根据权利要求1所述的方法，其中，所述焊膏是Sn。
23.根据权利要求2所述的方法，进一步包括，在涂敷所述焊膏之后执行回流，以便在所述垂直柱的顶部上形成焊料盖。
24.一种方法，包括：
形成叠置在一接合焊盘上的一垂直铜柱，其中所述接合焊盘叠置在一半导体衬底上；
将焊膏涂敷在所述铜柱的顶部上，其中所述焊膏由至少一个光致抗蚀层限定，并且所述焊膏掺杂有至少一种微量元素；以及
执行回流，以便用所述焊膏形成焊料盖。
25.根据权利要求24所述的方法，其中，所述垂直铜柱包括可润湿焊料盖涂饰，所述可润湿焊料盖涂饰由Ni、NiAu、NiPdAu、NiPd、Pd以及NiSn之一形成。
26.根据权利要求24所述的方法，进一步包括：
在形成所述垂直铜柱之前形成叠置在所述接合焊盘上的一种子层；以及
在形成所述垂直铜柱之前形成叠置在所述种子层上的所述至少一个光致抗蚀层。
27.根据权利要求24所述的方法，其中，所述焊膏是Sn。
28.根据权利要求24所述的方法，进一步包括：
在形成所述垂直铜柱之前形成叠置在所述接合焊盘上的一介电层且在所述介电层中提供一开口以露出所述接合焊盘的一部分；以及
形成叠置在所述介电层上的一种子层。
29.根据权利要求24所述的方法，其中一钝化层叠置在所述半导体衬底上，并且所述钝化层具有一开口以露出所述接合焊盘，所述方法进一步包括，在形成所述垂直铜柱之前将一种子层直接沉积在所述钝化层和所述接合焊盘上。
30.一种方法，包括：
形成第一垂直柱和第二垂直柱，每一个均叠置在相应的接合焊盘上，其中所述相应的接合焊盘叠置在一半导体衬底上；
形成至少一个光致抗蚀层，所述光致抗蚀层具有第一孔和第二孔；
将焊料涂敷在所述第一柱和所述第二柱中每一个的顶表面上，其中所述第一柱上的所述焊料由所述第一孔限定，并且所述第二柱上的所述焊料由所述第二孔限定；以及
执行回流，以在所述第一柱上形成第一焊料盖以及在所述第二柱上形成第二焊料盖，其中所述第一柱和第一焊料盖的组合高度大于所述第二柱和第二焊料盖的组合高度。
31.根据权利要求30所述的方法，其中，所述至少一个光致抗蚀层是单层光致抗蚀层或多层光致抗蚀堆叠。
32.根据权利要求30所述的方法，其中，所述第一柱和第一焊料盖的组合高度比所述第二柱和第二焊料盖的组合高度高出至少约5微米。
CN201080037577XA 2009-07-02 2010-06-29 用于垂直柱互连的方法和结构 Pending CN102484081A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US22283909P 2009-07-02 2009-07-02
US61/222,839 2009-07-02
PCT/US2010/040410 WO2011002778A2 (en) 2009-07-02 2010-06-29 Methods and structures for a vertical pillar interconnect

Publications (1)

Publication Number Publication Date
CN102484081A true CN102484081A (zh) 2012-05-30

Family

ID=43411697

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080037577XA Pending CN102484081A (zh) 2009-07-02 2010-06-29 用于垂直柱互连的方法和结构

Country Status (7)

Country Link
US (1) US20110003470A1 (zh)
EP (1) EP2449582A4 (zh)
JP (1) JP2012532459A (zh)
KR (1) KR20120045005A (zh)
CN (1) CN102484081A (zh)
TW (1) TW201108342A (zh)
WO (1) WO2011002778A2 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104008983A (zh) * 2014-05-04 2014-08-27 清华大学 一种金属凸点制造方法
CN106057761A (zh) * 2016-08-14 2016-10-26 天津大学 用于超大规模集成电路芯片的桶形焊球重分布封装结构
CN106653719A (zh) * 2016-12-30 2017-05-10 通富微电子股份有限公司 一种圆片级封装结构与封装方法
CN109564897A (zh) * 2016-09-15 2019-04-02 英特尔公司 镍-锡微凸块结构及其制造方法

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8592995B2 (en) * 2009-07-02 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump
JP2012038965A (ja) * 2010-08-09 2012-02-23 Lapis Semiconductor Co Ltd 半導体装置及びその製造方法
JP2012069903A (ja) * 2010-08-27 2012-04-05 Elpida Memory Inc 半導体装置及びその製造方法
KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
US9142743B2 (en) * 2011-08-02 2015-09-22 Kabushiki Kaisha Toshiba High temperature gold-free wafer bonding for light emitting diodes
US8431478B2 (en) * 2011-09-16 2013-04-30 Chipmos Technologies, Inc. Solder cap bump in semiconductor package and method of manufacturing the same
US8810020B2 (en) 2012-06-22 2014-08-19 Freescale Semiconductor, Inc. Semiconductor device with redistributed contacts
US20150072515A1 (en) * 2013-09-09 2015-03-12 Rajendra C. Dias Laser ablation method and recipe for sacrificial material patterning and removal
US9165877B2 (en) * 2013-10-04 2015-10-20 Mediatek Inc. Fan-out semiconductor package with copper pillar bumps
JP6004441B2 (ja) 2013-11-29 2016-10-05 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ 基板接合方法、バンプ形成方法及び半導体装置
CN103779246A (zh) * 2014-02-21 2014-05-07 江阴长电先进封装有限公司 一种高可靠性的铜柱凸块封装方法及其封装结构
US20150276945A1 (en) 2014-03-25 2015-10-01 Oy Ajat Ltd. Semiconductor bump-bonded x-ray imaging device
KR102344790B1 (ko) 2014-08-29 2021-12-30 닛데쓰마이크로메탈가부시키가이샤 반도체 접속의 Cu 필러용 원기둥상 형성물
JP6476823B2 (ja) * 2014-12-16 2019-03-06 三菱マテリアル株式会社 ピラー形成用ペースト、ピラーの製造方法、バンプ構造体の製造方法、ピラー、及びバンプ構造体
US9508671B2 (en) 2015-04-20 2016-11-29 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US10340241B2 (en) 2015-06-11 2019-07-02 International Business Machines Corporation Chip-on-chip structure and methods of manufacture
TWI572257B (zh) * 2015-10-19 2017-02-21 欣興電子股份有限公司 柱狀結構及其製作方法
KR102513360B1 (ko) * 2016-02-22 2023-03-24 삼성디스플레이 주식회사 범프 구조물, 범프 구조물을 포함하는 구동 칩 및 범프 구조물의 제조 방법
US9837341B1 (en) * 2016-09-15 2017-12-05 Intel Corporation Tin-zinc microbump structures
US10797012B2 (en) 2017-08-25 2020-10-06 Dialog Semiconductor (Uk) Limited Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices
US11183615B2 (en) * 2018-02-01 2021-11-23 Nuvoton Technology Corporation Japan Semiconductor device
KR102495582B1 (ko) 2018-02-08 2023-02-06 삼성전자주식회사 평탄화된 보호막을 갖는 반도체 소자 및 그 제조방법
JP7228086B2 (ja) 2018-07-26 2023-02-24 Dic株式会社 導電性ペーストを用いた導電性ピラーの製造方法
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件
US11127705B2 (en) * 2019-01-16 2021-09-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US11235404B2 (en) * 2020-03-21 2022-02-01 International Business Machines Corporation Personalized copper block for selective solder removal
KR20240055121A (ko) 2022-07-29 2024-04-26 유비이 가부시키가이샤 폴리이미드 전구체 조성물, 폴리이미드 필름 및 폴리이미드 필름/기재 적층체

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1239514A2 (en) * 2001-03-05 2002-09-11 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US20040185649A1 (en) * 2003-03-20 2004-09-23 Min-Lung Huang [a wafer bumping process]
US20060094226A1 (en) * 2004-10-28 2006-05-04 Advanced Semiconductor Engineering, Inc. Bumping process
US20060094224A1 (en) * 2004-11-03 2006-05-04 Advanced Semiconductor Engineering, Inc. Bumping process and structure thereof
KR20070036531A (ko) * 2005-09-29 2007-04-03 매그나칩 반도체 유한회사 반도체 칩 모듈 제작방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG49779A1 (en) * 1993-11-26 1998-06-15 Delco Electronics Corp Method of forming solder bumps on an integrated circuit flip chip
JP3310499B2 (ja) * 1995-08-01 2002-08-05 富士通株式会社 半導体装置
US6578754B1 (en) * 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6592019B2 (en) * 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
US6732913B2 (en) * 2001-04-26 2004-05-11 Advanpack Solutions Pte Ltd. Method for forming a wafer level chip scale package, and package formed thereby
JP3615206B2 (ja) * 2001-11-15 2005-02-02 富士通株式会社 半導体装置の製造方法
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6974659B2 (en) * 2002-01-16 2005-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a solder ball using a thermally stable resinous protective layer
US20040007779A1 (en) * 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
US20060094266A1 (en) * 2004-11-01 2006-05-04 Hon Hai Precision Ind Co., Ltd. Electrical connector having protecting device
US8741737B2 (en) * 2006-09-20 2014-06-03 Board Of Regents, The University Of Texas System Three-dimensional wafer stacking with vertical interconnects
KR101036388B1 (ko) * 2008-08-19 2011-05-23 삼성전기주식회사 인쇄회로기판 및 이의 제조 방법
US9627254B2 (en) * 2009-07-02 2017-04-18 Flipchip International, Llc Method for building vertical pillar interconnect

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1239514A2 (en) * 2001-03-05 2002-09-11 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US20040185649A1 (en) * 2003-03-20 2004-09-23 Min-Lung Huang [a wafer bumping process]
US20060094226A1 (en) * 2004-10-28 2006-05-04 Advanced Semiconductor Engineering, Inc. Bumping process
US20060094224A1 (en) * 2004-11-03 2006-05-04 Advanced Semiconductor Engineering, Inc. Bumping process and structure thereof
KR20070036531A (ko) * 2005-09-29 2007-04-03 매그나칩 반도체 유한회사 반도체 칩 모듈 제작방법

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104008983A (zh) * 2014-05-04 2014-08-27 清华大学 一种金属凸点制造方法
CN104008983B (zh) * 2014-05-04 2016-10-12 清华大学 一种金属凸点制造方法
CN106057761A (zh) * 2016-08-14 2016-10-26 天津大学 用于超大规模集成电路芯片的桶形焊球重分布封装结构
CN109564897A (zh) * 2016-09-15 2019-04-02 英特尔公司 镍-锡微凸块结构及其制造方法
CN109564897B (zh) * 2016-09-15 2023-07-28 英特尔公司 镍-锡微凸块结构及其制造方法
CN106653719A (zh) * 2016-12-30 2017-05-10 通富微电子股份有限公司 一种圆片级封装结构与封装方法

Also Published As

Publication number Publication date
WO2011002778A3 (en) 2011-03-31
JP2012532459A (ja) 2012-12-13
US20110003470A1 (en) 2011-01-06
TW201108342A (en) 2011-03-01
EP2449582A2 (en) 2012-05-09
WO2011002778A2 (en) 2011-01-06
KR20120045005A (ko) 2012-05-08
EP2449582A4 (en) 2013-06-12

Similar Documents

Publication Publication Date Title
CN102484081A (zh) 用于垂直柱互连的方法和结构
US9627254B2 (en) Method for building vertical pillar interconnect
CN106558537B (zh) 集成多输出结构以及形成方法
US6743660B2 (en) Method of making a wafer level chip scale package
US6939789B2 (en) Method of wafer level chip scale packaging
US8461679B2 (en) Method for fabricating circuit component
US6930032B2 (en) Under bump metallurgy structural design for high reliability bumped packages
US11031256B2 (en) Semiconductor device with tiered pillar and manufacturing method thereof
CN109979903B (zh) 具有凸块结构的半导体器件和制造半导体器件的方法
US20030073036A1 (en) Method of making tall flip chip bumps
TWI792089B (zh) 半導體裝置和製造其之方法
TWI669763B (zh) 用於在半導體晶圓上形成柱狀凸塊的方法
US7956472B2 (en) Packaging substrate having electrical connection structure and method for fabricating the same
CN105977166A (zh) 用于在半导体装置的金属基极层上产生金属柱的方法
US20170053883A1 (en) Integrated circuit package
US10141270B2 (en) Semiconductor device and method of manufacturing thereof
CN108269780B (zh) 半导体装置及其制造方法
KR101758999B1 (ko) 반도체 디바이스 및 그 제조 방법
US11393742B2 (en) Method for fabricating a semiconductor flip-chip package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120530