JP2003332582A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法Info
- Publication number
- JP2003332582A JP2003332582A JP2002137268A JP2002137268A JP2003332582A JP 2003332582 A JP2003332582 A JP 2003332582A JP 2002137268 A JP2002137268 A JP 2002137268A JP 2002137268 A JP2002137268 A JP 2002137268A JP 2003332582 A JP2003332582 A JP 2003332582A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate electrode
- forming
- film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6727—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having source or drain regions connected to bulk conducting substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6733—Multi-gate TFTs
- H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
Landscapes
- Thin Film Transistor (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002137268A JP2003332582A (ja) | 2002-05-13 | 2002-05-13 | 半導体装置及びその製造方法 |
| TW092112697A TWI236149B (en) | 2002-05-13 | 2003-05-09 | Semiconductor device and its manufacturing method |
| CN200510084297.5A CN100524819C (zh) | 2002-05-13 | 2003-05-13 | 半导体器件及其制造方法 |
| CN03131313.2A CN1235292C (zh) | 2002-05-13 | 2003-05-13 | 半导体器件及其制造方法 |
| US10/436,181 US6979846B2 (en) | 2002-05-13 | 2003-05-13 | Semiconductor device and manufacturing method thereof |
| US11/137,539 US7208353B2 (en) | 2002-05-13 | 2005-05-26 | Semiconductor device and manufacturing method thereof |
| US11/717,068 US7537978B2 (en) | 2002-05-13 | 2007-03-13 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002137268A JP2003332582A (ja) | 2002-05-13 | 2002-05-13 | 半導体装置及びその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003332582A true JP2003332582A (ja) | 2003-11-21 |
| JP2003332582A5 JP2003332582A5 (enExample) | 2005-08-25 |
Family
ID=29397554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002137268A Pending JP2003332582A (ja) | 2002-05-13 | 2002-05-13 | 半導体装置及びその製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (3) | US6979846B2 (enExample) |
| JP (1) | JP2003332582A (enExample) |
| CN (2) | CN1235292C (enExample) |
| TW (1) | TWI236149B (enExample) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007103551A (ja) * | 2005-10-03 | 2007-04-19 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
| JP2012039101A (ja) * | 2010-07-16 | 2012-02-23 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
| CN113053820A (zh) * | 2020-03-30 | 2021-06-29 | 台湾积体电路制造股份有限公司 | 半导体结构和形成集成电路结构的方法 |
Families Citing this family (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7687917B2 (en) * | 2002-05-08 | 2010-03-30 | Nec Electronics Corporation | Single damascene structure semiconductor device having silicon-diffused metal wiring layer |
| US6833556B2 (en) | 2002-08-12 | 2004-12-21 | Acorn Technologies, Inc. | Insulated gate field effect transistor having passivated schottky barriers to the channel |
| US7084423B2 (en) | 2002-08-12 | 2006-08-01 | Acorn Technologies, Inc. | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| US6833569B2 (en) * | 2002-12-23 | 2004-12-21 | International Business Machines Corporation | Self-aligned planar double-gate process by amorphization |
| JP2004319853A (ja) * | 2003-04-17 | 2004-11-11 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| JP3962009B2 (ja) * | 2003-12-05 | 2007-08-22 | 株式会社東芝 | 半導体装置の製造方法 |
| JP2005197462A (ja) * | 2004-01-07 | 2005-07-21 | Toshiba Corp | 半導体装置及びその製造方法 |
| US7056773B2 (en) * | 2004-04-28 | 2006-06-06 | International Business Machines Corporation | Backgated FinFET having different oxide thicknesses |
| KR100629264B1 (ko) * | 2004-07-23 | 2006-09-29 | 삼성전자주식회사 | 게이트 관통 바디 콘택을 갖는 반도체소자 및 그 제조방법 |
| JP4664631B2 (ja) * | 2004-08-05 | 2011-04-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
| KR100601995B1 (ko) * | 2005-03-02 | 2006-07-18 | 삼성전자주식회사 | 물성 변환층을 이용한 트랜지스터와 그 동작 및 제조 방법 |
| US7102166B1 (en) | 2005-04-21 | 2006-09-05 | International Business Machines Corporation | Hybrid orientation field effect transistors (FETs) |
| KR100695150B1 (ko) * | 2005-05-12 | 2007-03-14 | 삼성전자주식회사 | 금속-절연체 변환 물질을 이용한 트랜지스터 및 그 제조방법 |
| US7709313B2 (en) * | 2005-07-19 | 2010-05-04 | International Business Machines Corporation | High performance capacitors in planar back gates CMOS |
| US7573306B2 (en) * | 2006-01-31 | 2009-08-11 | Kabushiki Kaisha Toshiba | Semiconductor memory device, power supply detector and semiconductor device |
| JP5329024B2 (ja) * | 2006-06-27 | 2013-10-30 | 国立大学法人東北大学 | 半導体装置 |
| EP2050140B1 (en) * | 2006-08-04 | 2010-05-12 | Nxp B.V. | Method of manufacturing a double gate transistor |
| JP2008177273A (ja) * | 2007-01-17 | 2008-07-31 | Toshiba Corp | 半導体記憶装置及び半導体記憶装置の製造方法 |
| US7812400B2 (en) * | 2007-03-19 | 2010-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate strip with reduced thickness |
| KR100861236B1 (ko) * | 2007-04-10 | 2008-10-02 | 경북대학교 산학협력단 | 낮은 누설전류를 갖는 기둥형 전계효과트랜지스터 |
| US9564200B2 (en) * | 2007-04-10 | 2017-02-07 | Snu R&Db Foundation | Pillar-type field effect transistor having low leakage current |
| US8687417B2 (en) * | 2007-10-05 | 2014-04-01 | Globalfoundries Inc. | Electronic device and method of biasing |
| GB2459667A (en) * | 2008-04-29 | 2009-11-04 | Sharp Kk | Thin film transistor and active matrix display |
| US7863126B2 (en) * | 2008-05-15 | 2011-01-04 | International Business Machines Corporation | Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region |
| JP5550444B2 (ja) | 2010-05-17 | 2014-07-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP5531848B2 (ja) * | 2010-08-06 | 2014-06-25 | 富士通セミコンダクター株式会社 | 半導体装置、半導体集積回路装置、SRAM、Dt−MOSトランジスタの製造方法 |
| US8716800B2 (en) * | 2010-12-31 | 2014-05-06 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor structure and method for manufacturing the same |
| CN102738167B (zh) * | 2011-03-31 | 2017-02-22 | 中国科学院微电子研究所 | 半导体器件及其形成方法 |
| CN102646592B (zh) * | 2011-05-03 | 2014-12-03 | 京东方科技集团股份有限公司 | 薄膜场效应晶体管器件及其制备方法 |
| US8552500B2 (en) | 2011-05-24 | 2013-10-08 | International Business Machines Corporation | Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability |
| US8415743B2 (en) | 2011-05-24 | 2013-04-09 | International Business Machines Corporation | ETSOI CMOS with back gates |
| CN102983116B (zh) | 2011-09-07 | 2015-09-30 | 中国科学院微电子研究所 | 半导体衬底、具有该半导体衬底的集成电路及其制造方法 |
| CN103050525B (zh) | 2011-10-12 | 2015-06-17 | 中国科学院微电子研究所 | Mosfet及其制造方法 |
| KR101990622B1 (ko) | 2011-11-23 | 2019-06-18 | 아콘 테크놀로지스 인코포레이티드 | 계면 원자 단일층의 삽입에 의한 ⅳ족 반도체에 대한 금속 접점의 개선 |
| JP2013115272A (ja) * | 2011-11-29 | 2013-06-10 | Toshiba Corp | 半導体装置とその製造方法 |
| US9299802B2 (en) * | 2012-10-28 | 2016-03-29 | International Business Machines Corporation | Method to improve reliability of high-K metal gate stacks |
| US8796751B2 (en) | 2012-11-20 | 2014-08-05 | Micron Technology, Inc. | Transistors, memory cells and semiconductor constructions |
| CN103151293B (zh) * | 2013-02-25 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | 射频传输结构的形成方法 |
| US20150129967A1 (en) * | 2013-11-12 | 2015-05-14 | Stmicroelectronics International N.V. | Dual gate fd-soi transistor |
| US9800204B2 (en) * | 2014-03-19 | 2017-10-24 | Stmicroelectronics International N.V. | Integrated circuit capacitor including dual gate silicon-on-insulator transistor |
| CN104752429B (zh) * | 2015-04-17 | 2017-10-27 | 上海华虹宏力半导体制造有限公司 | 绝缘体上硅射频开关器件结构 |
| US9620611B1 (en) | 2016-06-17 | 2017-04-11 | Acorn Technology, Inc. | MIS contact structure with metal oxide conductor |
| CN107527800B (zh) * | 2016-06-22 | 2021-05-11 | 无锡华润上华科技有限公司 | 沟槽栅极结构及其制造方法 |
| DE112017005855T5 (de) | 2016-11-18 | 2019-08-01 | Acorn Technologies, Inc. | Nanodrahttransistor mit Source und Drain induziert durch elektrische Kontakte mit negativer Schottky-Barrierenhöhe |
| JP2018164055A (ja) * | 2017-03-27 | 2018-10-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US10903332B2 (en) | 2018-08-22 | 2021-01-26 | International Business Machines Corporation | Fully depleted SOI transistor with a buried ferroelectric layer in back-gate |
| US11476363B2 (en) * | 2019-04-10 | 2022-10-18 | United Microelectronics Corp. | Semiconductor device and method of fabricating the same |
| US12446253B2 (en) * | 2022-09-19 | 2025-10-14 | Globalfoundries U.S. Inc. | Field effect transistor with adjustable effective gate length |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3488730B2 (ja) | 1993-11-05 | 2004-01-19 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
| KR970008576A (ko) | 1995-07-07 | 1997-02-24 | 에프. 피. 터핀 | Soi 기판 상의 cmos 집적회로 및 이의 형성 방법 |
| JPH10163342A (ja) | 1996-12-04 | 1998-06-19 | Sharp Corp | 半導体装置 |
| JP3107024B2 (ja) * | 1997-12-09 | 2000-11-06 | 日本電気株式会社 | 薄膜トランジスタの製造方法 |
| JP3762136B2 (ja) | 1998-04-24 | 2006-04-05 | 株式会社東芝 | 半導体装置 |
| US6072217A (en) * | 1998-06-11 | 2000-06-06 | Sun Microsystems, Inc. | Tunable threshold SOI device using isolated well structure for back gate |
| KR100349768B1 (ko) * | 1998-06-30 | 2002-08-24 | 샤프 가부시키가이샤 | 반도체 장치 및 그의 제조방법 |
| EP0991118B1 (en) * | 1998-10-02 | 2006-01-18 | STMicroelectronics S.r.l. | Method for realizing a multilevel ROM memory in a dual gate CMOS process and corresponding ROM memory cell |
| FR2789519B1 (fr) * | 1999-02-05 | 2003-03-28 | Commissariat Energie Atomique | Transistor mos a tension de seuil dynamique equipe d'un limiteur de courant, et procede de realisation d'un tel transistor |
| JP3174852B2 (ja) | 1999-03-05 | 2001-06-11 | 東京大学長 | しきい値電圧を制御しうるmosトランジスタを有する回路及びしきい値電圧制御方法 |
| JP4270719B2 (ja) | 1999-06-30 | 2009-06-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
| JP2001044441A (ja) | 1999-07-29 | 2001-02-16 | Sony Corp | 完全空乏soi型半導体装置及び集積回路 |
| JP4074051B2 (ja) | 1999-08-31 | 2008-04-09 | 株式会社東芝 | 半導体基板およびその製造方法 |
| US6566177B1 (en) * | 1999-10-25 | 2003-05-20 | International Business Machines Corporation | Silicon-on-insulator vertical array device trench capacitor DRAM |
| US6420767B1 (en) * | 2000-06-28 | 2002-07-16 | Advanced Micro Devices, Inc. | Capacitively coupled DTMOS on SOI |
| JP2002110994A (ja) | 2000-09-28 | 2002-04-12 | Toshiba Corp | 半導体装置及びその製造方法 |
| JP3624822B2 (ja) * | 2000-11-22 | 2005-03-02 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
| US6433609B1 (en) * | 2001-11-19 | 2002-08-13 | International Business Machines Corporation | Double-gate low power SOI active clamp network for single power supply and multiple power supply applications |
| US6645796B2 (en) * | 2001-11-21 | 2003-11-11 | International Business Machines Corporation | Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices |
-
2002
- 2002-05-13 JP JP2002137268A patent/JP2003332582A/ja active Pending
-
2003
- 2003-05-09 TW TW092112697A patent/TWI236149B/zh active
- 2003-05-13 US US10/436,181 patent/US6979846B2/en not_active Expired - Fee Related
- 2003-05-13 CN CN03131313.2A patent/CN1235292C/zh not_active Expired - Fee Related
- 2003-05-13 CN CN200510084297.5A patent/CN100524819C/zh not_active Expired - Fee Related
-
2005
- 2005-05-26 US US11/137,539 patent/US7208353B2/en not_active Expired - Fee Related
-
2007
- 2007-03-13 US US11/717,068 patent/US7537978B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007103551A (ja) * | 2005-10-03 | 2007-04-19 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
| JP2012039101A (ja) * | 2010-07-16 | 2012-02-23 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
| CN113053820A (zh) * | 2020-03-30 | 2021-06-29 | 台湾积体电路制造股份有限公司 | 半导体结构和形成集成电路结构的方法 |
| US12484298B2 (en) | 2020-03-30 | 2025-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with self-aligned backside power rail |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200403851A (en) | 2004-03-01 |
| US20030209761A1 (en) | 2003-11-13 |
| CN1722466A (zh) | 2006-01-18 |
| TWI236149B (en) | 2005-07-11 |
| US6979846B2 (en) | 2005-12-27 |
| CN1235292C (zh) | 2006-01-04 |
| US7208353B2 (en) | 2007-04-24 |
| CN1461058A (zh) | 2003-12-10 |
| US20070176237A1 (en) | 2007-08-02 |
| CN100524819C (zh) | 2009-08-05 |
| US20050253196A1 (en) | 2005-11-17 |
| US7537978B2 (en) | 2009-05-26 |
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