JP2003242799A5 - - Google Patents

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Publication number
JP2003242799A5
JP2003242799A5 JP2002034652A JP2002034652A JP2003242799A5 JP 2003242799 A5 JP2003242799 A5 JP 2003242799A5 JP 2002034652 A JP2002034652 A JP 2002034652A JP 2002034652 A JP2002034652 A JP 2002034652A JP 2003242799 A5 JP2003242799 A5 JP 2003242799A5
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JP
Japan
Prior art keywords
evaluation
register
mode
circuit
debug function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002034652A
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English (en)
Japanese (ja)
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JP2003242799A (ja
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Publication date
Application filed filed Critical
Priority to JP2002034652A priority Critical patent/JP2003242799A/ja
Priority claimed from JP2002034652A external-priority patent/JP2003242799A/ja
Priority to US10/359,707 priority patent/US6865705B2/en
Publication of JP2003242799A publication Critical patent/JP2003242799A/ja
Publication of JP2003242799A5 publication Critical patent/JP2003242799A5/ja
Pending legal-status Critical Current

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JP2002034652A 2002-02-12 2002-02-12 半導体集積回路 Pending JP2003242799A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002034652A JP2003242799A (ja) 2002-02-12 2002-02-12 半導体集積回路
US10/359,707 US6865705B2 (en) 2002-02-12 2003-02-07 Semiconductor integrated circuit device capable of switching mode for trimming internal circuitry through JTAG boundary scan method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002034652A JP2003242799A (ja) 2002-02-12 2002-02-12 半導体集積回路

Publications (2)

Publication Number Publication Date
JP2003242799A JP2003242799A (ja) 2003-08-29
JP2003242799A5 true JP2003242799A5 (enExample) 2005-08-25

Family

ID=27654924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002034652A Pending JP2003242799A (ja) 2002-02-12 2002-02-12 半導体集積回路

Country Status (2)

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US (1) US6865705B2 (enExample)
JP (1) JP2003242799A (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4542852B2 (ja) * 2004-08-20 2010-09-15 株式会社アドバンテスト 試験装置及び試験方法
JP4646604B2 (ja) * 2004-11-11 2011-03-09 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US20060218455A1 (en) * 2005-03-23 2006-09-28 Silicon Design Solution, Inc. Integrated circuit margin stress test system
JP4825436B2 (ja) 2005-03-29 2011-11-30 ルネサスエレクトロニクス株式会社 半導体記憶装置及び半導体装置
KR100721581B1 (ko) * 2005-09-29 2007-05-23 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자
US20070285105A1 (en) * 2006-06-02 2007-12-13 Steven Wayne Bergstedt Methods and Apparatuses for Trimming Circuits
JP5057744B2 (ja) * 2006-10-20 2012-10-24 株式会社東芝 半導体集積回路装置
JP5029155B2 (ja) * 2007-06-11 2012-09-19 富士通セミコンダクター株式会社 半導体集積回路及びコード割り当て方法
US7712003B2 (en) * 2007-08-15 2010-05-04 International Business Machines Corporation Methodology and system to set JTAG interface
US7668037B2 (en) * 2007-11-06 2010-02-23 International Business Machines Corporation Storage array including a local clock buffer with programmable timing
US7882407B2 (en) * 2007-12-17 2011-02-01 Qualcomm Incorporated Adapting word line pulse widths in memory systems
US20090234767A1 (en) * 2008-03-12 2009-09-17 Steidlmayer J Peter Cost-based financial product
US7787314B2 (en) * 2008-09-11 2010-08-31 Altera Corporation Dynamic real-time delay characterization and configuration
KR101716714B1 (ko) 2010-04-01 2017-03-16 삼성전자주식회사 클럭 신호에 동기하는 반도체 메모리 장치
JP5343916B2 (ja) 2010-04-16 2013-11-13 富士通セミコンダクター株式会社 半導体メモリ
US9223714B2 (en) 2013-03-15 2015-12-29 Intel Corporation Instruction boundary prediction for variable length instruction set
JP5770885B2 (ja) * 2014-05-02 2015-08-26 スパンション エルエルシー 半導体メモリ

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1131398A (ja) * 1997-07-08 1999-02-02 Hitachi Ltd 半導体集積回路装置
JPH11289322A (ja) 1998-04-03 1999-10-19 Hitachi Ltd 半導体集積回路装置および電子装置
US5970005A (en) * 1998-04-27 1999-10-19 Ict, Inc. Testing structure and method for high density PLDs which have flexible logic built-in blocks
JP3560836B2 (ja) * 1998-12-14 2004-09-02 株式会社東芝 半導体装置
JP4627865B2 (ja) * 2000-11-07 2011-02-09 ルネサスエレクトロニクス株式会社 半導体集積回路装置

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