JP2003242799A - 半導体集積回路 - Google Patents

半導体集積回路

Info

Publication number
JP2003242799A
JP2003242799A JP2002034652A JP2002034652A JP2003242799A JP 2003242799 A JP2003242799 A JP 2003242799A JP 2002034652 A JP2002034652 A JP 2002034652A JP 2002034652 A JP2002034652 A JP 2002034652A JP 2003242799 A JP2003242799 A JP 2003242799A
Authority
JP
Japan
Prior art keywords
evaluation
register
circuit
trimming
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002034652A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003242799A5 (enExample
Inventor
Masahiko Tomizawa
雅彦 富沢
Masahiko Nishiyama
雅彦 西山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP2002034652A priority Critical patent/JP2003242799A/ja
Priority to US10/359,707 priority patent/US6865705B2/en
Publication of JP2003242799A publication Critical patent/JP2003242799A/ja
Publication of JP2003242799A5 publication Critical patent/JP2003242799A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP2002034652A 2002-02-12 2002-02-12 半導体集積回路 Pending JP2003242799A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002034652A JP2003242799A (ja) 2002-02-12 2002-02-12 半導体集積回路
US10/359,707 US6865705B2 (en) 2002-02-12 2003-02-07 Semiconductor integrated circuit device capable of switching mode for trimming internal circuitry through JTAG boundary scan method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002034652A JP2003242799A (ja) 2002-02-12 2002-02-12 半導体集積回路

Publications (2)

Publication Number Publication Date
JP2003242799A true JP2003242799A (ja) 2003-08-29
JP2003242799A5 JP2003242799A5 (enExample) 2005-08-25

Family

ID=27654924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002034652A Pending JP2003242799A (ja) 2002-02-12 2002-02-12 半導体集積回路

Country Status (2)

Country Link
US (1) US6865705B2 (enExample)
JP (1) JP2003242799A (enExample)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006018947A1 (ja) * 2004-08-20 2006-02-23 Advantest Corporation 試験装置及び試験方法
JP2006277808A (ja) * 2005-03-29 2006-10-12 Renesas Technology Corp 半導体記憶装置及び半導体装置
JP2008103047A (ja) * 2006-10-20 2008-05-01 Toshiba Corp 半導体集積回路装置
JP2011503766A (ja) * 2007-11-06 2011-01-27 インターナショナル・ビジネス・マシーンズ・コーポレーション 記憶回路およびストレージ・アレイのタイミング特性を測定するための方法（プログラマブル・タイミングを備えたローカル・クロック・バッファを含むストレージ・アレイ）
JP2012502407A (ja) * 2008-09-11 2012-01-26 アルテラ・コ―ポレ―シヨン 動的、かつリアルタイムなディレイ特徴化、及び設定
JP2014160537A (ja) * 2014-05-02 2014-09-04 Spansion Llc 半導体メモリ
US9224487B2 (en) 2010-04-16 2015-12-29 Cypress Semiconductor Corporation Semiconductor memory read and write access

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4646604B2 (ja) * 2004-11-11 2011-03-09 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US20060218455A1 (en) * 2005-03-23 2006-09-28 Silicon Design Solution, Inc. Integrated circuit margin stress test system
KR100721581B1 (ko) * 2005-09-29 2007-05-23 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자
US20070285105A1 (en) * 2006-06-02 2007-12-13 Steven Wayne Bergstedt Methods and Apparatuses for Trimming Circuits
JP5029155B2 (ja) * 2007-06-11 2012-09-19 富士通セミコンダクター株式会社 半導体集積回路及びコード割り当て方法
US7712003B2 (en) * 2007-08-15 2010-05-04 International Business Machines Corporation Methodology and system to set JTAG interface
US7882407B2 (en) * 2007-12-17 2011-02-01 Qualcomm Incorporated Adapting word line pulse widths in memory systems
US20090234767A1 (en) * 2008-03-12 2009-09-17 Steidlmayer J Peter Cost-based financial product
KR101716714B1 (ko) 2010-04-01 2017-03-16 삼성전자주식회사 클럭 신호에 동기하는 반도체 메모리 장치
US9223714B2 (en) 2013-03-15 2015-12-29 Intel Corporation Instruction boundary prediction for variable length instruction set

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1131398A (ja) * 1997-07-08 1999-02-02 Hitachi Ltd 半導体集積回路装置
JPH11289322A (ja) 1998-04-03 1999-10-19 Hitachi Ltd 半導体集積回路装置および電子装置
US5970005A (en) * 1998-04-27 1999-10-19 Ict, Inc. Testing structure and method for high density PLDs which have flexible logic built-in blocks
JP3560836B2 (ja) * 1998-12-14 2004-09-02 株式会社東芝 半導体装置
JP4627865B2 (ja) * 2000-11-07 2011-02-09 ルネサスエレクトロニクス株式会社 半導体集積回路装置

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006018947A1 (ja) * 2004-08-20 2006-02-23 Advantest Corporation 試験装置及び試験方法
JP2006059477A (ja) * 2004-08-20 2006-03-02 Advantest Corp 試験装置及び試験方法
JP2006277808A (ja) * 2005-03-29 2006-10-12 Renesas Technology Corp 半導体記憶装置及び半導体装置
US7269086B2 (en) 2005-03-29 2007-09-11 Renesas Technology Corp. Semiconductor memory device and semiconductor device
US7426152B2 (en) 2005-03-29 2008-09-16 Renesas Technology Corp. Semiconductor memory device and semiconductor device
JP2008103047A (ja) * 2006-10-20 2008-05-01 Toshiba Corp 半導体集積回路装置
JP2011503766A (ja) * 2007-11-06 2011-01-27 インターナショナル・ビジネス・マシーンズ・コーポレーション 記憶回路およびストレージ・アレイのタイミング特性を測定するための方法（プログラマブル・タイミングを備えたローカル・クロック・バッファを含むストレージ・アレイ）
JP2012502407A (ja) * 2008-09-11 2012-01-26 アルテラ・コ―ポレ―シヨン 動的、かつリアルタイムなディレイ特徴化、及び設定
US9224487B2 (en) 2010-04-16 2015-12-29 Cypress Semiconductor Corporation Semiconductor memory read and write access
JP2014160537A (ja) * 2014-05-02 2014-09-04 Spansion Llc 半導体メモリ

Also Published As

Publication number Publication date
US20030151962A1 (en) 2003-08-14
US6865705B2 (en) 2005-03-08

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