JP2005531876A5 - - Google Patents

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Publication number
JP2005531876A5
JP2005531876A5 JP2004517527A JP2004517527A JP2005531876A5 JP 2005531876 A5 JP2005531876 A5 JP 2005531876A5 JP 2004517527 A JP2004517527 A JP 2004517527A JP 2004517527 A JP2004517527 A JP 2004517527A JP 2005531876 A5 JP2005531876 A5 JP 2005531876A5
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JP
Japan
Prior art keywords
toggle
array
predetermined
value
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004517527A
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English (en)
Japanese (ja)
Other versions
JP4359561B2 (ja
JP2005531876A (ja
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Publication date
Priority claimed from US10/186,141 external-priority patent/US6693824B2/en
Application filed filed Critical
Publication of JP2005531876A publication Critical patent/JP2005531876A/ja
Publication of JP2005531876A5 publication Critical patent/JP2005531876A5/ja
Application granted granted Critical
Publication of JP4359561B2 publication Critical patent/JP4359561B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2004517527A 2002-06-28 2003-04-29 トグルメモリに書き込む回路および方法 Expired - Fee Related JP4359561B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/186,141 US6693824B2 (en) 2002-06-28 2002-06-28 Circuit and method of writing a toggle memory
PCT/US2003/013179 WO2004003922A1 (en) 2002-06-28 2003-04-29 Circuit and method of writing a toggle memory

Publications (3)

Publication Number Publication Date
JP2005531876A JP2005531876A (ja) 2005-10-20
JP2005531876A5 true JP2005531876A5 (enExample) 2006-06-22
JP4359561B2 JP4359561B2 (ja) 2009-11-04

Family

ID=29779824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004517527A Expired - Fee Related JP4359561B2 (ja) 2002-06-28 2003-04-29 トグルメモリに書き込む回路および方法

Country Status (10)

Country Link
US (1) US6693824B2 (enExample)
EP (1) EP1518246B1 (enExample)
JP (1) JP4359561B2 (enExample)
KR (1) KR100943112B1 (enExample)
CN (1) CN100470665C (enExample)
AT (1) ATE333138T1 (enExample)
AU (1) AU2003231170A1 (enExample)
DE (1) DE60306782T2 (enExample)
TW (1) TWI307887B (enExample)
WO (1) WO2004003922A1 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6842365B1 (en) * 2003-09-05 2005-01-11 Freescale Semiconductor, Inc. Write driver for a magnetoresistive memory
US7286378B2 (en) * 2003-11-04 2007-10-23 Micron Technology, Inc. Serial transistor-cell array architecture
US7613868B2 (en) * 2004-06-09 2009-11-03 Headway Technologies, Inc. Method and system for optimizing the number of word line segments in a segmented MRAM array
JP2006031795A (ja) * 2004-07-14 2006-02-02 Renesas Technology Corp 不揮発性半導体記憶装置
JP2006065986A (ja) * 2004-08-27 2006-03-09 Fujitsu Ltd 磁気抵抗メモリおよび磁気抵抗メモリ書き込み方法
JP4012196B2 (ja) * 2004-12-22 2007-11-21 株式会社東芝 磁気ランダムアクセスメモリのデータ書き込み方法
US7543211B2 (en) * 2005-01-31 2009-06-02 Everspin Technologies, Inc. Toggle memory burst
US7646628B2 (en) * 2005-02-09 2010-01-12 Nec Corporation Toggle magnetic random access memory and write method of toggle magnetic random access memory
JP5035620B2 (ja) * 2005-09-14 2012-09-26 日本電気株式会社 磁気ランダムアクセスメモリの波形整形回路
US7569902B2 (en) * 2005-10-28 2009-08-04 Board Of Trustees Of The University Of Alabama Enhanced toggle-MRAM memory device
US7577017B2 (en) * 2006-01-20 2009-08-18 Industrial Technology Research Institute High-bandwidth magnetoresistive random access memory devices and methods of operation thereof
US7746686B2 (en) * 2006-04-21 2010-06-29 Honeywell International Inc. Partitioned random access and read only memory
US8111544B2 (en) * 2009-02-23 2012-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Programming MRAM cells using probability write
US9613675B2 (en) 2013-12-14 2017-04-04 Qualcomm Incorporated System and method to perform low power memory operations
JP6423084B2 (ja) * 2014-08-29 2018-11-14 シーメンス アクチエンゲゼルシヤフトＳｉｅｍｅｎｓ Ａｋｔｉｅｎｇｅｓｅｌｌｓｃｈａｆｔ ガスタービンエンジン用の制御された収束圧縮機流路
CN204878059U (zh) 2014-12-17 2015-12-16 依必安-派特穆尔芬根股份有限两合公司 一种叶片及风机叶轮
KR101976045B1 (ko) * 2016-08-30 2019-05-09 에스케이하이닉스 주식회사 쓰기 동작시 상태 전환 인식이 가능한 자기 저항 메모리 장치 및 이에 있어서 읽기 및 쓰기 동작 방법
US11275356B2 (en) * 2018-11-22 2022-03-15 Mitsubishi Electric Corporation Input-output control unit, PLC and data control method

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4763305A (en) 1985-11-27 1988-08-09 Motorola, Inc. Intelligent write in an EEPROM with data and erase check
US6256224B1 (en) * 2000-05-03 2001-07-03 Hewlett-Packard Co Write circuit for large MRAM arrays
US5946227A (en) 1998-07-20 1999-08-31 Motorola, Inc. Magnetoresistive random access memory with shared word and digit lines
US5953248A (en) 1998-07-20 1999-09-14 Motorola, Inc. Low switching field magnetic tunneling junction for high density arrays
US6111781A (en) 1998-08-03 2000-08-29 Motorola, Inc. Magnetic random access memory array divided into a plurality of memory banks
DE19853447A1 (de) * 1998-11-19 2000-05-25 Siemens Ag Magnetischer Speicher
KR100450466B1 (ko) * 1999-01-13 2004-09-30 인피니언 테크놀로지스 아게 Ｍｒａｍ용 판독-/기록 아키텍처
US6185143B1 (en) 2000-02-04 2001-02-06 Hewlett-Packard Company Magnetic random access memory (MRAM) device including differential sense amplifiers
US6191989B1 (en) 2000-03-07 2001-02-20 International Business Machines Corporation Current sensing amplifier
US6272041B1 (en) 2000-08-28 2001-08-07 Motorola, Inc. MTJ MRAM parallel-parallel architecture
JP4149647B2 (ja) * 2000-09-28 2008-09-10 株式会社東芝 半導体記憶装置及びその製造方法
US6335890B1 (en) 2000-11-01 2002-01-01 International Business Machines Corporation Segmented write line architecture for writing magnetic random access memories
US6418046B1 (en) * 2001-01-30 2002-07-09 Motorola, Inc. MRAM architecture and system
DE10107380C1 (de) * 2001-02-16 2002-07-25 Infineon Technologies Ag Verfahren zum Beschreiben magnetoresistiver Speicherzellen und mit diesem Verfahren beschreibbarer magnetoresistiver Speicher

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