JP5320511B2 - マルチレベル・ライトワンス・メモリ・セルを備える書き換え可能メモリデバイス - Google Patents
マルチレベル・ライトワンス・メモリ・セルを備える書き換え可能メモリデバイス Download PDFInfo
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- JP5320511B2 JP5320511B2 JP2012544515A JP2012544515A JP5320511B2 JP 5320511 B2 JP5320511 B2 JP 5320511B2 JP 2012544515 A JP2012544515 A JP 2012544515A JP 2012544515 A JP2012544515 A JP 2012544515A JP 5320511 B2 JP5320511 B2 JP 5320511B2
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- Prior art keywords
- memory
- memory cells
- memory cell
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- read
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5646—Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
Description
Claims (10)
- 複数のマルチレベル・ライトワンス・メモリ・セルを備えるメモリアレイであって、各メモリセルは、複数の抵抗レベルの1つにプログラム可能である、メモリアレイと、
メモリアレイと通信する回路であって、該回路は、
メモリアレイからメモリセルのグループを選択し、
メモリセルのグループと関連しており、メモリセルのグループが書き込まれた回数を示す1組のフラグビットを読み出し、
メモリセルのグループが書き込まれた回数に対する適切な閾値読出しレベル及び読出し電圧を選択し、
メモリセルのグループ内の各メモリセルに対して、選択された閾値読出しレベルに基づいて、読出し電圧が印加されたメモリセルを、プログラムされていない単一ビットメモリセル又はプログラムされた単一ビットメモリセルとして読み出す、
ように構成される、前記メモリアレイと通信する回路と、
を備える、メモリデバイス。 - 回路は、さらに、
メモリセルのグループをプログラムし、
メモリセルのグループが書き込まれた回数の増加を示すために、第2の組のフラグビットをプログラムする、
ように構成される、請求項1に記載のメモリデバイス。 - メモリセルのグループは、プログラミング前に読み出され、抵抗の調整を必要とするメモリセルのみがプログラムされる、請求項2に記載のメモリデバイス。
- 1組のフラグビットを記憶するメモリセルは、一度書き込まれただけである、請求項1に記載のメモリデバイス。
- 回路は、メモリセルの導電性パスを破壊してさらに高い抵抗率レベルを形成するために、パルスを印加するようにさらに機能する、請求項1に記載のメモリデバイス。
- マルチレベル・ライトワンス・メモリ・セルを読み出す方法であって、
複数のマルチレベル・ライトワンス・メモリ・セルを備えるメモリアレイからメモリセルのグループを選択するステップであって、各メモリセルは、複数の抵抗率レベルの1つにプログラム可能であるステップと、
メモリセルのグループに関連する1組のフラグビットを読み出すステップであって、1組のフラグビットは、メモリセルのグループが書き込まれた回数を示すステップと、
メモリセルのグループが書き込まれた回数に対する適切な閾値読出しレベル及び読出し電圧を選択するステップと、
メモリセルのグループ内の各メモリセルに対して、選択された閾値読出しレベルに基づいて、読出し電圧が印加されたメモリセルを、プログラムされていない単一ビットメモリセル又はプログラムされた単一ビットメモリセルとして読み出すステップと、
を備える、方法。 - メモリセルのグループをプログラムするステップと、
メモリセルのグループが書き込まれた回数の増加を示すために、第2の組のフラグビットをプログラムするステップと、
をさらに備える、請求項6に記載の方法。 - メモリセルのグループはプログラミング前に読み出され、抵抗の調整を必要とするメモリセルのみがプログラムされる、請求項7に記載の方法。
- 1組のフラグビットを記憶するメモリセルは一度書き込まれただけである、請求項6に記載の方法。
- メモリセルの導電性パスを破壊してさらに高い抵抗率レベルを形成するために、パルスを印加するステップをさらに備える、請求項6に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/643,561 | 2009-12-21 | ||
US12/643,561 US8149607B2 (en) | 2009-12-21 | 2009-12-21 | Rewritable memory device with multi-level, write-once memory cells |
PCT/US2010/055547 WO2011078917A1 (en) | 2009-12-21 | 2010-11-05 | Rewritable memory device with multi-level, write-once memory cells |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013515330A JP2013515330A (ja) | 2013-05-02 |
JP5320511B2 true JP5320511B2 (ja) | 2013-10-23 |
Family
ID=43417069
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012544515A Expired - Fee Related JP5320511B2 (ja) | 2009-12-21 | 2010-11-05 | マルチレベル・ライトワンス・メモリ・セルを備える書き換え可能メモリデバイス |
Country Status (7)
Country | Link |
---|---|
US (1) | US8149607B2 (ja) |
EP (1) | EP2517209A1 (ja) |
JP (1) | JP5320511B2 (ja) |
KR (1) | KR101213982B1 (ja) |
CN (1) | CN102656640A (ja) |
TW (1) | TW201135730A (ja) |
WO (1) | WO2011078917A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8588009B2 (en) * | 2011-09-28 | 2013-11-19 | International Business Machines Corporation | Circuit for memory cell recovery |
US9025391B2 (en) * | 2012-11-27 | 2015-05-05 | Infineon Technologies Ag | Circuit arrangement and method for operating a circuit arrangement |
US9312017B2 (en) * | 2014-01-15 | 2016-04-12 | Apple Inc. | Storage in charge-trap memory structures using additional electrically-charged regions |
US9672928B2 (en) | 2015-11-10 | 2017-06-06 | Samsung Electronics Co., Ltd. | Method and apparatus for estimating read levels of nonvolatile memory and for programming pilot signals used for such estimation |
KR102406664B1 (ko) | 2016-02-24 | 2022-06-08 | 삼성전자주식회사 | Otp 메모리 및 그것의 데이터 기입 방법 |
KR20210024269A (ko) | 2019-08-21 | 2021-03-05 | 삼성전자주식회사 | 빠른 읽기 페이지를 포함하는 불휘발성 메모리 장치 및 이를 포함하는 스토리지 장치 |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69626654T2 (de) * | 1995-09-29 | 2004-02-05 | Intel Corporation, Santa Clara | Mehrfaches schreiben pro einfachem löschen in nichtflüchtigem speicher |
JP3114630B2 (ja) * | 1996-10-03 | 2000-12-04 | 日本電気株式会社 | 不揮発性半導体メモリおよび書込み読出し方法 |
JP2000348493A (ja) * | 1999-06-03 | 2000-12-15 | Fujitsu Ltd | 不揮発性メモリ回路 |
US7062602B1 (en) * | 2001-04-09 | 2006-06-13 | Matrix Semiconductor, Inc. | Method for reading data in a write-once memory device using a write-many file system |
US6490218B1 (en) * | 2001-08-17 | 2002-12-03 | Matrix Semiconductor, Inc. | Digital memory method and system for storing multiple bit digital data |
US6456528B1 (en) * | 2001-09-17 | 2002-09-24 | Sandisk Corporation | Selective operation of a multi-state non-volatile memory system in a binary mode |
US6901549B2 (en) * | 2001-12-14 | 2005-05-31 | Matrix Semiconductor, Inc. | Method for altering a word stored in a write-once memory device |
US7800933B2 (en) * | 2005-09-28 | 2010-09-21 | Sandisk 3D Llc | Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance |
US7800932B2 (en) * | 2005-09-28 | 2010-09-21 | Sandisk 3D Llc | Memory cell comprising switchable semiconductor memory element with trimmable resistance |
US7051251B2 (en) * | 2002-12-20 | 2006-05-23 | Matrix Semiconductor, Inc. | Method for storing data in a write-once memory array using a write-many file system |
US7132350B2 (en) * | 2003-07-21 | 2006-11-07 | Macronix International Co., Ltd. | Method for manufacturing a programmable eraseless memory |
EP1503384A3 (en) | 2003-07-21 | 2007-07-18 | Macronix International Co., Ltd. | Method of programming memory |
CN100524763C (zh) * | 2003-08-15 | 2009-08-05 | 旺宏电子股份有限公司 | 集成电路、存储单元及其制造方法、存储单元的编程方法 |
US7177183B2 (en) * | 2003-09-30 | 2007-02-13 | Sandisk 3D Llc | Multiple twin cell non-volatile memory array and logic block structure and method therefor |
US7082490B2 (en) * | 2003-10-20 | 2006-07-25 | Atmel Corporation | Method and system for enhancing the endurance of memory cells |
US6996004B1 (en) * | 2003-11-04 | 2006-02-07 | Advanced Micro Devices, Inc. | Minimization of FG-FG coupling in flash memory |
US7196570B2 (en) | 2004-05-05 | 2007-03-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multiple-time programmable resistance circuit |
US20060067117A1 (en) * | 2004-09-29 | 2006-03-30 | Matrix Semiconductor, Inc. | Fuse memory cell comprising a diode, the diode serving as the fuse element |
US7272041B2 (en) | 2005-06-30 | 2007-09-18 | Intel Corporation | Memory array with pseudo single bit memory cell and method |
US7453755B2 (en) * | 2005-07-01 | 2008-11-18 | Sandisk 3D Llc | Memory cell with high-K antifuse for reverse bias programming |
US7450414B2 (en) * | 2006-07-31 | 2008-11-11 | Sandisk 3D Llc | Method for using a mixed-use memory array |
US7486537B2 (en) * | 2006-07-31 | 2009-02-03 | Sandisk 3D Llc | Method for using a mixed-use memory array with different data states |
US7903447B2 (en) | 2006-12-13 | 2011-03-08 | Macronix International Co., Ltd. | Method, apparatus and computer program product for read before programming process on programmable resistive memory cell |
TWI346948B (en) * | 2007-06-26 | 2011-08-11 | Quanta Storage Inc | Writing method for an optical disk drive |
US20090086521A1 (en) * | 2007-09-28 | 2009-04-02 | Herner S Brad | Multiple antifuse memory cells and methods to form, program, and sense the same |
US7846782B2 (en) | 2007-09-28 | 2010-12-07 | Sandisk 3D Llc | Diode array and method of making thereof |
JP2009252255A (ja) * | 2008-04-01 | 2009-10-29 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
KR101412974B1 (ko) * | 2008-05-28 | 2014-06-30 | 삼성전자주식회사 | 메모리 장치 및 메모리 프로그래밍 방법 |
-
2009
- 2009-12-21 US US12/643,561 patent/US8149607B2/en active Active
-
2010
- 2010-11-05 WO PCT/US2010/055547 patent/WO2011078917A1/en active Application Filing
- 2010-11-05 KR KR1020127015984A patent/KR101213982B1/ko not_active IP Right Cessation
- 2010-11-05 EP EP10782466A patent/EP2517209A1/en not_active Withdrawn
- 2010-11-05 JP JP2012544515A patent/JP5320511B2/ja not_active Expired - Fee Related
- 2010-11-05 CN CN2010800567163A patent/CN102656640A/zh active Pending
- 2010-12-07 TW TW099142643A patent/TW201135730A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
WO2011078917A1 (en) | 2011-06-30 |
JP2013515330A (ja) | 2013-05-02 |
EP2517209A1 (en) | 2012-10-31 |
TW201135730A (en) | 2011-10-16 |
KR101213982B1 (ko) | 2012-12-20 |
US8149607B2 (en) | 2012-04-03 |
US20110149631A1 (en) | 2011-06-23 |
CN102656640A (zh) | 2012-09-05 |
KR20120080665A (ko) | 2012-07-17 |
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