JPH1116394A5 - - Google Patents

Info

Publication number
JPH1116394A5
JPH1116394A5 JP1998153922A JP15392298A JPH1116394A5 JP H1116394 A5 JPH1116394 A5 JP H1116394A5 JP 1998153922 A JP1998153922 A JP 1998153922A JP 15392298 A JP15392298 A JP 15392298A JP H1116394 A5 JPH1116394 A5 JP H1116394A5
Authority
JP
Japan
Prior art keywords
memory
value
row
cell
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1998153922A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1116394A (ja
Filing date
Publication date
Priority claimed from US08/858,271 external-priority patent/US5903505A/en
Application filed filed Critical
Publication of JPH1116394A publication Critical patent/JPH1116394A/ja
Publication of JPH1116394A5 publication Critical patent/JPH1116394A5/ja
Pending legal-status Critical Current

Links

JP10153922A 1997-05-19 1998-05-19 サブスレッショルド漏れ電流が最悪の条件に設定され得る、メモリのリフレッシュ動作を検査する方法 Pending JPH1116394A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/858,271 US5903505A (en) 1997-05-19 1997-05-19 Method of testing memory refresh operations wherein subthreshold leakage current may be set to near worst-case conditions
US858,271 1997-05-19

Publications (2)

Publication Number Publication Date
JPH1116394A JPH1116394A (ja) 1999-01-22
JPH1116394A5 true JPH1116394A5 (enExample) 2005-10-06

Family

ID=25327924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10153922A Pending JPH1116394A (ja) 1997-05-19 1998-05-19 サブスレッショルド漏れ電流が最悪の条件に設定され得る、メモリのリフレッシュ動作を検査する方法

Country Status (2)

Country Link
US (1) US5903505A (enExample)
JP (1) JPH1116394A (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10199293A (ja) * 1996-12-27 1998-07-31 Canon Inc メモリのデータ保持特性の試験方法
US6167544A (en) * 1998-08-19 2000-12-26 Stmicroelectronics, Inc. Method and apparatus for testing dynamic random access memory
KR100548541B1 (ko) * 1999-06-30 2006-02-02 주식회사 하이닉스반도체 반도체 소자의 리프레쉬 특성을 측정하기 위한 테스트 장치 및방법
DE10004958A1 (de) * 2000-02-04 2001-08-09 Infineon Technologies Ag Verfahren zum Testen der Refresheinrichtung eines Informationsspeichers
JP2002133876A (ja) * 2000-10-23 2002-05-10 Hitachi Ltd 半導体記憶装置
US6728156B2 (en) * 2002-03-11 2004-04-27 International Business Machines Corporation Memory array system
US6947348B2 (en) * 2003-07-15 2005-09-20 International Business Machines Corporation Gain cell memory having read cycle interlock

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5149641A (en) * 1974-10-26 1976-04-30 Nippon Electric Co Kiokusochino shikenhoho
JPS51139221A (en) * 1975-05-28 1976-12-01 Hitachi Ltd Method of and apparatus for measuring reflesh period of mis dynamic ty pe memory
JPS57127992A (en) * 1981-01-28 1982-08-09 Nec Corp Test method for memory
JP2606669B2 (ja) * 1994-09-22 1997-05-07 日本電気株式会社 半導体記憶装置

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