JP2001148199A - 自己テスト回路内蔵半導体記憶装置 - Google Patents

自己テスト回路内蔵半導体記憶装置

Info

Publication number
JP2001148199A
JP2001148199A JP32982299A JP32982299A JP2001148199A JP 2001148199 A JP2001148199 A JP 2001148199A JP 32982299 A JP32982299 A JP 32982299A JP 32982299 A JP32982299 A JP 32982299A JP 2001148199 A JP2001148199 A JP 2001148199A
Authority
JP
Japan
Prior art keywords
test
data
test circuit
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32982299A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001148199A5 (enExample
Inventor
Tetsushi Tanizaki
哲志 谷▲崎▼
Kazufumi Sugiura
和史 杉浦
Masami Nakajima
雅美 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Engineering Corp
Mitsubishi Electric Corp
Original Assignee
Renesas Semiconductor Engineering Corp
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Engineering Corp, Mitsubishi Electric Corp filed Critical Renesas Semiconductor Engineering Corp
Priority to JP32982299A priority Critical patent/JP2001148199A/ja
Priority to US09/712,246 priority patent/US6993696B1/en
Publication of JP2001148199A publication Critical patent/JP2001148199A/ja
Publication of JP2001148199A5 publication Critical patent/JP2001148199A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G11C2029/3602—Pattern generator

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Dram (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP32982299A 1999-11-19 1999-11-19 自己テスト回路内蔵半導体記憶装置 Pending JP2001148199A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP32982299A JP2001148199A (ja) 1999-11-19 1999-11-19 自己テスト回路内蔵半導体記憶装置
US09/712,246 US6993696B1 (en) 1999-11-19 2000-11-15 Semiconductor memory device with built-in self test circuit operating at high rate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32982299A JP2001148199A (ja) 1999-11-19 1999-11-19 自己テスト回路内蔵半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2001148199A true JP2001148199A (ja) 2001-05-29
JP2001148199A5 JP2001148199A5 (enExample) 2005-11-04

Family

ID=18225627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32982299A Pending JP2001148199A (ja) 1999-11-19 1999-11-19 自己テスト回路内蔵半導体記憶装置

Country Status (2)

Country Link
US (1) US6993696B1 (enExample)
JP (1) JP2001148199A (enExample)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003229000A (ja) * 2001-12-26 2003-08-15 Arm Ltd メモリ自己テストの方法と装置
JP2004030765A (ja) * 2002-06-25 2004-01-29 Fujitsu Ltd 自己診断機能内蔵の半導体記憶装置
US6930931B2 (en) 2002-10-30 2005-08-16 Renesas Technology Corp. Program counter circuit
US7032141B2 (en) 2002-01-25 2006-04-18 Renesas Technology Corp. Semiconductor device including test-facilitating circuit using built-in self test circuit
JP2007027642A (ja) * 2005-07-21 2007-02-01 Ricoh Co Ltd 半導体装置及び半導体装置のテスト方法
JP2007164839A (ja) * 2005-12-09 2007-06-28 Toshiba Corp 不揮発性半導体記憶装置及びその自己テスト方法
JP2009259398A (ja) * 2004-11-18 2009-11-05 Mentor Graphics Corp プログラマブル・メモリ・ビルト・イン・セルフ・テスト（ｍｂｉｓｔ）の方法及び装置
CN104881338A (zh) * 2014-02-28 2015-09-02 瑞萨电子株式会社 半导体设备

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7734966B1 (en) 2002-12-26 2010-06-08 Marvell International Ltd. Method and system for memory testing and test data reporting during memory testing
US20050034040A1 (en) * 2003-08-07 2005-02-10 Broadcom Corporation System and method for self-adaptive redundancy choice logic
US7631236B2 (en) * 2004-01-29 2009-12-08 International Business Machines Corporation Hybrid built-in self test (BIST) architecture for embedded memory arrays and an associated method
US7370249B2 (en) * 2004-06-22 2008-05-06 Intel Corporation Method and apparatus for testing a memory array
KR100540506B1 (ko) * 2004-08-03 2006-01-11 주식회사 유니테스트 메모리 소자 테스트를 위한 알고리즘 패턴 생성기 및 이를이용한 메모리 테스터
US7409618B2 (en) * 2004-10-06 2008-08-05 Lsi Corporation Self verifying communications testing
US8161461B2 (en) * 2005-03-24 2012-04-17 Hewlett-Packard Development Company, L.P. Systems and methods for evaluating code usage
KR100788913B1 (ko) * 2005-11-18 2007-12-27 주식회사디아이 반도체 장치의 테스트 시스템을 위한 전치 분기 패턴 발생장치
DE102007013075A1 (de) * 2007-03-19 2008-09-25 Qimonda Ag Testverfahren, integrierte Schaltung und Testsystem
US8321726B2 (en) * 2008-06-18 2012-11-27 Arm Limited Repairing memory arrays
US8887019B2 (en) * 2010-11-16 2014-11-11 Cadence Design Systems, Inc. Method and system for providing efficient on-product clock generation for domains compatible with compression
US10818374B2 (en) 2018-10-29 2020-10-27 Texas Instruments Incorporated Testing read-only memory using memory built-in self-test controller
KR102827631B1 (ko) * 2019-12-10 2025-07-03 에스케이하이닉스 주식회사 테스트 제어 회로를 포함하는 메모리 장치

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0682325B2 (ja) * 1990-05-29 1994-10-19 株式会社東芝 情報処理装置のテスト容易化回路
US5254942A (en) * 1991-04-25 1993-10-19 Daniel D'Souza Single chip IC tester architecture
US5790564A (en) 1995-06-07 1998-08-04 International Business Machines Corporation Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor
JP2918019B2 (ja) 1995-08-30 1999-07-12 日本電気株式会社 シングルチップマイクロプロセッサのテスト回路
US5796745A (en) * 1996-07-19 1998-08-18 International Business Machines Corporation Memory array built-in self test circuit for testing multi-port memory arrays
US5974579A (en) * 1996-09-03 1999-10-26 Credence Systems Corporation Efficient built-in self test for embedded memories with differing address spaces
JP3516834B2 (ja) 1997-06-10 2004-04-05 シャープ株式会社 半導体集積回路
JPH11329000A (ja) 1998-05-19 1999-11-30 Mitsubishi Electric Corp 内蔵メモリテスト方法、およびそれに用いるバスインタフェースユニット、コマンドデコーダ
US6249893B1 (en) * 1998-10-30 2001-06-19 Advantest Corp. Method and structure for testing embedded cores based system-on-a-chip

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003229000A (ja) * 2001-12-26 2003-08-15 Arm Ltd メモリ自己テストの方法と装置
US7032141B2 (en) 2002-01-25 2006-04-18 Renesas Technology Corp. Semiconductor device including test-facilitating circuit using built-in self test circuit
JP2004030765A (ja) * 2002-06-25 2004-01-29 Fujitsu Ltd 自己診断機能内蔵の半導体記憶装置
US6819609B2 (en) 2002-06-25 2004-11-16 Fujitsu Limited Semiconductor memory device with built-in self-diagnostic function and semiconductor device having the semiconductor memory device
US6930931B2 (en) 2002-10-30 2005-08-16 Renesas Technology Corp. Program counter circuit
JP2009259398A (ja) * 2004-11-18 2009-11-05 Mentor Graphics Corp プログラマブル・メモリ・ビルト・イン・セルフ・テスト（ｍｂｉｓｔ）の方法及び装置
JP2007027642A (ja) * 2005-07-21 2007-02-01 Ricoh Co Ltd 半導体装置及び半導体装置のテスト方法
JP2007164839A (ja) * 2005-12-09 2007-06-28 Toshiba Corp 不揮発性半導体記憶装置及びその自己テスト方法
US7739560B2 (en) 2005-12-09 2010-06-15 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of self-testing the same
CN104881338A (zh) * 2014-02-28 2015-09-02 瑞萨电子株式会社 半导体设备
JP2015162215A (ja) * 2014-02-28 2015-09-07 ルネサスエレクトロニクス株式会社 半導体装置
US9710174B2 (en) 2014-02-28 2017-07-18 Renesas Electronics Corporation Semiconductor device
CN104881338B (zh) * 2014-02-28 2019-08-13 瑞萨电子株式会社 半导体设备

Also Published As

Publication number Publication date
US6993696B1 (en) 2006-01-31

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