JP2001102523A - 薄膜デバイスおよびその製造方法 - Google Patents

薄膜デバイスおよびその製造方法

Info

Publication number
JP2001102523A
JP2001102523A JP27406299A JP27406299A JP2001102523A JP 2001102523 A JP2001102523 A JP 2001102523A JP 27406299 A JP27406299 A JP 27406299A JP 27406299 A JP27406299 A JP 27406299A JP 2001102523 A JP2001102523 A JP 2001102523A
Authority
JP
Japan
Prior art keywords
layer
support substrate
thin film
adhesive
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP27406299A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001102523A5 (enExample
Inventor
Kazushi Yamauchi
一志 山内
Takeshi Matsushita
孟史 松下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP27406299A priority Critical patent/JP2001102523A/ja
Priority to TW089120014A priority patent/TW492067B/zh
Priority to DE10047963A priority patent/DE10047963A1/de
Priority to US09/670,275 priority patent/US6503778B1/en
Priority to KR1020000056962A priority patent/KR20010039935A/ko
Publication of JP2001102523A publication Critical patent/JP2001102523A/ja
Publication of JP2001102523A5 publication Critical patent/JP2001102523A5/ja
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F55/00—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto
    • H10F55/20—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto wherein the electric light source controls the radiation-sensitive semiconductor devices, e.g. optocouplers
    • H10F55/25—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto wherein the electric light source controls the radiation-sensitive semiconductor devices, e.g. optocouplers wherein the radiation-sensitive devices and the electric light source are all semiconductor devices
    • H10F55/255—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto wherein the electric light source controls the radiation-sensitive semiconductor devices, e.g. optocouplers wherein the radiation-sensitive devices and the electric light source are all semiconductor devices formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7426—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01971—Cleaning, e.g. oxide removal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
    • H10W72/07207—Temporary substrates, e.g. removable substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07302—Connecting or disconnecting of die-attach connectors using an auxiliary member
    • H10W72/07304—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H10W72/07307—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating the auxiliary member being a temporary substrate, e.g. a removable substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Thin Film Transistor (AREA)
  • Light Receiving Elements (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
  • Electroluminescent Light Sources (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Recrystallisation Techniques (AREA)
JP27406299A 1999-09-28 1999-09-28 薄膜デバイスおよびその製造方法 Abandoned JP2001102523A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP27406299A JP2001102523A (ja) 1999-09-28 1999-09-28 薄膜デバイスおよびその製造方法
TW089120014A TW492067B (en) 1999-09-28 2000-09-27 Thin film device and method of manufacturing the same
DE10047963A DE10047963A1 (de) 1999-09-28 2000-09-27 Dünnfilm-Bauteil und Verfahren zu dessen Herstellung
US09/670,275 US6503778B1 (en) 1999-09-28 2000-09-27 Thin film device and method of manufacturing the same
KR1020000056962A KR20010039935A (ko) 1999-09-28 2000-09-28 박막 디바이스 및 그 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27406299A JP2001102523A (ja) 1999-09-28 1999-09-28 薄膜デバイスおよびその製造方法

Publications (2)

Publication Number Publication Date
JP2001102523A true JP2001102523A (ja) 2001-04-13
JP2001102523A5 JP2001102523A5 (enExample) 2006-04-06

Family

ID=17536447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27406299A Abandoned JP2001102523A (ja) 1999-09-28 1999-09-28 薄膜デバイスおよびその製造方法

Country Status (5)

Country Link
US (1) US6503778B1 (enExample)
JP (1) JP2001102523A (enExample)
KR (1) KR20010039935A (enExample)
DE (1) DE10047963A1 (enExample)
TW (1) TW492067B (enExample)

Cited By (15)

* Cited by examiner, † Cited by third party
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JP2003316281A (ja) * 2002-04-22 2003-11-07 Sony Corp 薄膜デバイスの製造方法、薄膜デバイスおよび表示装置
JP2004200522A (ja) * 2002-12-19 2004-07-15 Semiconductor Energy Lab Co Ltd 半導体チップおよびその作製方法
JP2004247405A (ja) * 2003-02-12 2004-09-02 Semiconductor Energy Lab Co Ltd 半導体装置
JP2005513781A (ja) * 2001-12-17 2005-05-12 フリースケール セミコンダクター インコーポレイテッド 材料を接合及び転写して半導体デバイスを形成する方法
JP2006041135A (ja) * 2004-07-26 2006-02-09 Sumitomo Bakelite Co Ltd 電子デバイスおよびその製造方法
JP2007266044A (ja) * 2006-03-27 2007-10-11 New Japan Radio Co Ltd 半導体装置の製造方法
JP2008505508A (ja) * 2004-06-30 2008-02-21 クリー　インコーポレイテッド 発光デバイスをパッケージするためのチップスケール方法およびチップスケールにパッケージされた発光デバイス
US7564139B2 (en) 2002-12-26 2009-07-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN100530576C (zh) * 2002-12-27 2009-08-19 株式会社半导体能源研究所 半导体器件以及其制作方法
JP2009302405A (ja) * 2008-06-16 2009-12-24 Shibaura Mechatronics Corp Ｓｏｉ基板の製造方法及び製造装置
JP2010232367A (ja) * 2009-03-26 2010-10-14 Nitta Ind Corp 薄膜層の転写方法および薄膜層転写用粘着テープ
JP2010245290A (ja) * 2009-04-06 2010-10-28 Canon Inc 半導体装置の製造方法
JP2014135516A (ja) * 2008-07-09 2014-07-24 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2015503228A (ja) * 2011-11-16 2015-01-29 クアルコム，インコーポレイテッド 絶縁層および第２の層を有する積層されたチップセットおよびそれを形成する方法
JP2017098573A (ja) * 2011-06-22 2017-06-01 ペレグリン セミコンダクター コーポレイション 選択基板の両面に部品を有する集積回路、及びその製造方法

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US7823279B2 (en) * 2002-04-01 2010-11-02 Intel Corporation Method for using an in package power supply to supply power to an integrated circuit and to a component
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US7064055B2 (en) 2002-12-31 2006-06-20 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure having a seamless bonding interface
JP4213478B2 (ja) * 2003-01-14 2009-01-21 株式会社ルネサステクノロジ 半導体装置の製造方法
US7436050B2 (en) * 2003-01-22 2008-10-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a flexible printed circuit
DE10303643B3 (de) * 2003-01-30 2004-09-09 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von Substratkontakten bei SOI-Schaltungsstrukturen
JP3981026B2 (ja) * 2003-01-30 2007-09-26 株式会社東芝 多層配線層を有する半導体装置およびその製造方法
JP4526771B2 (ja) 2003-03-14 2010-08-18 株式会社半導体エネルギー研究所 半導体装置の作製方法
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DE102011113642B4 (de) * 2011-09-16 2013-06-06 Austriamicrosystems Ag Verfahren zur Herstellung eines Halbleiterbauelementes unter Verwendung eines Hilfsträgers
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CN104716060A (zh) * 2015-03-16 2015-06-17 中国航天科技集团公司第九研究院第七七一研究所 一种tsv多层芯片键合方法
US9466729B1 (en) * 2015-05-08 2016-10-11 Qualcomm Incorporated Etch stop region based fabrication of bonded semiconductor structures
FR3051971B1 (fr) 2016-05-30 2019-12-13 Soitec Procede de fabrication d'une structure semi-conductrice comprenant un interposeur
FR3068510B1 (fr) * 2017-07-03 2019-08-30 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation d'une interface destinee a assembler temporairement un support microelectronique et une poignee de manipulation, et interface d'assemblage temporaire
US11239238B2 (en) 2019-10-29 2022-02-01 Intel Corporation Thin film transistor based memory cells on both sides of a layer of logic devices
CN114746999A (zh) * 2019-12-02 2022-07-12 维耶尔公司 在用于微型器件集成的背板上创建暂存
US11817442B2 (en) 2020-12-08 2023-11-14 Intel Corporation Hybrid manufacturing for integrated circuit devices and assemblies
US11756886B2 (en) 2020-12-08 2023-09-12 Intel Corporation Hybrid manufacturing of microeletronic assemblies with first and second integrated circuit structures
US12412835B2 (en) 2021-04-27 2025-09-09 Intel Corporation Back-side power delivery with glass support at the front
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Cited By (19)

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Publication number Priority date Publication date Assignee Title
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JP2003316281A (ja) * 2002-04-22 2003-11-07 Sony Corp 薄膜デバイスの製造方法、薄膜デバイスおよび表示装置
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KR20010039935A (ko) 2001-05-15

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