DE10047963A1 - Dünnfilm-Bauteil und Verfahren zu dessen Herstellung - Google Patents

Dünnfilm-Bauteil und Verfahren zu dessen Herstellung

Info

Publication number
DE10047963A1
DE10047963A1 DE10047963A DE10047963A DE10047963A1 DE 10047963 A1 DE10047963 A1 DE 10047963A1 DE 10047963 A DE10047963 A DE 10047963A DE 10047963 A DE10047963 A DE 10047963A DE 10047963 A1 DE10047963 A1 DE 10047963A1
Authority
DE
Germany
Prior art keywords
component
layer
substrate
layers
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10047963A
Other languages
German (de)
English (en)
Inventor
Kazushi Yamauchi
Takeshi Matsushita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE10047963A1 publication Critical patent/DE10047963A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F55/00—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto
    • H10F55/20—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto wherein the electric light source controls the radiation-sensitive semiconductor devices, e.g. optocouplers
    • H10F55/25—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto wherein the electric light source controls the radiation-sensitive semiconductor devices, e.g. optocouplers wherein the radiation-sensitive devices and the electric light source are all semiconductor devices
    • H10F55/255—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto wherein the electric light source controls the radiation-sensitive semiconductor devices, e.g. optocouplers wherein the radiation-sensitive devices and the electric light source are all semiconductor devices formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7426—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01971—Cleaning, e.g. oxide removal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
    • H10W72/07207—Temporary substrates, e.g. removable substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07302—Connecting or disconnecting of die-attach connectors using an auxiliary member
    • H10W72/07304—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H10W72/07307—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating the auxiliary member being a temporary substrate, e.g. a removable substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Thin Film Transistor (AREA)
  • Light Receiving Elements (AREA)
  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
  • Electroluminescent Light Sources (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Recrystallisation Techniques (AREA)
DE10047963A 1999-09-28 2000-09-27 Dünnfilm-Bauteil und Verfahren zu dessen Herstellung Withdrawn DE10047963A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27406299A JP2001102523A (ja) 1999-09-28 1999-09-28 薄膜デバイスおよびその製造方法

Publications (1)

Publication Number Publication Date
DE10047963A1 true DE10047963A1 (de) 2001-03-29

Family

ID=17536447

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10047963A Withdrawn DE10047963A1 (de) 1999-09-28 2000-09-27 Dünnfilm-Bauteil und Verfahren zu dessen Herstellung

Country Status (5)

Country Link
US (1) US6503778B1 (enExample)
JP (1) JP2001102523A (enExample)
KR (1) KR20010039935A (enExample)
DE (1) DE10047963A1 (enExample)
TW (1) TW492067B (enExample)

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DE10143764A1 (de) * 2001-09-06 2003-03-27 Infineon Technologies Ag Verfahren zum Anbringen von Speicherchips an einer Trägerplatine
DE10156465C1 (de) * 2001-11-16 2003-07-10 Infineon Technologies Ag Waferanordnung und Verfahren zur Herstellung einer Bondverbindung
DE10223719C1 (de) * 2002-05-28 2003-11-27 Infineon Technologies Ag Schicht-Anordnung und Verfahren zum Herstellen einer Schicht-Anordnung
EP1260481A3 (en) * 2001-05-21 2003-12-03 Hewlett-Packard Company Atomic resolution storage system
EP1261023A3 (en) * 2001-05-21 2003-12-03 Hewlett-Packard Company Atomic resolution storage system
DE10227605A1 (de) * 2002-06-20 2004-01-15 Infineon Technologies Ag Schicht-Anordnung und Verfahren zum Herstellen einer Schicht-Anordnung
EP1434262A2 (en) * 2002-12-26 2004-06-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device manufactured by the transfer technique
DE10303643B3 (de) * 2003-01-30 2004-09-09 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von Substratkontakten bei SOI-Schaltungsstrukturen
WO2003085725A3 (en) * 2002-04-01 2004-09-10 Intel Corp In package power supplies for integrated circuits
WO2004061953A3 (en) * 2002-12-31 2005-06-23 Massachusetts Inst Technology Method of forming a multi-layer semiconductor structure incorporating a processing handle member
US7064055B2 (en) 2002-12-31 2006-06-20 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure having a seamless bonding interface
EP1686623A4 (en) * 2003-10-30 2007-07-11 Japan Science & Tech Agency SEMICONDUCTOR ELEMENT AND PROCESS FOR ITS MANUFACTURE
EP1755164A3 (fr) * 2005-08-18 2007-09-12 Stmicroelectronics SA Procédé d'assemblage de composants passifs et de composants actifs et circuit intégré correspondant
DE102011113642A1 (de) * 2011-09-16 2013-03-21 Austriamicrosystems Ag Verfahren zur Herstellung eines Halbleiterbauelementes unter Verwendung eines Hilfsträgers
EP1434264A3 (en) * 2002-12-27 2017-01-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method using the transfer technique
EP4105981A1 (en) * 2021-06-17 2022-12-21 INTEL Corporation Layer transfer on non-semiconductor support structures
US11690211B2 (en) 2019-10-29 2023-06-27 Intel Corporation Thin film transistor based memory cells on both sides of a layer of logic devices
US11756886B2 (en) 2020-12-08 2023-09-12 Intel Corporation Hybrid manufacturing of microeletronic assemblies with first and second integrated circuit structures
US11817442B2 (en) 2020-12-08 2023-11-14 Intel Corporation Hybrid manufacturing for integrated circuit devices and assemblies
US12412835B2 (en) 2021-04-27 2025-09-09 Intel Corporation Back-side power delivery with glass support at the front
US12520482B2 (en) 2022-06-29 2026-01-06 Intel Corporation Memory arrays with backside components and angled transistors

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EP1620583A4 (en) * 2003-05-06 2009-04-22 Canon Kk SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, LUMINOUS DIODE AND MANUFACTURING METHOD THEREFOR
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US9496255B2 (en) 2011-11-16 2016-11-15 Qualcomm Incorporated Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
US8946052B2 (en) * 2012-09-26 2015-02-03 Sandia Corporation Processes for multi-layer devices utilizing layer transfer
CN104716060A (zh) * 2015-03-16 2015-06-17 中国航天科技集团公司第九研究院第七七一研究所 一种tsv多层芯片键合方法
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Cited By (36)

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Publication number Priority date Publication date Assignee Title
EP1260481A3 (en) * 2001-05-21 2003-12-03 Hewlett-Packard Company Atomic resolution storage system
EP1261023A3 (en) * 2001-05-21 2003-12-03 Hewlett-Packard Company Atomic resolution storage system
DE10143764A1 (de) * 2001-09-06 2003-03-27 Infineon Technologies Ag Verfahren zum Anbringen von Speicherchips an einer Trägerplatine
DE10156465C1 (de) * 2001-11-16 2003-07-10 Infineon Technologies Ag Waferanordnung und Verfahren zur Herstellung einer Bondverbindung
WO2003085725A3 (en) * 2002-04-01 2004-09-10 Intel Corp In package power supplies for integrated circuits
US7823279B2 (en) 2002-04-01 2010-11-02 Intel Corporation Method for using an in package power supply to supply power to an integrated circuit and to a component
DE10223719C1 (de) * 2002-05-28 2003-11-27 Infineon Technologies Ag Schicht-Anordnung und Verfahren zum Herstellen einer Schicht-Anordnung
DE10227605A1 (de) * 2002-06-20 2004-01-15 Infineon Technologies Ag Schicht-Anordnung und Verfahren zum Herstellen einer Schicht-Anordnung
EP1434262A2 (en) * 2002-12-26 2004-06-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device manufactured by the transfer technique
US7303942B2 (en) 2002-12-26 2007-12-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US7564139B2 (en) 2002-12-26 2009-07-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
EP1434262A3 (en) * 2002-12-26 2006-09-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device manufactured by the transfer technique
EP1434264A3 (en) * 2002-12-27 2017-01-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method using the transfer technique
WO2004061953A3 (en) * 2002-12-31 2005-06-23 Massachusetts Inst Technology Method of forming a multi-layer semiconductor structure incorporating a processing handle member
US7064055B2 (en) 2002-12-31 2006-06-20 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure having a seamless bonding interface
US7307003B2 (en) 2002-12-31 2007-12-11 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure incorporating a processing handle member
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KR20010039935A (ko) 2001-05-15

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