JP2000195856A - 半導体素子のゲ―ト酸化膜形成方法 - Google Patents

半導体素子のゲ―ト酸化膜形成方法

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JP2000195856A
JP2000195856A JP11322122A JP32212299A JP2000195856A JP 2000195856 A JP2000195856 A JP 2000195856A JP 11322122 A JP11322122 A JP 11322122A JP 32212299 A JP32212299 A JP 32212299A JP 2000195856 A JP2000195856 A JP 2000195856A
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oxide film
film
thickness
gate oxide
forming
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JP3528151B2 (ja
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Moon Sig Joo
文 植 周
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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Abstract

(57)【要約】 【課題】 本発明は、４０Å以下の有効ゲート酸化膜厚
を確保しながら、低リーク電流及び高信頼性のゲート酸
化膜が得られる半導体素子のゲート酸化膜形成方法を提
供する。 【解決手段】 半導体基板１１上に底部酸化膜としてＮ
Ｏ-オキシナイトライド膜１２を形成し、ＮＯ-オキシナ
イトライド膜上に中間酸化膜としてタンタル酸化膜１３
を形成し、次に、タンタル酸化膜上に上部酸化膜として
ＴＥＯＳ膜１４を形成し、基板をＮ２Ｏ雰囲気で熱処理
する。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は半導体素子の製造方
法に関し、特に半導体素子のゲート酸化膜形成方法に関
する。
【０００２】
【従来の技術】近年、半導体素子の高集積化、高速化、
低電圧化及び低電力化に伴い、ゲート酸化膜厚が薄くな
っている。一般に、ゲート酸化膜は、熱酸化工程によっ
て、約３.８５程度の誘電常数を持つシリコン酸化膜(Ｓ
ｉＯ２)で形成される。しかし、この場合、厚さが低減
されるにつれてダイレクトトンネリング効果(direct tu
nneling effect)を引き起こすことで、リーク電流が増
加するという問題がある。
【０００３】これを解決するために、ゲート酸化膜をシ
リコン酸化膜とシリコン窒化膜(Ｓｉ３Ｎ４)の積層膜で
形成する方法が提案された。しかし、シリコン窒化膜の
誘電常数が約７.０であるため、高信頼性及び低リーク
電流の特性が得られる４０Å以下の有効ゲート酸化膜厚
は得にくい。
【０００４】したがって、シリコン窒化膜よりも高い約
２５の誘電常数を持つタンタル酸化膜(Ｔａ２Ｏ５)を用
いて、底部酸化膜/タンタル酸化膜/上部酸化膜の積層膜
でゲート酸化膜を形成する方法が提案された。このゲー
ト酸化膜は、底部酸化膜を熱酸化方式にて５乃至２０Å
の膜厚でシリコン酸化膜で形成し、その上部にタンタル
酸化膜を３０乃至１００Åの膜厚で形成した後、上部酸
化膜を１０乃至２０Åの膜厚でＴＥＯＳ膜で形成した
後、Ｏ２雰囲気下で熱処理することで形成される。この
場合、実際のゲート酸化膜厚(physical gate oxide thi
ckness)は４５乃至１４０Åであるが、タンタル酸化膜
の高い誘電常数により有効ゲート酸化膜厚は４０Å以下
となる。
【０００５】
【発明が解決しようとする課題】しかしながら、上述の
如く、底部酸化膜を薄く形成する場合、その厚さの均一
度(uniformity)及び信頼性が劣化するため、その上部に
形成されるタンタル酸化膜のリーク電流に対するバリア
特性が低下するだけでなく、次の熱工程に対する耐酸化
特性も低下する。
【０００６】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、４０Å以下の有効ゲー
ト酸化膜厚を確保しながら、低リーク電流及び高信頼性
のゲート酸化膜が得られる半導体素子のゲート酸化膜形
成方法を提供することにある。
【０００７】
【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体素子のゲート酸化膜形成方法は、底
部酸化膜/中間酸化膜/上部酸化膜の積層構造からなる半
導体素子のゲート酸化膜形成方法において、半導体基板
上に底部酸化膜としてＮＯガスによるオキシナイトライ
ド膜(NO-oxynitride layer)を形成し、このＮＯ-オキシ
ナイトライド膜上に前記中間酸化膜としてタンタル酸化
膜を形成し、その後、タンタル酸化膜上に上部酸化膜を
形成し、基板をＮ２Ｏ雰囲気で熱処理する。
【０００８】具体的には、ＮＯ-オキシナイトライド膜
は５乃至２０Åの膜厚で、ＮＯガス雰囲気で炉(furnac
e)またはラピッドサーマル処理(rapid thermal process
ing；以下、ＲＴＰという)により形成される。望ましく
は、炉またはＲＴＰは、８００乃至８５０℃で、減圧ま
たは昇圧で進行され、ＮＯガスのフロー速度(flow rat
e)は５乃至２０リットルである。
【０００９】また、タンタル酸化膜は３０乃至１５０Å
の膜厚でＬＰＣＶＤ(low pressurechemical vapor depo
sition；低圧化学気相蒸着)またはＭＯＣＶＤ (metal o
rganic CVD；金属有機ＣＶＤ)で形成され、その有効酸
化膜厚は５乃至２０Åとなる。さらに、上部酸化膜はＴ
ＥＯＳ膜またはＨＴＯ膜(high temperature oxide laye
r；高温酸化膜)で１０乃至２０Åの膜厚で形成される。
【００１０】また、熱処理は炉またはＲＴＰで、８００
乃至８５０℃で、減圧または昇圧で進行され、Ｎ２Ｏの
ガスフロー速度は５乃至２０リットルである。
【００１１】
【発明の実施の形態】以下、添付図面に基づき、本発明
の好適実施態様を詳細に説明する。図１（ａ）、
（ｂ）、（ｃ）は本発明の実施態様による半導体素子の
ゲート酸化膜形成方法を説明するための断面図である。
【００１２】図１（ａ）を参照すると、シリコンからな
る半導体基板１１上に素子分離膜(不図示)を形成した
後、ＨＦを用いて洗浄工程を行って基板表面の自然酸化
膜(不図示)を除去する。次に、基板１１上に底部酸化膜
としてＮＯガスによるオキシナイトライド膜１２を５乃
至２０Åの膜厚で形成する。望ましくは、ＮＯ-オキシ
ナイトライド膜１２はＮＯガス雰囲気で炉またはＲＴＰ
によって、８００乃至８５０℃で減圧または昇圧で進行
して形成する。ここで、ＮＯガスのフロー速度は５乃至
２０リットルである。ここで、ＮＯ-オキシナイトライ
ド膜１２は成長速度が低いため、従来の熱酸化によるシ
リコン酸化膜よりも厚さの均一度が優れ、８００乃至８
５０℃の比較的低温で形成されるため、熱的予算(therm
al budget)が減少する。また、窒素により次の熱工程で
基板の酸化を抑制して有効酸化膜の成長を防止するだけ
でなく、ホットキャリアに対する耐性を増加させること
で、リーク電流に対するバリア特性が向上される。
【００１３】図１（ｂ）を参照すると、ＮＯ-オキシナ
イトライド膜１２上にＬＰＣＶＤ（低圧化学気相蒸着)
またはＭＯＣＶＤ（金属有機ＣＶＤ)によって、中間酸
化膜としてタンタル酸化膜(Ｔａ２Ｏ５)１３を３０乃至
１５０Åの膜厚で形成する。ここで、タンタル酸化膜１
３はシリコン酸化膜に比べて約６.５倍の誘電常数を持
つため、有効酸化膜厚は約５乃至２０Å程度となる。
【００１４】図１（ｃ）を参照すると、タンタル酸化膜
１３上にＣＶＤによって、上部酸化膜としてＴＥＯＳ膜
１４を１０乃至２０Åの膜厚で形成する。次に、従来の
Ｏ２雰囲気の代わりにＮ２Ｏ雰囲気で、炉またはＲＴＰ
で、８００乃至８５０℃で減圧または昇圧で熱処理を行
う。ここで、Ｎ２Ｏガスのフロー速度(flow rate)は５
乃至２０リットルである。
【００１５】これに伴い、ＴＥＯＳ膜１４を窒化させて
次工程により引き起こされるホウ素浸透を防止すること
で、しきい値電圧(Ｖｔｈ)が安定する。また、タンタル
酸化膜１３の酸素欠乏(oxygen vacancy)が減少されるこ
とで、リーク電流に対するバリア特性が向上される。ま
た、熱処理を８００乃至８５０℃の比較的低温で進行す
るため、熱的予算(thermal budget)が減少する。
【００１６】一方、前記ＴＥＯＳ膜１４の代りに、上部
酸化膜をＨＴＯ膜(高温酸化膜)で形成することができ
る。
【００１７】尚、本発明は、上記した実施の形態に限ら
れるものではない。本発明の趣旨から逸脱しない範囲内
で多様に変更・実施することが可能である。
【００１８】
【発明の効果】本発明によれば、ゲート酸化膜をＮＯ-
オキシナイトライド/タンタル酸化膜/ＴＥＯＳ膜の積層
膜で形成した後、Ｎ２Ｏ雰囲気で熱処理を進行して形成
することで、４０Å以下の有効ゲート酸化膜厚を確保し
ながら、低リーク電流及び高信頼性のゲート酸化膜が得
られるので、素子の特性が向上する。
【図面の簡単な説明】
【図１】本発明の半導体素子のゲート酸化膜形成方法の
実施態様を説明するための断面図であり、（ａ）は半導
体基板上にＮＯ-オキシナイトライド膜を形成する工
程、（ｂ）はＮＯ-オキシナイトライド膜上にタンタル
酸化膜を形成する工程、（ｃ）はタンタル酸化膜上にＴ
ＥＯＳ膜を形成する工程である。
【符号の説明】
１１ 半導体基板 １２ ＮＯ-オキシナイトライド膜 １３ タンタル酸化膜 １４ ＴＥＯＳ膜

Claims (14)

    【特許請求の範囲】
  1. 【請求項１】 底部酸化膜/中間酸化膜/上部酸化膜の積
    層構造からなる半導体素子のゲート酸化膜形成方法にお
    いて、 半導体基板上に前記底部酸化膜としてＮＯガスによるオ
    キシナイトライド膜を形成する段階と、 前記ＮＯ-オキシナイトライド膜上に前記中間酸化膜と
    してタンタル酸化膜を形成する段階と、 前記タンタル酸化膜上に前記上部酸化膜を形成する段階
    と、 前記基板をＮ２Ｏ雰囲気で熱処理する段階とを含むこと
    を特徴とする半導体素子のゲート酸化膜形成方法。
  2. 【請求項２】 前記ＮＯ-オキシナイトライド膜は５乃
    至２０Åの膜厚で形成されることを特徴とする請求項１
    記載の半導体素子のゲート酸化膜形成方法。
  3. 【請求項３】 前記ＮＯ-オキシナイトライド膜はＮＯ
    ガス雰囲気で炉またはラピッドサーマル処理により形成
    されることを特徴とする請求項２記載の半導体素子のゲ
    ート酸化膜形成方法。
  4. 【請求項４】 前記炉またはラピッドサーマル処理は、
    ８００乃至８５０℃で、減圧または昇圧で進行されるこ
    とを特徴とする請求項３記載の半導体素子のゲート酸化
    膜形成方法。
  5. 【請求項５】 前記ＮＯガスのフロー速度は５乃至２０
    リットルであることを特徴とする請求項４記載の半導体
    素子のゲート酸化膜形成方法。
  6. 【請求項６】 前記タンタル酸化膜は３０乃至１５０Å
    の膜厚で形成されることを特徴とする請求項１記載の半
    導体素子のゲート酸化膜形成方法。
  7. 【請求項７】 前記タンタル酸化膜の有効酸化膜厚は５
    乃至２０Åであることを特徴とする請求項６記載の半導
    体素子のゲート酸化膜形成方法。
  8. 【請求項８】 前記タンタル酸化膜はＬＰＣＶＤまたは
    ＭＯＣＶＤで形成されることを特徴とする請求項６記載
    の半導体素子のゲート酸化膜形成方法。
  9. 【請求項９】 前記上部酸化膜は１０乃至２０Åの膜厚
    で形成されることを特徴とする請求項１記載の半導体素
    子のゲート酸化膜形成方法。
  10. 【請求項１０】 前記上部酸化膜はＴＥＯＳ膜で形成さ
    れることを特徴とする請求項９記載の半導体素子のゲー
    ト酸化膜形成方法。
  11. 【請求項１１】 前記上部酸化膜はＨＴＯ膜で形成され
    ることを特徴とする請求項９記載の半導体素子のゲート
    酸化膜形成方法。
  12. 【請求項１２】 前記熱処理は炉またはラピッドサーマ
    ル処理で進行されることを特徴とする請求項１記載の半
    導体素子のゲート酸化膜形成方法。
  13. 【請求項１３】 前記炉またはラピッドサーマル処理
    は、８００乃至８５０℃で、減圧または昇圧で進行され
    ることを特徴とする請求項１２記載の半導体素子のゲー
    ト酸化膜形成方法。
  14. 【請求項１４】 前記Ｎ２Ｏのガスフロー速度は５乃至
    ２０リットルであることを特徴とする請求項１３記載の
    半導体素子のゲート酸化膜形成方法。
JP32212299A 1998-12-30 1999-11-12 半導体素子のゲート酸化膜形成方法 Expired - Lifetime JP3528151B2 (ja)

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