JP2000151369A5 - - Google Patents

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Publication number
JP2000151369A5
JP2000151369A5 JP1998318691A JP31869198A JP2000151369A5 JP 2000151369 A5 JP2000151369 A5 JP 2000151369A5 JP 1998318691 A JP1998318691 A JP 1998318691A JP 31869198 A JP31869198 A JP 31869198A JP 2000151369 A5 JP2000151369 A5 JP 2000151369A5
Authority
JP
Japan
Prior art keywords
clock
semiconductor integrated
input node
integrated circuit
distribution system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1998318691A
Other languages
English (en)
Japanese (ja)
Other versions
JP3753355B2 (ja
JP2000151369A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from JP31869198A external-priority patent/JP3753355B2/ja
Priority to JP31869198A priority Critical patent/JP3753355B2/ja
Priority to TW088117929A priority patent/TW452680B/zh
Priority to KR1019990047415A priority patent/KR100609342B1/ko
Priority to US09/437,267 priority patent/US6396323B1/en
Publication of JP2000151369A publication Critical patent/JP2000151369A/ja
Priority to US10/105,362 priority patent/US6720815B2/en
Priority to US10/792,720 priority patent/US6906572B2/en
Publication of JP2000151369A5 publication Critical patent/JP2000151369A5/ja
Priority to US10/992,730 priority patent/US7084690B2/en
Publication of JP3753355B2 publication Critical patent/JP3753355B2/ja
Application granted granted Critical
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP31869198A 1998-11-10 1998-11-10 半導体装置 Expired - Fee Related JP3753355B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP31869198A JP3753355B2 (ja) 1998-11-10 1998-11-10 半導体装置
TW088117929A TW452680B (en) 1998-11-10 1999-10-16 Electrical circuit, semiconductor integrated circuit device, circuit design method, record media and data distribution method
KR1019990047415A KR100609342B1 (ko) 1998-11-10 1999-10-29 반도체 장치
US09/437,267 US6396323B1 (en) 1998-11-10 1999-11-10 Phase adjustor for semiconductor integrated circuit
US10/105,362 US6720815B2 (en) 1998-11-10 2002-03-26 Phase adjustor for semiconductor integrated circuit
US10/792,720 US6906572B2 (en) 1998-11-10 2004-03-05 Semiconductor integrated circuit device
US10/992,730 US7084690B2 (en) 1998-11-10 2004-11-22 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31869198A JP3753355B2 (ja) 1998-11-10 1998-11-10 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2003364041A Division JP2004152290A (ja) 2003-10-24 2003-10-24 半導体装置

Publications (3)

Publication Number Publication Date
JP2000151369A JP2000151369A (ja) 2000-05-30
JP2000151369A5 true JP2000151369A5 (enExample) 2004-11-04
JP3753355B2 JP3753355B2 (ja) 2006-03-08

Family

ID=18101947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31869198A Expired - Fee Related JP3753355B2 (ja) 1998-11-10 1998-11-10 半導体装置

Country Status (4)

Country Link
US (4) US6396323B1 (enExample)
JP (1) JP3753355B2 (enExample)
KR (1) KR100609342B1 (enExample)
TW (1) TW452680B (enExample)

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JP3753355B2 (ja) * 1998-11-10 2006-03-08 株式会社ルネサステクノロジ 半導体装置
JP3880302B2 (ja) * 2000-10-12 2007-02-14 富士通株式会社 位相合成回路およびタイミング信号発生回路
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US7528638B2 (en) * 2003-12-22 2009-05-05 Micron Technology, Inc. Clock signal distribution with reduced parasitic loading effects
US7084686B2 (en) * 2004-05-25 2006-08-01 Micron Technology, Inc. System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
US7078951B2 (en) * 2004-08-27 2006-07-18 Micron Technology, Inc. System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
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US20070229115A1 (en) * 2006-01-25 2007-10-04 International Business Machines Corporation Method and apparatus for correcting duty cycle error in a clock distribution network
US7688928B2 (en) * 2006-09-05 2010-03-30 Lsi Corporation Duty cycle counting phase calibration scheme of an input/output (I/O) interface
EP2126660A2 (en) * 2006-12-01 2009-12-02 The Regents of the University of Michigan Clock distribution network architecture for resonant-clocked systems
US7973565B2 (en) * 2007-05-23 2011-07-05 Cyclos Semiconductor, Inc. Resonant clock and interconnect architecture for digital devices with multiple clock networks
US8205182B1 (en) 2007-08-22 2012-06-19 Cadence Design Systems, Inc. Automatic synthesis of clock distribution networks
JP2009152822A (ja) * 2007-12-20 2009-07-09 Spansion Llc 記憶装置
US7941689B2 (en) * 2008-03-19 2011-05-10 International Business Machines Corporation Minimizing clock uncertainty on clock distribution networks using a multi-level de-skewing technique
JP5774980B2 (ja) * 2008-04-07 2015-09-09 エコラボ インコーポレイティド 超高濃度液体脱脂組成物
US8471597B2 (en) 2008-05-27 2013-06-25 Qualcomm Incorporated Power saving circuit using a clock buffer and multiple flip-flops
WO2011046984A2 (en) 2009-10-12 2011-04-21 Cyclos Semiconductor Inc. Architecture for single-stepping in resonant clock distribution networks
FR2968787A1 (fr) * 2010-12-13 2012-06-15 Commissariat Energie Atomique Dispositif et procede de compensation de delai de propagation d'un signal
WO2013064868A1 (en) * 2011-11-04 2013-05-10 Freescale Semiconductor, Inc. Multi-level clock signal distribution network and integrated circuit
US9172383B2 (en) * 2013-01-29 2015-10-27 Broadcom Corporation Induction-coupled clock distribution for an integrated circuit
EP4645313A1 (en) * 2024-05-02 2025-11-05 Nxp B.V. Memory and method for constructing a memory

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JP3753355B2 (ja) * 1998-11-10 2006-03-08 株式会社ルネサステクノロジ 半導体装置

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