KR100609342B1 - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR100609342B1
KR100609342B1 KR1019990047415A KR19990047415A KR100609342B1 KR 100609342 B1 KR100609342 B1 KR 100609342B1 KR 1019990047415 A KR1019990047415 A KR 1019990047415A KR 19990047415 A KR19990047415 A KR 19990047415A KR 100609342 B1 KR100609342 B1 KR 100609342B1
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KR
South Korea
Prior art keywords
clock
clock signal
latch
phase
input node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019990047415A
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English (en)
Korean (ko)
Other versions
KR20000035108A (ko
Inventor
미즈노히로유키
Original Assignee
가부시키가이샤 히타치세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 히타치세이사쿠쇼 filed Critical 가부시키가이샤 히타치세이사쿠쇼
Publication of KR20000035108A publication Critical patent/KR20000035108A/ko
Application granted granted Critical
Publication of KR100609342B1 publication Critical patent/KR100609342B1/ko
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Dram (AREA)
KR1019990047415A 1998-11-10 1999-10-29 반도체 장치 Expired - Fee Related KR100609342B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP98-318691 1998-11-10
JP31869198A JP3753355B2 (ja) 1998-11-10 1998-11-10 半導体装置

Publications (2)

Publication Number Publication Date
KR20000035108A KR20000035108A (ko) 2000-06-26
KR100609342B1 true KR100609342B1 (ko) 2006-08-09

Family

ID=18101947

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990047415A Expired - Fee Related KR100609342B1 (ko) 1998-11-10 1999-10-29 반도체 장치

Country Status (4)

Country Link
US (4) US6396323B1 (enExample)
JP (1) JP3753355B2 (enExample)
KR (1) KR100609342B1 (enExample)
TW (1) TW452680B (enExample)

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JP3753355B2 (ja) * 1998-11-10 2006-03-08 株式会社ルネサステクノロジ 半導体装置
JP3880302B2 (ja) * 2000-10-12 2007-02-14 富士通株式会社 位相合成回路およびタイミング信号発生回路
US6594772B1 (en) * 2000-01-14 2003-07-15 Hewlett-Packard Development Company, L.P. Clock distribution circuitry to different nodes on integrated circuit with clock coupling circuitry to maintain predetermined phase relation between output and input of adjacent nodes
US7358974B2 (en) * 2001-01-29 2008-04-15 Silicon Graphics, Inc. Method and system for minimizing an amount of data needed to test data against subarea boundaries in spatially composited digital video
US6985041B2 (en) * 2002-05-02 2006-01-10 Intel Corporation Clock generating circuit and method
US6809606B2 (en) * 2002-05-02 2004-10-26 Intel Corporation Voltage ID based frequency control for clock generating circuit
US6885233B2 (en) * 2002-05-02 2005-04-26 Intel Corporation Altering operating frequency and voltage set point of a circuit in response to the operating temperature and instantaneous operating voltage of the circuit
JP4163974B2 (ja) * 2003-02-18 2008-10-08 松下電器産業株式会社 半導体装置
US7528638B2 (en) * 2003-12-22 2009-05-05 Micron Technology, Inc. Clock signal distribution with reduced parasitic loading effects
US7084686B2 (en) * 2004-05-25 2006-08-01 Micron Technology, Inc. System and method for open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
US7078951B2 (en) * 2004-08-27 2006-07-18 Micron Technology, Inc. System and method for reduced power open-loop synthesis of output clock signals having a selected phase relative to an input clock signal
KR100640609B1 (ko) * 2004-12-13 2006-11-01 삼성전자주식회사 포인트 확산클럭분배 네트워크 및 클럭분배방법
US7216279B2 (en) * 2005-07-19 2007-05-08 Lsi Logic Corporation Testing with high speed pulse generator
JP2007123336A (ja) * 2005-10-25 2007-05-17 Renesas Technology Corp 半導体集積回路のクロック構成方法およびそのプログラム
US20070229115A1 (en) * 2006-01-25 2007-10-04 International Business Machines Corporation Method and apparatus for correcting duty cycle error in a clock distribution network
US7688928B2 (en) * 2006-09-05 2010-03-30 Lsi Corporation Duty cycle counting phase calibration scheme of an input/output (I/O) interface
JP2010511942A (ja) * 2006-12-01 2010-04-15 ザ・リージェンツ・オブ・ザ・ユニバーシティ・オブ・ミシガン 共鳴クロックされたシステムのためのクロック分配ネットワークアーキテクチャ
US7973565B2 (en) * 2007-05-23 2011-07-05 Cyclos Semiconductor, Inc. Resonant clock and interconnect architecture for digital devices with multiple clock networks
US8205182B1 (en) 2007-08-22 2012-06-19 Cadence Design Systems, Inc. Automatic synthesis of clock distribution networks
JP2009152822A (ja) * 2007-12-20 2009-07-09 Spansion Llc 記憶装置
US7941689B2 (en) * 2008-03-19 2011-05-10 International Business Machines Corporation Minimizing clock uncertainty on clock distribution networks using a multi-level de-skewing technique
WO2009125335A2 (en) * 2008-04-07 2009-10-15 Ecolab Inc. Ultra-concentrated liquid degreaser composition
US8471597B2 (en) 2008-05-27 2013-06-25 Qualcomm Incorporated Power saving circuit using a clock buffer and multiple flip-flops
KR20120082450A (ko) * 2009-10-12 2012-07-23 사이클로스 세미컨덕터, 인크. 종래의 모드에서 공진 클록 네트워크를 동작시키기 위한 아키텍처
FR2968787A1 (fr) * 2010-12-13 2012-06-15 Commissariat Energie Atomique Dispositif et procede de compensation de delai de propagation d'un signal
US9459651B2 (en) 2011-11-04 2016-10-04 Freescale Semiconductor, Inc. Multi-level clock signal distribution network and integrated circuit
US9172383B2 (en) * 2013-01-29 2015-10-27 Broadcom Corporation Induction-coupled clock distribution for an integrated circuit
EP4645313A1 (en) * 2024-05-02 2025-11-05 Nxp B.V. Memory and method for constructing a memory

Citations (5)

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Publication number Priority date Publication date Assignee Title
JPH0277150A (ja) * 1988-09-13 1990-03-16 Toshiba Corp クロックライン駆動装置
JPH03161815A (ja) * 1989-11-20 1991-07-11 Matsushita Electric Ind Co Ltd クロック供給方式
JPH0934584A (ja) * 1995-07-14 1997-02-07 Oki Electric Ind Co Ltd クロック分配回路
JPH09251484A (ja) * 1996-03-18 1997-09-22 Sharp Corp 配線パターン作成装置
KR980011481A (ko) * 1996-07-08 1998-04-30 니시무로 다이조 데이타 처리장치, 반도체 기억장치 및 데이타 처리방법

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FR2556525B1 (fr) * 1983-12-09 1991-06-14 Plessey Overseas Appareil de detection de signaux radioelectriques modules en frequence
JPS60162388A (ja) * 1984-02-02 1985-08-24 Mitsubishi Electric Corp 磁気記録方式
JPH0640649B2 (ja) * 1986-04-16 1994-05-25 株式会社日立製作所 多段再生中継装置
US5093750A (en) * 1987-11-06 1992-03-03 Samsung Electronics Co., Ltd. System for recording/reproducing video data on or from a tape medium for storing digital signals and method therein
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JPH03101412A (ja) * 1989-09-14 1991-04-26 Hitachi Ltd 論理集積回路
US5239206A (en) * 1990-03-06 1993-08-24 Advanced Micro Devices, Inc. Synchronous circuit with clock skew compensating function and circuits utilizing same
JPH05159080A (ja) * 1991-12-05 1993-06-25 Hitachi Ltd 論理集積回路
US5255257A (en) * 1992-03-04 1993-10-19 Lasertape Systems, Inc. Frequency, phase and amplitude control apparatus and method for acousto-optic deflector optimization
US5485490A (en) * 1992-05-28 1996-01-16 Rambus, Inc. Method and circuitry for clock synchronization
JP3161815B2 (ja) 1992-06-09 2001-04-25 太平洋セメント株式会社 セラミックスと金属の接合用ロウ材及びその接合方法
KR100293596B1 (ko) * 1993-01-27 2001-09-17 가나이 쓰도무 Lsi내클럭분배회로
US5422915A (en) * 1993-12-23 1995-06-06 Unisys Corporation Fault tolerant clock distribution system
US5416861A (en) * 1994-04-29 1995-05-16 University Of Cincinnati Optical synchronous clock distribution network and high-speed signal distribution network
US5621692A (en) * 1994-05-24 1997-04-15 Winbond Electronics Corporation Memory device with page select capability
US5570045A (en) * 1995-06-07 1996-10-29 Lsi Logic Corporation Hierarchical clock distribution system and method
JP3291198B2 (ja) * 1996-05-08 2002-06-10 富士通株式会社 半導体集積回路
US5703537A (en) * 1996-07-03 1997-12-30 Microclock Incorporated Phase-locked loop clock circuit for generation of audio sampling clock signals from video reference signals
US5923385A (en) * 1996-10-11 1999-07-13 C-Cube Microsystems Inc. Processing system with single-buffered display capture
JPH10161769A (ja) * 1996-12-02 1998-06-19 Hitachi Ltd 半導体装置
TW389328U (en) * 1998-10-28 2000-05-01 Winbond Electronics Corp A device stringing along the frequency of stylization
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Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277150A (ja) * 1988-09-13 1990-03-16 Toshiba Corp クロックライン駆動装置
JPH03161815A (ja) * 1989-11-20 1991-07-11 Matsushita Electric Ind Co Ltd クロック供給方式
JPH0934584A (ja) * 1995-07-14 1997-02-07 Oki Electric Ind Co Ltd クロック分配回路
JPH09251484A (ja) * 1996-03-18 1997-09-22 Sharp Corp 配線パターン作成装置
KR980011481A (ko) * 1996-07-08 1998-04-30 니시무로 다이조 데이타 처리장치, 반도체 기억장치 및 데이타 처리방법

Also Published As

Publication number Publication date
US20040169535A1 (en) 2004-09-02
JP3753355B2 (ja) 2006-03-08
US20020067197A1 (en) 2002-06-06
KR20000035108A (ko) 2000-06-26
JP2000151369A (ja) 2000-05-30
US6906572B2 (en) 2005-06-14
US20020105367A1 (en) 2002-08-08
US20050075855A1 (en) 2005-04-07
US6396323B1 (en) 2002-05-28
TW452680B (en) 2001-09-01
US7084690B2 (en) 2006-08-01
US6720815B2 (en) 2004-04-13

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