ITMI20052042A1 - Sistema di memoria dispositivo di memoria unita'di controllo di memoria e suo procedimento - Google Patents

Sistema di memoria dispositivo di memoria unita'di controllo di memoria e suo procedimento

Info

Publication number
ITMI20052042A1
ITMI20052042A1 IT002042A ITMI20052042A ITMI20052042A1 IT MI20052042 A1 ITMI20052042 A1 IT MI20052042A1 IT 002042 A IT002042 A IT 002042A IT MI20052042 A ITMI20052042 A IT MI20052042A IT MI20052042 A1 ITMI20052042 A1 IT MI20052042A1
Authority
IT
Italy
Prior art keywords
memory
procedure
control unit
memory device
memory system
Prior art date
Application number
IT002042A
Other languages
English (en)
Inventor
Dong-Yang Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI20052042A1 publication Critical patent/ITMI20052042A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Static Random-Access Memory (AREA)
IT002042A 2004-11-04 2005-10-26 Sistema di memoria dispositivo di memoria unita'di controllo di memoria e suo procedimento ITMI20052042A1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040089253A KR100574989B1 (ko) 2004-11-04 2004-11-04 데이터 스트로브 버스라인의 효율을 향상시키는메모리장치 및 이를 구비하는 메모리 시스템, 및 데이터스트로브 신호 제어방법

Publications (1)

Publication Number Publication Date
ITMI20052042A1 true ITMI20052042A1 (it) 2006-05-05

Family

ID=36261634

Family Applications (1)

Application Number Title Priority Date Filing Date
IT002042A ITMI20052042A1 (it) 2004-11-04 2005-10-26 Sistema di memoria dispositivo di memoria unita'di controllo di memoria e suo procedimento

Country Status (7)

Country Link
US (2) US7450441B2 (it)
JP (1) JP5036998B2 (it)
KR (1) KR100574989B1 (it)
CN (1) CN1770061B (it)
DE (1) DE102005050595B4 (it)
IT (1) ITMI20052042A1 (it)
TW (1) TWI289312B (it)

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US9658642B2 (en) * 2013-07-01 2017-05-23 Intel Corporation Timing control for unmatched signal receiver
JP5588053B2 (ja) * 2013-09-05 2014-09-10 ルネサスエレクトロニクス株式会社 半導体集積回路
US10083728B2 (en) 2013-09-06 2018-09-25 Mediatek Inc. Memory controller, memory module and memory system
JP5759602B2 (ja) * 2014-07-24 2015-08-05 ルネサスエレクトロニクス株式会社 半導体集積回路
TWI608346B (zh) * 2014-12-10 2017-12-11 緯創資通股份有限公司 儲存裝置的檢測系統及其檢測方法
KR20160093434A (ko) * 2015-01-29 2016-08-08 에스케이하이닉스 주식회사 고속 통신을 위한 인터페이스 회로, 이를 포함하는 반도체 장치 및 시스템
US9384795B1 (en) 2015-04-29 2016-07-05 Qualcomm Incorporated Fully valid-gated read and write for low power array
KR102390917B1 (ko) 2015-10-16 2022-04-27 삼성전자주식회사 리드 인터페이스 장치의 클린 데이터 스트로브 신호 생성회로
US10163485B2 (en) * 2016-05-25 2018-12-25 Mediatek Inc. Memory module, memory controller and associated control method for read training technique
KR20180062511A (ko) * 2016-11-30 2018-06-11 에스케이하이닉스 주식회사 메모리 장치 및 이의 동작 방법, 메모리 시스템의 동작 방법
US9984740B1 (en) * 2017-03-21 2018-05-29 Micron Technology, Inc. Timing control for input receiver
JP2019128829A (ja) * 2018-01-25 2019-08-01 東芝メモリ株式会社 半導体記憶装置及びメモリシステム
US10176862B1 (en) * 2018-01-26 2019-01-08 Micron Technology, Inc. Data strobe gating
JP6894459B2 (ja) * 2019-02-25 2021-06-30 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． 疑似スタティックランダムアクセスメモリとその動作方法
TWI713042B (zh) * 2019-07-22 2020-12-11 群聯電子股份有限公司 記憶體介面電路、記憶體儲存裝置及設定狀態檢測方法
CN112309451B (zh) * 2019-07-30 2023-10-31 星宸科技股份有限公司 存储器控制器、存储器的读取控制的方法及相关存储系统
TWI779935B (zh) * 2021-11-24 2022-10-01 瑞昱半導體股份有限公司 資料處理系統、緩衝電路與緩衝電路的操作方法

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Also Published As

Publication number Publication date
CN1770061B (zh) 2010-08-25
KR100574989B1 (ko) 2006-05-02
US20090044039A1 (en) 2009-02-12
TWI289312B (en) 2007-11-01
DE102005050595A1 (de) 2006-06-01
JP2006134334A (ja) 2006-05-25
JP5036998B2 (ja) 2012-09-26
US7450441B2 (en) 2008-11-11
US20060092721A1 (en) 2006-05-04
TW200625328A (en) 2006-07-16
DE102005050595B4 (de) 2009-10-08
US7974143B2 (en) 2011-07-05
CN1770061A (zh) 2006-05-10

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