TW200625328A - A memory system, a memory device, a memory controller and method thereof - Google Patents

A memory system, a memory device, a memory controller and method thereof

Info

Publication number
TW200625328A
TW200625328A TW094137571A TW94137571A TW200625328A TW 200625328 A TW200625328 A TW 200625328A TW 094137571 A TW094137571 A TW 094137571A TW 94137571 A TW94137571 A TW 94137571A TW 200625328 A TW200625328 A TW 200625328A
Authority
TW
Taiwan
Prior art keywords
memory
memory device
logic level
controller
memory controller
Prior art date
Application number
TW094137571A
Other languages
Chinese (zh)
Other versions
TWI289312B (en
Inventor
Dong-Yang Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200625328A publication Critical patent/TW200625328A/en
Application granted granted Critical
Publication of TWI289312B publication Critical patent/TWI289312B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization

Abstract

The memory system, memory device, memory controller and method may have a reduced power consumption. The memory system, memory device, memory controller and method may transition a data strobe signal to a valid logic level during a standby state. The valid logic level may be less than a logic level associated with a higher impedance level, such as when a bus may be turned off or connected to a ground voltage. A delay locked circuit need not be used in the memory device.
TW094137571A 2004-11-04 2005-10-27 A memory system, a memory device, a memory controller and method thereof TWI289312B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040089253A KR100574989B1 (en) 2004-11-04 2004-11-04 Memory device for improving efficiency of data strobe bus line and memory system including the same, and data strobe signal control method thereof

Publications (2)

Publication Number Publication Date
TW200625328A true TW200625328A (en) 2006-07-16
TWI289312B TWI289312B (en) 2007-11-01

Family

ID=36261634

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094137571A TWI289312B (en) 2004-11-04 2005-10-27 A memory system, a memory device, a memory controller and method thereof

Country Status (7)

Country Link
US (2) US7450441B2 (en)
JP (1) JP5036998B2 (en)
KR (1) KR100574989B1 (en)
CN (1) CN1770061B (en)
DE (1) DE102005050595B4 (en)
IT (1) ITMI20052042A1 (en)
TW (1) TWI289312B (en)

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TWI779935B (en) * 2021-11-24 2022-10-01 瑞昱半導體股份有限公司 Data processing system, buffer circuit and method for operating buffer circuit

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JP5258687B2 (en) * 2009-07-13 2013-08-07 ルネサスエレクトロニクス株式会社 Memory interface control circuit
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JP5363252B2 (en) 2009-09-09 2013-12-11 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
KR101143469B1 (en) * 2010-07-02 2012-05-08 에스케이하이닉스 주식회사 Output enable signal generation circuit of semiconductor memory
US8520428B2 (en) * 2011-03-25 2013-08-27 Intel Corporation Combined data level-shifter and DE-skewer
DE112011105864T5 (en) * 2011-11-17 2014-08-07 Intel Corporation Method, device and system for memory validation
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US9658642B2 (en) * 2013-07-01 2017-05-23 Intel Corporation Timing control for unmatched signal receiver
JP5588053B2 (en) * 2013-09-05 2014-09-10 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
US10083728B2 (en) * 2013-09-06 2018-09-25 Mediatek Inc. Memory controller, memory module and memory system
JP5759602B2 (en) * 2014-07-24 2015-08-05 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit
TWI608346B (en) * 2014-12-10 2017-12-11 緯創資通股份有限公司 Structural-error detecting system for storage device and error detecting method thereof
KR20160093434A (en) * 2015-01-29 2016-08-08 에스케이하이닉스 주식회사 Interface circuit for high speed communication, semiconductor apparatus and system including the same
US9384795B1 (en) 2015-04-29 2016-07-05 Qualcomm Incorporated Fully valid-gated read and write for low power array
KR102390917B1 (en) 2015-10-16 2022-04-27 삼성전자주식회사 Clean data strobe signal generating circuit in read interface device
US10163485B2 (en) * 2016-05-25 2018-12-25 Mediatek Inc. Memory module, memory controller and associated control method for read training technique
KR20180062511A (en) * 2016-11-30 2018-06-11 에스케이하이닉스 주식회사 Memory device, operation method of the same and operation method of memory system
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JP6894459B2 (en) * 2019-02-25 2021-06-30 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． Pseudo-static random access memory and how it works
TWI713042B (en) * 2019-07-22 2020-12-11 群聯電子股份有限公司 Memory interface circuit, memory storage device and configuration status checking method
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Publication number Priority date Publication date Assignee Title
TWI779935B (en) * 2021-11-24 2022-10-01 瑞昱半導體股份有限公司 Data processing system, buffer circuit and method for operating buffer circuit

Also Published As

Publication number Publication date
TWI289312B (en) 2007-11-01
US20060092721A1 (en) 2006-05-04
DE102005050595A1 (en) 2006-06-01
US7450441B2 (en) 2008-11-11
DE102005050595B4 (en) 2009-10-08
JP2006134334A (en) 2006-05-25
CN1770061B (en) 2010-08-25
KR100574989B1 (en) 2006-05-02
CN1770061A (en) 2006-05-10
US20090044039A1 (en) 2009-02-12
ITMI20052042A1 (en) 2006-05-05
US7974143B2 (en) 2011-07-05
JP5036998B2 (en) 2012-09-26

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees