TW200625328A - A memory system, a memory device, a memory controller and method thereof - Google Patents
A memory system, a memory device, a memory controller and method thereofInfo
- Publication number
- TW200625328A TW200625328A TW094137571A TW94137571A TW200625328A TW 200625328 A TW200625328 A TW 200625328A TW 094137571 A TW094137571 A TW 094137571A TW 94137571 A TW94137571 A TW 94137571A TW 200625328 A TW200625328 A TW 200625328A
- Authority
- TW
- Taiwan
- Prior art keywords
- memory
- memory device
- logic level
- controller
- memory controller
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Memory System (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040089253A KR100574989B1 (ko) | 2004-11-04 | 2004-11-04 | 데이터 스트로브 버스라인의 효율을 향상시키는메모리장치 및 이를 구비하는 메모리 시스템, 및 데이터스트로브 신호 제어방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200625328A true TW200625328A (en) | 2006-07-16 |
TWI289312B TWI289312B (en) | 2007-11-01 |
Family
ID=36261634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094137571A TWI289312B (en) | 2004-11-04 | 2005-10-27 | A memory system, a memory device, a memory controller and method thereof |
Country Status (7)
Country | Link |
---|---|
US (2) | US7450441B2 (zh) |
JP (1) | JP5036998B2 (zh) |
KR (1) | KR100574989B1 (zh) |
CN (1) | CN1770061B (zh) |
DE (1) | DE102005050595B4 (zh) |
IT (1) | ITMI20052042A1 (zh) |
TW (1) | TWI289312B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI779935B (zh) * | 2021-11-24 | 2022-10-01 | 瑞昱半導體股份有限公司 | 資料處理系統、緩衝電路與緩衝電路的操作方法 |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7339840B2 (en) * | 2005-05-13 | 2008-03-04 | Infineon Technologies Ag | Memory system and method of accessing memory chips of a memory system |
JP4267002B2 (ja) | 2006-06-08 | 2009-05-27 | エルピーダメモリ株式会社 | コントローラ及びメモリを備えるシステム |
US7564735B2 (en) * | 2006-07-05 | 2009-07-21 | Qimonda Ag | Memory device, and method for operating a memory device |
WO2008063199A1 (en) | 2006-11-20 | 2008-05-29 | Rambus Inc. | Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift |
US7587571B2 (en) * | 2006-11-29 | 2009-09-08 | Qimonda Ag | Evaluation unit in an integrated circuit |
US7508723B2 (en) * | 2007-05-24 | 2009-03-24 | Entorian Technologies, Lp | Buffered memory device |
US7703063B2 (en) * | 2007-08-17 | 2010-04-20 | International Business Machines Corporation | Implementing memory read data eye stretcher |
US7661084B2 (en) * | 2007-08-17 | 2010-02-09 | International Business Machines Corporation | Implementing memory read data eye stretcher |
JP5143512B2 (ja) * | 2007-09-13 | 2013-02-13 | 株式会社リコー | メモリ制御装置 |
KR100929845B1 (ko) * | 2007-09-28 | 2009-12-04 | 주식회사 하이닉스반도체 | 동기식 반도체 메모리 소자 및 그의 구동방법 |
CN101593549B (zh) * | 2008-05-27 | 2011-06-22 | 群联电子股份有限公司 | 多非易失性存储器封装储存系统及其控制器与存取方法 |
CN101609712B (zh) * | 2008-06-18 | 2012-01-11 | 群联电子股份有限公司 | 具有多非易失性存储器的存储系统及其控制器与存取方法 |
JP5489427B2 (ja) * | 2008-06-27 | 2014-05-14 | スパンション エルエルシー | メモリ制御装置、メモリシステムおよびメモリ装置の制御方法。 |
CN102272730B (zh) * | 2008-10-09 | 2017-05-24 | 美光科技公司 | 经虚拟化错误校正码nand |
US20100332922A1 (en) * | 2009-06-30 | 2010-12-30 | Mediatek Inc. | Method for managing device and solid state disk drive utilizing the same |
JP5258687B2 (ja) * | 2009-07-13 | 2013-08-07 | ルネサスエレクトロニクス株式会社 | メモリインタフェース制御回路 |
JP5346259B2 (ja) | 2009-09-08 | 2013-11-20 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
JP5390310B2 (ja) | 2009-09-08 | 2014-01-15 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
JP5363252B2 (ja) | 2009-09-09 | 2013-12-11 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
KR101143469B1 (ko) * | 2010-07-02 | 2012-05-08 | 에스케이하이닉스 주식회사 | 반도체 메모리의 출력 인에이블 신호 생성 회로 |
US8520428B2 (en) * | 2011-03-25 | 2013-08-27 | Intel Corporation | Combined data level-shifter and DE-skewer |
DE112011105864T5 (de) | 2011-11-17 | 2014-08-07 | Intel Corporation | Verfahren, Vorrichtung und System zur Speichervalidierung |
KR101957814B1 (ko) * | 2012-06-13 | 2019-03-14 | 에스케이하이닉스 주식회사 | 집적 회로 및 이의 동작 방법 |
US9658642B2 (en) * | 2013-07-01 | 2017-05-23 | Intel Corporation | Timing control for unmatched signal receiver |
JP5588053B2 (ja) * | 2013-09-05 | 2014-09-10 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
US10083728B2 (en) * | 2013-09-06 | 2018-09-25 | Mediatek Inc. | Memory controller, memory module and memory system |
JP5759602B2 (ja) * | 2014-07-24 | 2015-08-05 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
TWI608346B (zh) * | 2014-12-10 | 2017-12-11 | 緯創資通股份有限公司 | 儲存裝置的檢測系統及其檢測方法 |
KR20160093434A (ko) * | 2015-01-29 | 2016-08-08 | 에스케이하이닉스 주식회사 | 고속 통신을 위한 인터페이스 회로, 이를 포함하는 반도체 장치 및 시스템 |
US9384795B1 (en) | 2015-04-29 | 2016-07-05 | Qualcomm Incorporated | Fully valid-gated read and write for low power array |
KR102390917B1 (ko) | 2015-10-16 | 2022-04-27 | 삼성전자주식회사 | 리드 인터페이스 장치의 클린 데이터 스트로브 신호 생성회로 |
US10163485B2 (en) * | 2016-05-25 | 2018-12-25 | Mediatek Inc. | Memory module, memory controller and associated control method for read training technique |
KR20180062511A (ko) * | 2016-11-30 | 2018-06-11 | 에스케이하이닉스 주식회사 | 메모리 장치 및 이의 동작 방법, 메모리 시스템의 동작 방법 |
US9984740B1 (en) * | 2017-03-21 | 2018-05-29 | Micron Technology, Inc. | Timing control for input receiver |
JP2019128829A (ja) * | 2018-01-25 | 2019-08-01 | 東芝メモリ株式会社 | 半導体記憶装置及びメモリシステム |
US10176862B1 (en) * | 2018-01-26 | 2019-01-08 | Micron Technology, Inc. | Data strobe gating |
JP6894459B2 (ja) * | 2019-02-25 | 2021-06-30 | 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. | 疑似スタティックランダムアクセスメモリとその動作方法 |
TWI713042B (zh) * | 2019-07-22 | 2020-12-11 | 群聯電子股份有限公司 | 記憶體介面電路、記憶體儲存裝置及設定狀態檢測方法 |
CN112309451B (zh) * | 2019-07-30 | 2023-10-31 | 星宸科技股份有限公司 | 存储器控制器、存储器的读取控制的方法及相关存储系统 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5724288A (en) * | 1995-08-30 | 1998-03-03 | Micron Technology, Inc. | Data communication for memory |
KR100268429B1 (ko) | 1997-03-18 | 2000-11-01 | 윤종용 | 동기형반도체메모리장치의데이터의입력회로및데이터입력방법 |
KR100303775B1 (ko) * | 1998-10-28 | 2001-09-24 | 박종섭 | 디디알 에스디램에서 데이터스트로브신호를 제어하기 위한 방법및 장치 |
JP4106811B2 (ja) * | 1999-06-10 | 2008-06-25 | 富士通株式会社 | 半導体記憶装置及び電子装置 |
US6519664B1 (en) | 2000-03-30 | 2003-02-11 | Intel Corporation | Parallel terminated bus system |
TWI228259B (en) * | 2000-05-22 | 2005-02-21 | Samsung Electronics Co Ltd | Method and circuit for inputting and outputting data, and system using semiconductor memory device including the same |
US7002378B2 (en) | 2000-12-29 | 2006-02-21 | Intel Corporation | Valid data strobe detection technique |
US6728162B2 (en) * | 2001-03-05 | 2004-04-27 | Samsung Electronics Co. Ltd | Data input circuit and method for synchronous semiconductor memory device |
US6512704B1 (en) | 2001-09-14 | 2003-01-28 | Sun Microsystems, Inc. | Data strobe receiver |
KR100437454B1 (ko) * | 2002-07-30 | 2004-06-23 | 삼성전자주식회사 | 소오스 싱크로너스 전송 방식을 이용한 비동기 메모리 및그것을 포함한 시스템 |
KR100546338B1 (ko) * | 2003-07-04 | 2006-01-26 | 삼성전자주식회사 | 데이터 비트 수에 따라 데이터 스트로브 신호를선택적으로 출력하는 버퍼 회로 및 시스템 |
US6922367B2 (en) * | 2003-07-09 | 2005-07-26 | Micron Technology, Inc. | Data strobe synchronization circuit and method for double data rate, multi-bit writes |
KR100535649B1 (ko) * | 2004-04-20 | 2005-12-08 | 주식회사 하이닉스반도체 | 디디알 메모리 소자의 디큐에스 신호 생성 회로 및 생성방법 |
-
2004
- 2004-11-04 KR KR1020040089253A patent/KR100574989B1/ko not_active IP Right Cessation
-
2005
- 2005-10-21 DE DE102005050595A patent/DE102005050595B4/de not_active Expired - Fee Related
- 2005-10-26 IT IT002042A patent/ITMI20052042A1/it unknown
- 2005-10-27 TW TW094137571A patent/TWI289312B/zh not_active IP Right Cessation
- 2005-11-04 US US11/266,383 patent/US7450441B2/en not_active Expired - Fee Related
- 2005-11-04 CN CN2005101201225A patent/CN1770061B/zh not_active Expired - Fee Related
- 2005-11-04 JP JP2005321358A patent/JP5036998B2/ja not_active Expired - Fee Related
-
2008
- 2008-10-01 US US12/285,294 patent/US7974143B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI779935B (zh) * | 2021-11-24 | 2022-10-01 | 瑞昱半導體股份有限公司 | 資料處理系統、緩衝電路與緩衝電路的操作方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5036998B2 (ja) | 2012-09-26 |
US20060092721A1 (en) | 2006-05-04 |
ITMI20052042A1 (it) | 2006-05-05 |
DE102005050595B4 (de) | 2009-10-08 |
JP2006134334A (ja) | 2006-05-25 |
US7974143B2 (en) | 2011-07-05 |
CN1770061A (zh) | 2006-05-10 |
DE102005050595A1 (de) | 2006-06-01 |
US7450441B2 (en) | 2008-11-11 |
TWI289312B (en) | 2007-11-01 |
US20090044039A1 (en) | 2009-02-12 |
CN1770061B (zh) | 2010-08-25 |
KR100574989B1 (ko) | 2006-05-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |