IT8219466A0 - Dispositivo di memoria a semiconduttori e procedimento di fabbricazione di esso. - Google Patents

Dispositivo di memoria a semiconduttori e procedimento di fabbricazione di esso.

Info

Publication number
IT8219466A0
IT8219466A0 IT8219466A IT1946682A IT8219466A0 IT 8219466 A0 IT8219466 A0 IT 8219466A0 IT 8219466 A IT8219466 A IT 8219466A IT 1946682 A IT1946682 A IT 1946682A IT 8219466 A0 IT8219466 A0 IT 8219466A0
Authority
IT
Italy
Prior art keywords
memory device
semiconductor memory
manufacturing procedure
procedure
manufacturing
Prior art date
Application number
IT8219466A
Other languages
English (en)
Other versions
IT1150181B (it
Inventor
Nobuyoshi Tanimura
Tokumasa Yasui
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of IT8219466A0 publication Critical patent/IT8219466A0/it
Application granted granted Critical
Publication of IT1150181B publication Critical patent/IT1150181B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
IT19466/82A 1981-02-06 1982-02-04 Dispositivo di memoria a semiconduttori e procedimento di fabbricazione di esso IT1150181B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56015733A JPS57130461A (en) 1981-02-06 1981-02-06 Semiconductor memory storage

Publications (2)

Publication Number Publication Date
IT8219466A0 true IT8219466A0 (it) 1982-02-04
IT1150181B IT1150181B (it) 1986-12-10

Family

ID=11896962

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19466/82A IT1150181B (it) 1981-02-06 1982-02-04 Dispositivo di memoria a semiconduttori e procedimento di fabbricazione di esso

Country Status (8)

Country Link
US (2) US4554729A (it)
JP (1) JPS57130461A (it)
DE (1) DE3204039A1 (it)
FR (1) FR2499749B1 (it)
GB (1) GB2092826B (it)
HK (1) HK44886A (it)
IT (1) IT1150181B (it)
MY (1) MY8600548A (it)

Families Citing this family (49)

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Publication number Priority date Publication date Assignee Title
JPS5736844A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Semiconductor device
JPS59107555A (ja) * 1982-12-03 1984-06-21 Fujitsu Ltd 半導体装置
US4633572A (en) * 1983-02-22 1987-01-06 General Motors Corporation Programming power paths in an IC by combined depletion and enhancement implants
JPS60116167A (ja) * 1983-11-29 1985-06-22 Toshiba Corp 半導体記憶装置及びその製造方法
US5610089A (en) * 1983-12-26 1997-03-11 Hitachi, Ltd. Method of fabrication of semiconductor integrated circuit device
US5276346A (en) * 1983-12-26 1994-01-04 Hitachi, Ltd. Semiconductor integrated circuit device having protective/output elements and internal circuits
KR930007195B1 (ko) * 1984-05-23 1993-07-31 가부시끼가이샤 히다찌세이사꾸쇼 반도체 장치와 그 제조 방법
US5352620A (en) * 1984-05-23 1994-10-04 Hitachi, Ltd. Method of making semiconductor device with memory cells and peripheral transistors
JPH0691195B2 (ja) * 1984-07-25 1994-11-14 株式会社日立製作所 半導体集積回路装置
US4670091A (en) * 1984-08-23 1987-06-02 Fairchild Semiconductor Corporation Process for forming vias on integrated circuits
KR940002772B1 (ko) * 1984-08-31 1994-04-02 가부시기가이샤 히다찌세이사꾸쇼 반도체 집적회로 장치 및 그 제조방법
US4830976A (en) * 1984-10-01 1989-05-16 American Telephone And Telegraph Company, At&T Bell Laboratories Integrated circuit resistor
KR940006668B1 (ko) * 1984-11-22 1994-07-25 가부시끼가이샤 히다찌세이사꾸쇼 반도체 집적회로 장치의 제조방법
GB2172744B (en) * 1985-03-23 1989-07-19 Stc Plc Semiconductor devices
JPS61263254A (ja) * 1985-05-17 1986-11-21 Nec Corp 入力保護装置
US4774203A (en) * 1985-10-25 1988-09-27 Hitachi, Ltd. Method for making static random-access memory device
US4774202A (en) * 1985-11-07 1988-09-27 Sprague Electric Company Memory device with interconnected polysilicon layers and method for making
JPS63305545A (ja) * 1987-06-05 1988-12-13 Hitachi Ltd 半導体集積回路装置
US4843027A (en) * 1987-08-21 1989-06-27 Siliconix Incorporated Method of fabricating a high value semiconductor resistor
US4984200A (en) * 1987-11-30 1991-01-08 Hitachi, Ltd. Semiconductor circuit device having a plurality of SRAM type memory cell arrangement
US5014242A (en) * 1987-12-10 1991-05-07 Hitachi, Ltd. Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit
US4830974A (en) * 1988-01-11 1989-05-16 Atmel Corporation EPROM fabrication process
US4833096A (en) * 1988-01-19 1989-05-23 Atmel Corporation EEPROM fabrication process
US5445980A (en) 1988-05-10 1995-08-29 Hitachi, Ltd. Method of making a semiconductor memory device
US5153144A (en) * 1988-05-10 1992-10-06 Hitachi, Ltd. Method of making tunnel EEPROM
US4859619A (en) * 1988-07-15 1989-08-22 Atmel Corporation EPROM fabrication process forming tub regions for high voltage devices
JP2829992B2 (ja) * 1988-11-10 1998-12-02 セイコーエプソン株式会社 半導体装置
US5349206A (en) * 1988-11-10 1994-09-20 Seiko Epson Corporation Integrated memory circuit with high density load elements
US5196233A (en) * 1989-01-18 1993-03-23 Sgs-Thomson Microelectronics, Inc. Method for fabricating semiconductor circuits
US5151387A (en) 1990-04-30 1992-09-29 Sgs-Thomson Microelectronics, Inc. Polycrystalline silicon contact structure
JP3266644B2 (ja) * 1991-04-08 2002-03-18 テキサス インスツルメンツ インコーポレイテツド ゲートアレイ装置
US5275962A (en) * 1991-04-08 1994-01-04 Texas Instruments Incorporated Mask programmable gate array base cell
TW208088B (it) * 1991-05-16 1993-06-21 American Telephone & Telegraph
US5204279A (en) * 1991-06-03 1993-04-20 Sgs-Thomson Microelectronics, Inc. Method of making SRAM cell and structure with polycrystalline p-channel load devices
US5187114A (en) * 1991-06-03 1993-02-16 Sgs-Thomson Microelectronics, Inc. Method of making SRAM cell and structure with polycrystalline P-channel load devices
JP2853426B2 (ja) * 1991-12-20 1999-02-03 日本電気株式会社 半導体記憶装置の製造方法
US5880022A (en) * 1991-12-30 1999-03-09 Lucent Technologies Inc. Self-aligned contact window
FR2690786A1 (fr) * 1992-04-30 1993-10-29 Sgs Thomson Microelectronics Sa Dispositif de protection d'un circuit intégré contre les décharges électrostatiques.
US5354704A (en) * 1993-07-28 1994-10-11 United Microelectronics Corporation Symmetric SRAM cell with buried N+ local interconnection line
JP3110262B2 (ja) * 1993-11-15 2000-11-20 松下電器産業株式会社 半導体装置及び半導体装置のオペレーティング方法
JP2689888B2 (ja) * 1993-12-30 1997-12-10 日本電気株式会社 半導体装置及びその製造方法
JPH09260510A (ja) * 1996-01-17 1997-10-03 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6140684A (en) * 1997-06-24 2000-10-31 Stmicroelectronic, Inc. SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers
JP3540190B2 (ja) * 1999-03-15 2004-07-07 日本電気株式会社 半導体記憶装置
US7160773B2 (en) * 2004-05-05 2007-01-09 Spansion Llc Methods and apparatus for wordline protection in flash memory devices
US7512509B2 (en) * 2007-04-26 2009-03-31 International Business Machines Corporation M1 testable addressable array for device parameter characterization
JP5274878B2 (ja) * 2008-04-15 2013-08-28 パナソニック株式会社 半導体装置及びその製造方法
JP2011091188A (ja) * 2009-10-22 2011-05-06 Sanyo Electric Co Ltd 半導体装置の製造方法
KR101896412B1 (ko) * 2011-08-01 2018-09-07 페어차일드코리아반도체 주식회사 폴리 실리콘 저항, 이를 포함하는 기준 전압 회로, 및 폴리 실리콘 저항 제조 방법

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Publication number Priority date Publication date Assignee Title
US3673428A (en) * 1970-09-18 1972-06-27 Rca Corp Input transient protection for complementary insulated gate field effect transistor integrated circuit device
US3967295A (en) * 1975-04-03 1976-06-29 Rca Corporation Input transient protection for integrated circuit element
DE2751481C2 (de) * 1976-11-22 1986-10-23 Mostek Corp. (n.d.Ges.d.Staates Delaware), Carrollton, Tex. Lastimpedanz für eine statische Halbleiterspeicherzelle
US4167804A (en) * 1976-12-13 1979-09-18 General Motors Corporation Integrated circuit process compatible surge protection resistor
JPS5376679A (en) * 1976-12-17 1978-07-07 Nec Corp Semiconductor device
US4240097A (en) * 1977-05-31 1980-12-16 Texas Instruments Incorporated Field-effect transistor structure in multilevel polycrystalline silicon
US4139785A (en) * 1977-05-31 1979-02-13 Texas Instruments Incorporated Static memory cell with inverted field effect transistor
US4209716A (en) * 1977-05-31 1980-06-24 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in second-level polycrystalline silicon layer
JPS5910581B2 (ja) * 1977-12-01 1984-03-09 富士通株式会社 半導体装置の製造方法
US4408385A (en) * 1978-06-15 1983-10-11 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
US4198695A (en) * 1978-07-19 1980-04-15 Texas Instruments Incorporated Static semiconductor memory cell using data lines for voltage supply
US4246593A (en) * 1979-01-02 1981-01-20 Texas Instruments Incorporated High density static memory cell with polysilicon resistors
JPS6055988B2 (ja) * 1979-01-26 1985-12-07 株式会社日立製作所 半導体装置の製法
US4475964A (en) * 1979-02-20 1984-10-09 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a semiconductor device
US4370798A (en) * 1979-06-15 1983-02-01 Texas Instruments Incorporated Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon
US4397077A (en) * 1981-12-16 1983-08-09 Inmos Corporation Method of fabricating self-aligned MOS devices and independently formed gate dielectrics and insulating layers
US4651409A (en) * 1984-02-09 1987-03-24 Ncr Corporation Method of fabricating a high density, low power, merged vertical fuse/bipolar transistor

Also Published As

Publication number Publication date
GB2092826B (en) 1985-01-09
US4554729A (en) 1985-11-26
DE3204039A1 (de) 1982-08-26
US4712192A (en) 1987-12-08
MY8600548A (en) 1986-12-31
JPH0410229B2 (it) 1992-02-24
GB2092826A (en) 1982-08-18
JPS57130461A (en) 1982-08-12
IT1150181B (it) 1986-12-10
FR2499749B1 (fr) 1986-01-24
HK44886A (en) 1986-06-27
FR2499749A1 (fr) 1982-08-13

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19950224