IT1272460B - Dispositivo di memoria dinamica ad accesso casuale adatto per abbreviare il tempo richiesto per testare la richiesta di auto-rinfresco - Google Patents

Dispositivo di memoria dinamica ad accesso casuale adatto per abbreviare il tempo richiesto per testare la richiesta di auto-rinfresco

Info

Publication number
IT1272460B
IT1272460B ITMI931088A ITMI931088A IT1272460B IT 1272460 B IT1272460 B IT 1272460B IT MI931088 A ITMI931088 A IT MI931088A IT MI931088 A ITMI931088 A IT MI931088A IT 1272460 B IT1272460 B IT 1272460B
Authority
IT
Italy
Prior art keywords
test
self
refreshment
refreshing
random access
Prior art date
Application number
ITMI931088A
Other languages
English (en)
Inventor
Tetsushi Tanizaki
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI931088A0 publication Critical patent/ITMI931088A0/it
Publication of ITMI931088A1 publication Critical patent/ITMI931088A1/it
Application granted granted Critical
Publication of IT1272460B publication Critical patent/IT1272460B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

Viene rivelata una memoria dinamica ad accesso casuale (DRAM) avente un circuito di controllo migliorato del rinfresco (20). Un circuito di controllo di auto-rinfresco (15) include un circuito oscillante (13) per generare un segnale di orologio (?0) che definisce un ciclo di rinfresco in una modalità normale di auto-rinfresco e un circuito oscillante (16) per generare un segnale di orologio (?t) che definisce un ciclo di rinfresco in una modalità di prova. Quando una tensione elevata più alta di un livello di una tensione di alimentazione Vcc viene applicata ad un terminale di ingresso RAS (22), un circuito di rivelamento della modalità di prova (19) fornisce un segnale di alto livello (CTE), attivando così una porta di trasmissione (18). In una prova di verifica della funzione di auto-rinfresco, dato che un contatore di rinfresco può generare un indirizzo di rinfresco avente un ciclo di rinfresco più breve di quello nella modalità normale di auto-rinfresco, può essere abbreviato il tempo richiesto per eseguire la prova.
ITMI931088A 1992-06-04 1993-05-26 Dispositivo di memoria dinamica ad accesso casuale adatto per abbreviare il tempo richiesto per testare la richiesta di auto-rinfresco IT1272460B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4144044A JP2856598B2 (ja) 1992-06-04 1992-06-04 ダイナミックランダムアクセスメモリ装置

Publications (3)

Publication Number Publication Date
ITMI931088A0 ITMI931088A0 (it) 1993-05-26
ITMI931088A1 ITMI931088A1 (it) 1994-11-26
IT1272460B true IT1272460B (it) 1997-06-23

Family

ID=15353020

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI931088A IT1272460B (it) 1992-06-04 1993-05-26 Dispositivo di memoria dinamica ad accesso casuale adatto per abbreviare il tempo richiesto per testare la richiesta di auto-rinfresco

Country Status (5)

Country Link
US (1) US5349562A (it)
JP (1) JP2856598B2 (it)
KR (1) KR960008279B1 (it)
DE (1) DE4317887A1 (it)
IT (1) IT1272460B (it)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950010624B1 (ko) * 1993-07-14 1995-09-20 삼성전자주식회사 반도체 메모리장치의 셀프리프레시 주기조절회로
JP2606669B2 (ja) * 1994-09-22 1997-05-07 日本電気株式会社 半導体記憶装置
JPH08153400A (ja) * 1994-11-29 1996-06-11 Mitsubishi Electric Corp Ｄｒａｍ
JPH08227579A (ja) * 1995-02-22 1996-09-03 Mitsubishi Electric Corp 半導体記憶装置
JPH09161478A (ja) * 1995-12-12 1997-06-20 Mitsubishi Electric Corp 半導体記憶装置
JP4014669B2 (ja) * 1996-04-22 2007-11-28 株式会社ルネサステクノロジ 同期型半導体記憶装置
US6392948B1 (en) * 1996-08-29 2002-05-21 Micron Technology, Inc. Semiconductor device with self refresh test mode
US5940851A (en) * 1996-11-27 1999-08-17 Monolithic Systems, Inc. Method and apparatus for DRAM refresh using master, slave and self-refresh modes
US6272588B1 (en) * 1997-05-30 2001-08-07 Motorola Inc. Method and apparatus for verifying and characterizing data retention time in a DRAM using built-in test circuitry
JPH1139862A (ja) * 1997-07-16 1999-02-12 Mitsubishi Electric Corp 半導体記憶装置
WO1999019879A1 (en) * 1997-10-10 1999-04-22 Rambus Incorporated Dram core refresh with reduced spike current
US6122214A (en) * 1998-03-23 2000-09-19 Matsushita Electric Industrial Co., Ltd. Semiconductor memory
US6049505A (en) 1998-05-22 2000-04-11 Micron Technology, Inc. Method and apparatus for generating memory addresses for testing memory devices
KR20000026987A (ko) * 1998-10-22 2000-05-15 구자홍 절전모드 제어장치 및 방법
US6317852B1 (en) * 1998-10-23 2001-11-13 Vanguard International Semiconductor Corporation Method to test auto-refresh and self refresh circuitry
KR100381966B1 (ko) * 1998-12-28 2004-03-22 주식회사 하이닉스반도체 반도체메모리장치및그구동방법
US6208577B1 (en) * 1999-04-16 2001-03-27 Micron Technology, Inc. Circuit and method for refreshing data stored in a memory cell
TW454289B (en) * 2000-03-09 2001-09-11 Taiwan Semiconductor Mfg Programmable memory refresh architecture
KR100712492B1 (ko) * 2001-06-28 2007-05-02 삼성전자주식회사 반도체 메모리 장치의 셀프 리프레쉬 회로 및 그 방법
US6774734B2 (en) * 2002-11-27 2004-08-10 International Business Machines Corporation Ring oscillator circuit for EDRAM/DRAM performance monitoring
KR100576922B1 (ko) 2004-04-19 2006-05-03 주식회사 하이닉스반도체 고전압 발생 회로
KR100607352B1 (ko) * 2004-12-30 2006-07-31 주식회사 하이닉스반도체 리프레쉬 오실레이터 제어 회로
KR100670657B1 (ko) * 2005-06-30 2007-01-17 주식회사 하이닉스반도체 반도체 메모리 소자
US7746159B1 (en) * 2006-06-06 2010-06-29 Cypress Semiconductor Corporation Polarity conversion circuit
KR100878301B1 (ko) * 2007-05-10 2009-01-13 주식회사 하이닉스반도체 다중 테스트 모드를 지원하는 테스트 회로
US7890286B2 (en) * 2007-12-18 2011-02-15 Hynix Semiconductor Inc. Test circuit for performing multiple test modes

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6061992A (ja) * 1983-09-14 1985-04-09 Nec Corp 擬似スタティックメモリ
JPS62170094A (ja) * 1986-01-21 1987-07-27 Mitsubishi Electric Corp 半導体記憶回路
JPS6432489A (en) * 1987-07-27 1989-02-02 Matsushita Electronics Corp Memory device
US4933907A (en) * 1987-12-03 1990-06-12 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory device and operating method therefor
US5243576A (en) * 1990-08-30 1993-09-07 Nec Corporation Semiconductor memory device
JPH05217366A (ja) * 1992-02-04 1993-08-27 Sharp Corp ダイナミック型半導体メモリ

Also Published As

Publication number Publication date
KR940001163A (ko) 1994-01-10
US5349562A (en) 1994-09-20
ITMI931088A1 (it) 1994-11-26
JPH05342862A (ja) 1993-12-24
JP2856598B2 (ja) 1999-02-10
ITMI931088A0 (it) 1993-05-26
DE4317887A1 (de) 1993-12-09
KR960008279B1 (ko) 1996-06-21

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970527