IT1247968B - Dispositivo di memoria a semiconduttore e relativo metodo di fabbricazione. - Google Patents

Dispositivo di memoria a semiconduttore e relativo metodo di fabbricazione.

Info

Publication number
IT1247968B
IT1247968B ITMI911513A ITMI911513A IT1247968B IT 1247968 B IT1247968 B IT 1247968B IT MI911513 A ITMI911513 A IT MI911513A IT MI911513 A ITMI911513 A IT MI911513A IT 1247968 B IT1247968 B IT 1247968B
Authority
IT
Italy
Prior art keywords
memory device
semiconductor memory
peripheral circuit
related manufacturing
source
Prior art date
Application number
ITMI911513A
Other languages
English (en)
Inventor
Kyu-Pil Lee
Yong-Jik Park
Jong-Bok Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI911513A0 publication Critical patent/ITMI911513A0/it
Publication of ITMI911513A1 publication Critical patent/ITMI911513A1/it
Application granted granted Critical
Publication of IT1247968B publication Critical patent/IT1247968B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Questa invenzione si riferisce ad un dispositivo di memoria a semiconduttore avente una schiera di celle e un circuito periferico e al relativo metodo di fabbricazione. Vengono forniti un dispositivo di memoria a semiconduttore e un relativo metodo di fabbricazione in cui le regioni di diffusione di impurità della sorgente e del pozzo dei transistori costituenti la schiera di celle hanno una concentrazione di impurità inferiore a quella delle regioni di diffusione di impurità della sorgente e del pozzo dei transistori costituenti il circuito periferico. Così, viene migliorata la caratteristica della tensione della scarica disruptiva della giunzione del transistore nell'area della schiera di celle, e vengono risolti il fenomeno di inversione dei dati e il problema del deterioramento della caratteristica di. aggiornamento dovuti alla corrente di dispersione del transistore nell'area del circuito periferico.
ITMI911513A 1991-03-20 1991-06-04 Dispositivo di memoria a semiconduttore e relativo metodo di fabbricazione. IT1247968B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910004394A KR940000510B1 (ko) 1991-03-20 1991-03-20 반도체 메모리장치 및 그 제조방법

Publications (3)

Publication Number Publication Date
ITMI911513A0 ITMI911513A0 (it) 1991-06-04
ITMI911513A1 ITMI911513A1 (it) 1992-12-04
IT1247968B true IT1247968B (it) 1995-01-05

Family

ID=19312269

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI911513A IT1247968B (it) 1991-03-20 1991-06-04 Dispositivo di memoria a semiconduttore e relativo metodo di fabbricazione.

Country Status (7)

Country Link
JP (1) JP2564712B2 (it)
KR (1) KR940000510B1 (it)
DE (1) DE4117703C2 (it)
FR (1) FR2674373B1 (it)
GB (1) GB2253937B (it)
IT (1) IT1247968B (it)
TW (1) TW199236B (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6258671B1 (en) * 1997-05-13 2001-07-10 Micron Technology, Inc. Methods of providing spacers over conductive line sidewalls, methods of forming sidewall spacers over etched line sidewalls, and methods of forming conductive lines
DE10121011B4 (de) * 2001-04-28 2004-11-04 Infineon Technologies Ag Verfahren zur maskenlosen Kontaktlochdotierung bei DRAMs/eDRAMs und entsprechend hergestellter Speicherchip

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4364075A (en) * 1980-09-02 1982-12-14 Intel Corporation CMOS Dynamic RAM cell and method of fabrication
JPS60164570A (ja) * 1984-02-06 1985-08-27 株式会社東芝 扉ロツク装置
JPS61156962A (ja) * 1984-12-27 1986-07-16 Nec Corp 構内電子交換システム
JPS61156862A (ja) * 1984-12-28 1986-07-16 Toshiba Corp 半導体記憶装置
JPS61218165A (ja) * 1985-03-25 1986-09-27 Hitachi Ltd 半導体記憶装置及び製造方法
JPH0821682B2 (ja) * 1987-04-24 1996-03-04 株式会社日立製作所 半導体装置の製造方法
JP2810042B2 (ja) * 1987-09-16 1998-10-15 株式会社日立製作所 半導体集積回路装置
JPH01231364A (ja) * 1988-03-11 1989-09-14 Hitachi Ltd 半導体集積回路装置
JPH0821687B2 (ja) * 1989-05-31 1996-03-04 富士通株式会社 半導体装置及びその製造方法
JP2673385B2 (ja) * 1989-10-26 1997-11-05 三菱電機株式会社 半導体装置
DE4034169C2 (de) * 1989-10-26 1994-05-19 Mitsubishi Electric Corp DRAM mit einem Speicherzellenfeld und Herstellungsverfahren dafür

Also Published As

Publication number Publication date
FR2674373A1 (fr) 1992-09-25
ITMI911513A1 (it) 1992-12-04
GB2253937B (en) 1995-10-25
GB2253937A (en) 1992-09-23
FR2674373B1 (fr) 2001-07-06
TW199236B (it) 1993-02-01
JPH04320059A (ja) 1992-11-10
KR940000510B1 (ko) 1994-01-21
DE4117703A1 (de) 1992-09-24
GB9112136D0 (en) 1991-07-24
KR920018890A (ko) 1992-10-22
JP2564712B2 (ja) 1996-12-18
ITMI911513A0 (it) 1991-06-04
DE4117703C2 (de) 1994-12-22

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970626