GB2253937A

GB2253937A - Semiconductor memory device

Info

Publication number: GB2253937A
Application number: GB9112136A
Authority: GB
Inventors: Kyu-Pil Lee; Yong-Jik Park; Jong-Bok Kim
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1991-03-20
Filing date: 1991-06-05
Publication date: 1992-09-23
Anticipated expiration: 2011-06-05
Also published as: KR940000510B1; FR2674373A1; DE4117703C2; DE4117703A1; GB2253937B; ITMI911513A0; GB9112136D0; ITMI911513A1; KR920018890A; IT1247968B; JP2564712B2; TW199236B; JPH04320059A; FR2674373B1

Abstract

The source and drain impurity diffusion regions (100) of transistors constituting the memory cell array of a DRAM have an impurity concentration lower than that of source and drain impurity diffusion regions (100, 200) of transistors constituting a peripheral circuit for the array, Thus, the breakdown voltage characteristic of the transistors in the cell array is improved, and the data inverting phenomenon and refresh characteristic deterioration problem due to the leakage current of the transistors in the peripheral circuit are both solved. <IMAGE>

Description

2253937 1 SEMICONDUCTOR MEMORY DEVICE AND THE FABRICATION METHOD THEREFOR

The present invention relates to a semiconductor device and the fabrication method therefor, and more particularly to a semiconductor memory device and the fabrication method therefor, in which the impurity concentration of the source and drain regions of transistors within a cell array is lower than that within a peripheral circuit.

The semiconductor memory device consists of a cell array area in which DRAM (Dynamic Random Access Memory) cells arranged in a matrix, each of which consist of a transistor, a capacitor, a word line connected to a bit line, and a peripheral circuit area for storing and transmitting data and which drives the cell array.

In semiconductor memory devices, miniaturization of unit cells to increase memory, high speed switching to transmit and store the data more quickly, and the accurate reading and writing of data in the cell array are all being widely studied.

FIG.1 of the accompanying drawings shows a sectional view of a cell array and peripheral circuit manufactured by the conventional method and is drawn to show the border between the cell array area and the peripheral circuit area constituting semiconductor memory device, thereby checking the variation in the reliability of the memory device according to characteristic variation in transistors constituting the two regions.

2 1 2 In this drawing, a DRAM cell array area consists of a transistor commonly having a drain region within an active region defined by a field oxide film 12 and having a source region and a gate electrode, and a capacitor in contact with the source region of the transistor and having a storage electrode, a dielectric film and a plate electrode. Transistors constituting the peripheral circuit are disposed in the periphery of the cell array. Generally, the impurity diffusion region of a transistor is formed by forming a gate electrode on the substrate and then doping an impurity using the gate electrode as a mask.

When the transistor becomes smaller to manufacture an effective highly integrated memory device, the power supplied is constant regardless of size reduction, thereby increasing the electric field strength inside the transistor. Particularly, in the pinch-off region near the drain, the electric field becomes much stronger, so that hot carriers are generated by the strong electric field in the region. The hot carrier is accelerated by the electric field to be injected into the gate oxide film. Otherwise, the hot carrier obtains an energy which overcome the band gap of the substrate silicon, so that new electron/hole pairs are generated according to the impact ionization; part of the newly generated electrons being injected into the gate oxide film according to the strength of the electrical f ield of the drain and part flow into the substrate to be substrate current.

If a hot carrier is injected into the gate oxide film, a new interface state is generated between the substrate and the 0 3 oxide film to change the threshold voltage or deteriorate mutual conductance. If part of the holes f low within the substrate, the substrate voltage increases and causes parasitic bipolar breakdown, thereby deteriorating the withstand voltage of the drain region, which hinders the memory characteristic.

To decrease the hot-carrier ef f ect due to a strong electric field as described above, a transistor is manufactured to have a double impurity diffusion region by thinly doping an impurity of low concentration in the substrate using the gate electrode as a mask, then forming a spacer on the side wall of the gate electrode, and again doping an impurity of high concentration using the spacer as a mask. In this structure called an LDD (Lightly Doped Drain) structure, an impurity dif fusion region of low concentration is formed near the gate electrode and in the drain region, thereby deteriorating the hotcarrier effect by weakening the electrical field therein. Generally, in the LDD structure, first of all, a first impurity diffusion region 100 is thinly formed by doping phosphorus using the gate electrode as a mask, and successively, a second impurity diffusion region 200 of a high concentration is thickly formed by disposing a spacer 18a on the side wall of the gate electrode 14 and then doping arsenic using the spacer as a mask.

The cell array area and the peripheral circuit area of the conventional semiconductor device using the LDD structure can improve the current driving capability by the above-mentioned effects, but an impurity diffusion process carried out in two 0 4 steps causes leakage current in the memory cells of the cell array area, thereby generating a data inverting phenomenon and deteriorating the refresh characteristic of the memory cell. This is because there are minute defects in the semiconductor substrate itself due to the process for coating and etching an oxide film on a substrate on which a gate electrode has been formed, to form the second impurity diffusion region or the process for doping an impurity of high concentration. The defects become a factor of the substrate leakage current, thereby causing the inverting of the data stored in the capacitor.

It is an object of the present invention to provide a semiconductor memory device in which an impurity diffusion concentration of a transistor within a cell array is lower than the diffusion concentration within a peripheral circuit to make a highly reliable memory device which improves the conditions of the above-described conventional semiconductor memory device.

It is another' object of the present invention to provide a fabrication method suitable for manufacturing the semiconductor memory device.

According to one aspect of the present invention, a semiconductor memory device having a cell array and a peripheral circuit is characterized in that the source and drain impurity diffusion regions of transistors constituting the cell array have an impurity concentration lower than that of the source and drain impurity diffusion regions of transistors constituting the 0 peripheral circuit.

According to another aspect of the present invention, in the semiconductor memory device having a cell array and a peripheral circuit, the transistors constituting the cell array and the peripheral circuit are manufactured by the steps of:

forming a field oxide film on a first conductive type semiconductor substrate; laminating and etching a gate oxide film and a first conductive layer on the whole surface of the semiconductor substrate to form a gate electrode; doping a second conductive type impurity on the whole surface of the semiconductor substrate, on which a gate electrode has been formed, to form a first impurity diffusion region; forming a spacer material on the whole surface of the substrate on which the first impurity diffusion region has already been formed; coating a photoresist on the whole surface and removing the photoresist of the peripheral circuit area by a photolithography process; anisotropically etching the spacer forming material to form a spacer on the side wall of the gate electrode of the 2 6 transistor arranged in the peripheral circuit area, and removing the remaining photoresist; and doping a second conductive type impurity using the spacer as a mask to form a second impurity diffusion region.

Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings,.in which:

FIG.1 is a sectional view of a cell array and a peripheral circuit manufactured by a conventional method; FIG.2 is a sectional view of an embodiment of a cell array and a peripheral circuit according to the present invention; FIGs. 3A to 3D are sectional views showing a sequential fabrication process of a cell array and a peripheral circuit according to an embodiment of the present invention; FIG.4 is a sectional view of another embodiment of a cell array and a peripheral circuit according to the present invention; and FIG.5 is a sectional view of a further embodiment of a cell array and a peripheral circuit according to the present invention.

W 7 FIG. 2 is a sectional view showing a semiconductor memory device according to an embodiment of the present invention Disposed in a cell array area is a DRAM cell which has two transistors which commonly have a drain region in an active region def ined by a f ield oxide f ilm 12 and have respective source regions and gate electrodes, and two capacitors each of which is in contact with the source region of the transistor and consists of a storage electrode, a dielectFic film and a plate electrode. In? periphery of the cell array area, transistors constituting a peripheral circuit are disposed. Here, source and drain impurity diffusion regions of transistors in the cell array area have an impurity concentration lower than that of the source and drain impurity diffusion regions of transistors in the peripheral circuit area.

FIGs. 3A to 3D are sectional views showing an embodiment of the sequential fabrication process of a semiconductor memory device according to the present invention.

First of all, FIG.3A shows a process for forming gate electrodes 14 and first impurity diffusion regions 100 on a semiconductor substrate 10. A field oxide film 12 is formed on the P-type semiconductor substrate 10 to separate the semiconductor substrate into active and an inactive regions. Then, a thin gate oxide film 13 and a polycrystalline silicon layer for forming the gate electrode are laminated on the whole surface. Successively, a photoresist is coated over the whole

0 8 surface of the polycrystalline silicon layer, and a mask pattern 16 for forning an electrode is made via an exposing and etching process. The gate electrodes 14 are completed by anisotropically etching the polycrystalline silicon layer and the gate oxide film using the mask pattern 16 as a mask. Successively, an N-type impurity such as phosphorus is diffused on the whole surface of the substrate using the gate electrode as a mask, thereby forming the self-aligned first impurity diffusion region on source and drain regions of each transistor. In this case, the impurity concentration of the first impurity diffusion region is a suitably low concentration, for instance, below 1018/c3n3.

FIG. 3B shows a process for forming spacers on the side walls of the gate electrodes. A spacer material 18, either a conductive material or an insulating material, is formed to a thickness of approximately 1700 A on the semiconductor substrate on which the first impurity diffusion region 100 has been selfaligned, and a photoresist is coated over the whole surface of the material. Successively, the photoresist coated over the peripheral circuit area only is removed by a photolithography process to form a photoresist pattern 20, so that the spacer material 18 formed on the peripheral circuit area is exposed. The exposed spacer material is anisotropically etched to leave a residue on the side walls of the gate electrodes 14, so that spacers 18a are formed.

FIG.3C shows a process for forming a second impurity diffusion region 200 on the peripheral circuit area. Before or p 9 after the photoresist pattern 20 is removed, an N-type impurity such as Arsenic is doped with a high concentration, above 1020/CM3 to diffuse the impurity of a high concentration on the first impurity diffusion region formed on the peripheral circuit area, thereby forming the second impurity diffusion region 200. The impurity is self-aligned by the spacers 18a formed on the side walls of the gate electrodes.

Accordingly, in the peripheral circuit area, the first impurity diffusion region of a low concentration using the gate electrode as a mask, and the second impurity diffusion region using the spacer 18a as a mask, are f ormed on an impurity diffusion region, i.e., the source and drain regions. By contrast, in a cell array area, only the first impurity diffusion region of low concentration is formed using the gate electrode as mask, so that the anisotropic etching process f or f orming spacer and the high concentration impurity doping process forming the second impurity diffusion region are both omitted. Since damage to the impurity diffusion region of the cell array from the two additional processes, i.e., the etching process and the doping process, is prevented, lattice defects of the impurity diffusion region, i.e., source and drain regions, caused during the two processes, are reduced. Generally, the generation of lattice defects in the impurity diffusion region generates leakage current. In a DRAM, if leakage current is generated in the source region of a transistor due to lattice defects, the data stored in the capacitor in contact with the source region may be inverted. Also, the device's refresh characteristic is deteriorated.

FIG. 3D shows a process for completing the cell array area and the peripheral circuit area. After the whole substrate is insulated by forming an interlayer insulting film on the whole surface of the substrate in which the second impurity diffusion region 200 has been formed, a unit process is carried out to arrange the DRAM cells of the cell array area in the form of a matrix.

in more detail, a contact hole is punched on the source region of the transistor formed on the cell array area to form capacitors C, and C., each of which comprises a storage electrode 30, a dielectric film 32, and a plate electrode, and an insulating film is then coated over the whole surface of the substrate on which the capacitors have been formed. Successively, the insulating film formed on the drain region of the transistor is removed to punch a contact hole for forming a bit line 40, and a conductive material is deposited to form a bit line 40, and, in essence, completes the cell array area in which DRAM cells are arranged in the form of a matrix. The peripheral circuit area is completed by removing the interlayer insulating film formed on the impurity diffusion region of the transistor, depositing the conductive material and patterning the conductive material to form an electrode 50.

Thus, in the peripheral circuit area, since the first impurity diffusion region of a low concentration and the second .I 1 11 impurity diffusion region of a high concentration form a single impurity diffusion region, the resistance between source and drain which was higher due to a hot carrier ef f ect, is now reduced, thereby improving the current driving capability of the transistor. On the other hand, in the cell array area, since only the f irst impurity diffusion region of a low concentration is formed, leakage current is prevented, thereby solving the conventional data inverting problem and ref resh characteristic deterioration problem, to form, a highly reliable semiconductor memory device.

FIG. 4 shows a sectional view of a semiconductor memory device manufactured according to another embodiment of the present invention. In the impurity diffusion region of the peripheral circuit area having first and second impurity diffusion regions, the second impurity diffusion region is deeper than the first impurity diffusion region, so that a part of the second impurity diffusion region is included in the first impurity diffusion region. In the above embodiment illustrated in FIGs.3A through 3D, the second impurity diffusion region is completely enclosed by the first impurity diffusion region.

FIG. 5 shows a sectional view of a semiconductor memory device manufactured according to a further embodiment of the present invention. In the source and drain impurity diffusion regions of the cell array area, only the first impurity diffusion region of a low concentration is formed, and then contact holes are formed for connecting the storage electrode and the bit line 0 12 with the first impurity diffusion region 100 and the third and fourth impurity diffusion regions 300 and 400 are formed in the first impurity diffusion region 100 through the contact holes so as to be self-aligned with the contact holes. In the source and drain impurity diffusion regions of the peripheral circuit area, the second impurity diffusion regions of high concentration is formed in addition to the first impurity diffusion regions of low concentration. As a result, the semiconductor memory device of this embodiment improves characteristics of the contacts between the impurity diffusion regions and the storage electrode and the; bit line.

The present invention is not limited to the embodiments described above, and modifications can be made by those skilled in the art without departing from the scope of the technical concept.

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Claims

1. A semiconductor memory device having a cell array and a peripheral circuit, wherein source and drain impurity diffusion regions of transistors constituting said cell array have an impurity concentration lower than that of source and drain impurity diffusion regions of transistors constituting said peripheral circuit.

2.' A semiconductor memory device as claimed in claim 1, wherein an impurity diffusion region of a transistor constituting said cell array is formed of a single layer.

3. A semiconductor memory device as claimed in claim 1, wherein an impurity diffusion region of a transistor constituting said cell array is multilayered.

4. A semiconductor memory device as claimed in claim 3, wherein said nultilayered region consists of a thin impurity diffusion region which is self-aligned to a gate electrode and a deep impurity diffusion region which is self-aligned to a contact hole.

5. A semiconductor memory device as claimed in any of claims 1 to 4, wherein an impurity diffusion region of a transistor constituting said peripheral circuit is multilayered.

6. A semiconductor memory device as claimed in claim 5, wherein 0 14 said multilayered region of the transistor constituting the peripheral circuit consists of a first impurity diffusion region of a lower concentration which is self-aligned to a gate electrode and a second impurity diffusion region of a high concentration which is self-aligned to a spacer formed on the side walls of the gate electrode.

7. A semiconductor memory device as claimed in claim 6, wherein said first impurity diffusion region completely encloses said second impurity diffusion region.

8. A semiconductor memory device as claimed in claim 6 wherein said first impurity diffusion region partly includes said second impurity diffusion region.

9. A method for manufacturing a semiconductor memory device having a cell array and a peripheral circuit, comprising the steps of:

forming a field oxide film on a first conductive type semiconductor substrate; laminating and etching a gate oxide film and a first conductive layer on the whole surface of said semiconductor substrate, thereby forming a gate electrode; doping a second conductive type impurity on the whole surface of the semiconductor substrate on which said gate 1, 1 0 electrode has been f ormed, thereby f orming a f irst impurity diffusion region; f orming a spacer material, on the whole surf ace on which said first impurity diffusion region has been formed; coating a photoresist on the whole surface and removing the photoresist of the peripheral circuit area by a photolithography process; k 1 removing said spacer forming material by an isotropic etching to form a spacer on the side walls of a gate electrode of a transistor arranged in said peripheral circuit area and then removing the remaining photoresist; and doping a second conductive type impurity using said spacer as a mask, thereby forming a second impurity diffusion region.

10. A method for manufacturing a semiconductor memory device as claimed in claim 9, wherein a f irst conductive type impurity is a P-type impurity and a second conductive type impurity is an Ntype impurity.

11. A semiconductor memory device as claimed in claim 9 or 10, wherein said second impurity diffusion region has an impurity concentration higher than that of said first impurity diffusion region.

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12. A method for manufacturing a semiconductor memory device as claimed in claim 9, 10 or 11, wherein an impurity concentration of said first impurity diffusion region is 1017 to 1018/CM3 and an impurity concentration of said second impurity diffusion region is 1020 to 1021/Cm3.

13. A method for manufacturing a semiconductor memory device as claimed in claim 9, 10, 11 or 12. wherein said f irst impurity dif fusion region is f ormed by injecting 1. 6E12 ions/cm2 at 8 0 KeV and said second impurity diffusion region is formed by injecting 5. 0E15 ions/CM2 at 60 KeV.

14. A method for manufacturing a semiconductor memory device as claimed in claim 9, 10, 11.. 12 or 13, wherein said second impurity diffusion region is formed by diffusing As ions, and said first impurity diffusion region is formed by diffusion P ions.

15. A method for manufacturing a semiconductor memory device as claimed in any of claims 9 to 14, wherein said spacer material is an oxide film.

16. A method for nanuf acturing a semiconductor memory device as claimed in any of claims 9 to 15, wherein the thickness of said spacer material is approximately 1700 A.

17. A method for manufacturing a semiconductor memory device as claimed in any of claims 9 to 16, wherein said second impurity 0 17 diffusion region is thinner than said first impurity diffusion region.

18. A method for manufacturing a semiconductor memory device as claimed in any of claims 9 to 16, wherein said second impurity diffusion region is thicker than said first impurity diffusion region.

19. A method for manufacturing a semiconductor memory d.vice in which the impurity concentration of the impurity diffusion region in a cell array area is lower than that of a peripheral circuit area, wherein an impurity diffusion region of a transistor constituting said cell array is completed by punching a contact hole f or storage electrode contact on a semiconductor substrate, where a first impurity diffusion region has been formed by doping an impurity using a gate electrode of said transistor as a mask, forming a third impurity diffusion region, forming a capacitor by a following process, punching a contact hole for bit line contact, and forming a fourth impurity diffusion region.

20. A method for manufacturing a semiconductor memory device as claimed in claim 19, wherein the impurity doped in said third and fourth impurity diffusion regions are the same type.

21. A method for manufacturing a semiconductor memory device as claimed in claim 19 or 20, wherein the depths of said third and fourth impurity diffusion regions are deeper than that of said first impurity diffusion region.

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22. A semiconductor memory device in which an impurity concentration of the impurity diffusion region is higher in a peripheral circuit area than in a cell array area, wherein an impurity diffusion region of a transistor constituting said cell array is completed by punching a contact hole for bit line contact on a semiconductor substrate, on which a first impurity diffusion region has been formed, by doping an impurity using a gate electrode of said transistor as mask, forming a fourth impurity diffusion region, completing a bit line by a following process, punching a contact hole for storage electrode contact, and forming a third impurity diffusion region.

23. A semiconductor memory device substantially as herein described with reference to Figure 2 with or without reference to any of Figures 3A to 3D, 4 and 5 of the accompanying drawings.

24. A method for manufacturing a semiconductor memory device substantially as herein described with reference to Figures 2 to 3D with or without reference to either of Figures 4 and 5 of the accompanying drawings.