199236 A6 B 6 經濟部中央標準局員工消費合作社印製 五、發明説明（1 ) (發明之背景〉 本發明是有關於半導體元件及其製造方法，特別是有 關半導體記億元件及其製造方法，在其中一値記億細胞陣 列中的電晶體的源極和汲極區域，其不純物的濃度比在周 邊電路為低。 半導體記億元件包括一個將動態隨機存取記億體 （ DRAM)赵转成矩陣的記億細胞陣列（cell array),每一個 動態隨機存取記億體包括一値電晶體、一個電容器，連接 至一條位元線的字元線及一値為了儲存和傳送資料及驅動 記億細胞陣列的周邊電路區域。 在半導體記億元件之記億細胞陣列中單位細胞的小型 化以增加記億容量，在資料的儲存和傳送間更快速的高速 切換，及精確的資料謓寫均在做廣泛的研究。 第1圖表示使用傳統方法製造記憶細胞陣列的剖面視 圖及組成半導體記憶元件的記億細胞陣列和周邊«路的分 界線，因此根據組成兩區域的電晶體的特性變化來檢核記 億元件變化的可靠性。 在圖中，一個DRAM記億細胞陣列區域包括一値電晶體 ，具有一値由一靥氣化薄膜12^定義的作動區域内的汲極 區域和一個源極區域，一個蘭極及一値與源極區域接觸的 電容器，一靥雙霣子薄膜和一値平板電極，構成周邊電路 的電晶體是排列在記億細胞陣列的周圍，一般來說，電晶 體不純物的擴散區域是藉由在基質 （SUBSTRATE)上所开多 成的閘極，然後使用此閘極當作遮蔽，遂入不純物所形成 -3- (請先閲讀背面之注意事項再填窝本頁) -裝. .訂. •線. 甲 4 ⑵ΠΧ297公釐）80. 5. 20,000張（H) Αβ Β 6 199236 五、發明説明（2) 的。 當霄晶體為了製造一個有效的高積體記億元件而變得 更小時，所需的電力不論尺寸的縮減均保持一定，因此會 增加«晶體内部的電場強度，特別是在靠近汲極的箍斷（ PINCH-OFF)區域，罨場會變得強很多，因此在此區域内 的強力電場會産生熱載子（HOT CARRIER)。熱載子會被 霣場加速而射入閘極氣化薄膜，要不然，熱載子會獲得克 服矽基質帶隙（BAND GAP)的能量，因此會根據衝搫離子 化的程度而産生新的電子/¾洞對；一部份新産生的霜子 會根據汲極霄場的強度而被射入閘極氣化薄膜且一部份流 進基質内變成基質的電流。 如果一個熱載子被射入閘極氣化薄膜，在基質和氣化 薄膜間的新界面狀態就會産生而改變菜壓臨界值（threshold) 或降低相互 轚導性。如果部份電洞流進基質，基質 的電壓就會增力Π並造成寄生（PARASITIC)雙極崩潰，因 此使汲極區域的耐電壓能力降低而阻礙記億的恃性。 為了減少前述由於強霄場所造成的熱載子效應，電晶 體製造成具有兩個在基質中使用閑極當作遮蔽，滲入低濃 度不純物的不純物擴散區域，因此在閘極的邊猫形成一値 間隔物（SPACER)且再一次使用此間隔物當作遮蔽滲入高 灌度的不純物，此種結構稱為微遽入汲極LDD (LIGHTLY DOPED DRAIN),在汲極區域和靠近閜極處形成一低濃度 的不純物擴散區域，因此經由減弱電場強度以降低熱載子 效應，一般來說，在LDD^S構最初第一個不純物擴散區域 *4- 甲 4(21 丨)Χ297公釐）80. 5. 20,000張（H) .........................................W ·:··装...........................·玎......r...............~ ♦ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 99236 A6 B 6 經濟部中央標準局員工消費合作社印製 五、發明説明（3 ) 100使用閜極當遮蔽藉由滲入磷形成薄的一曆，且連缠地 ，第二個高濃度的不純物擴散區域200¾藉由沉積一個間 隔物18a在閙極14邊牖所形成厚的一層，然後使用間隔物 作為滲入砷時所用之遮蔽髏。 傳統半導體元件的記慷細胞陣列區域和周邊電路區域 使用LDD結構能夠經由上述的效應增進電流驅動能力，但 是不純物擴散過程是以兩步驟實施，會造成記億細胞陣列 區域的記德體的漏失霣流，因此産生賫料顛倒現象並降低 記憶體更新的恃性，這是因為在半導髏基質本身中有少數 的缺陷，此缺陷是由於在形成蘭極的基質上做覆靥和腐蝕 氣化膜以形成第二値不純物擴散區域的過程或是旗入高濃 度的不純物過程所造成。此缺陷變成基質漏失®流的因素 ，因此造成儲存在電容器的資料顛倒。 〈發明之總論〉 本發明的目的是在提供一種半導體記億元件.其在記 億細胞陣列的電晶體的不純物濃度比在周邊電路内的不純 物濃度為低，使記億體元件有較高的可靠度以改進上述傳 統半導體記億元件的狀態〇 本發明的另一目的是提供一種適合於製造半導體記億 元件的製造方法。 為達成本發明的目的，半導體記億元件在記憶細胞陣 列和周邊電路具有某些特徽，即組成記億細胞陣列的電晶 體的源極和汲極區域的不純物擴散區域的不純物濃度比組 成周邊電路的電晶體的源極和汲極區域的不純物擴散區域 -5- (請先閱讀背面之注意事項再请寫本頁) .装· .訂· _線· 甲 4 (2IDX297公贷）80. 5_ 20,000張（H) A 6 B 6 199236 五、發明説明（斗） 的不純物潘度低〇 為達成本發明另一目的，在半導體記億元件中有記億 細胞陣列和周邊栗路，組成記億細胞陣列和周邊®路的電 晶體的製造步驟如下： 在第一導菜型半導體基質中，形成一靥氣化膜； 在半導體基質的整値表面上將閘門氣化薄膜和第一種 導電型薄曆加以分靥及腐触以形成閙極； 在已形成閘極的半導體基質的整個表面上雄入第二種 導型不純物，以形成第一個不純物擴散區域； 在己形成第一値不純物擴散區域的半導體基質的整個 表面上形成一値間隔物材料； 在整個表面覆上一層光阻材料並使用照相製版的程序 移去周邊霄路的光阻材料； 在間隔物成形材料上異向性的腐独以便在排列於周邊 電路區域的電晶體的蘭極的邊牆上形成間隔物，並且移去 剩餘的光阻材料；以及 利用間隔物做遮蔽髏，滲入第二種導電型不純物以形 成第二個不純物擴散區域。 〈圖示之簡簞說明〉 本發明的上述目的和其他優點藉由參閲附圖所作較佳 實例之説明將會更為明顯： 第1圖是一値由傳統方法製造的記億細胞陣列和周邊 電路的剖面圖； 第2圖是一個由本發明之具體實例製造的記億細胞陣 -6- 甲 4 (210X297公贷）80. 5. 20,000張（H) ..........................................> :.i..........................计.......................·《.線. (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 經濟部中央標準局貝Η消费合作社印製 199236 A6 x__B_6_ 五、發明説明（5) 列和周邊IS路的剖面圖； 第3A至3D圖是由本發明具體實例製造的記億細胞陣列 和周邊電路的製造順序的剖面圖； 第4圖是由本發明另一具體賁例製造的記億細胞陣列 和周邊電路的剖面圖； 第5圖仍是由本發明另一具醱實例製造的記億細胞陣 列和周邊菜路的剖面圖； 〈發明的詳細描述〉 第2圖是根據本發明的半導體元件的剖面圖。 排列在記億細胞陣列區域是DRAM，DRAM有兩値電晶體 ，通常在作動區域有一個由氣化膜12所定義的汲極區域和 個別的源極區域及蘭極，和兩個15容器，每一値電容器和 電晶體的源極區域相接觸並包含一個儲存電極，一個雙電 子膜和一個平板電極，在記億細胞陣列區域的周圍排列箸 組成周邊電路的電晶體，在記憶細胞陣列區域的電晶體的 源極和汲極的不純物擴散區域的不純物濃度比在周邊電路 區域的電晶體的源極和汲極的不純物擴散區域的不純物濃 度來的低。 第3A圖到3D圖是根據本發明製造的半導體元件的製造 順序的剖面圖。 首先，第3A圖顯示在半導體基質10上形成閙極14和第 —個不純物擴散區域100的程序。 為了將半導體基質區分成作動區域和不作動區域，氣 化膜12是在P型半導體的莲質10上成形的。然後一曆問門 甲 4 (210X297公蝥）SO. 5. 20,000張（Η) ..........................................Γ …r..........................".......·...............C •線· (請先閲讀背面之注意事項再填寫本頁) A 6 B 6 199236 五、發明説明（6) 氣化薄膜13和為形成閘極的矽多結晶層被分層的覆蓋在整 個表面。接箸，將光阻材料塗在砂多結晶靥的整値表面上 ，且遮蔽圖形1(3為形成一値電極藉由暴露和腐触程序來達 成。蘭極14是經由使用遮蔽圖形16當作遮蔽採異向性的腐 蝕矽多結晶靥和閑門氣化薄膜。接箸，一種N型的不純物 如磷，使用閑極當作遮蔽擴散至基質的整値表面，因此在 每一個電晶體的源極及汲極區域形成一種自動對齊的第一 値不純物擴散區域。在這種狀況下，在第一個不純物擴散 區域適當的低濃度是，例如低於lQ^/crn3。 第圖表示在閙極的邊牆上形成間隔物的程序，一種 間隔物材料13,不論是導電材料或絕緣材料，在第一個不 純物擴散區域100已自動對齊且在整個表面塗上光阻材料 的半導體基質上形成厚度約1700ί^的一靥。接著，僅在周 邊電路區域的光阻材料經由照相製版過程移去以形成光阻 型式20,如此在周邊電路成形的間隔物材料13會暴露在外 。暴露的間隔物材料是採異向性的腐触以便在閘極14的側 牆上産生殘留而形成間隔物18a。 第3C圖表示在周邊電路形成第二値不純物擴散區域 200的程序，在光阻型式20被移走之前或後，德入濃度高 於的高濃度N型不純物如碑，擴散高濃度的不純 物於在周邊電路上成形的第一個不純物擴散區域，因此形 成第二値不純物擴散區域200,不純物是藉由在閘極邊牆 上成形的間隔物18a而自動對齊的。 於是，在周邊電路區域，低濃度的第一値不純物擴散 -8- 甲 4(210X297公贷）80. 5. 20,000張（H〉 ..........................................……装：….....................tr'.......................-線. (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印裳 199236 A 6 B 6 經濟部中央標準局員工消費合作社印製 、五、發明説明（7) 區使用閘極做遮蔽及第二個不純物擴散區域使用間隔物18 a作為遮蔽體，均在不純物擴散區域成形，即源極和汲極 區域。相對的，在記憶細胞陣列中僅有使用閙極作遮蔽體 的低濃度的第一個不純物擴散區域成形，因此形成間隔物 的異向性腐触程序和使用高濃度的不純物形成第二値不純 物擴散區域的縿入程序均予以省略。因為造成對記億細胞 陣列不純物擴散區域的損傷的兩個程序，腐蝕和滲入程序 被阻止，由此兩個程序所造成的不純物區域的晶格缺陷， 即源極和汲極區域會減少。一般來説，在不純物擴散區域 所産生的晶格缺陷會産生漏失電'<庶，i^DRAM，如果由於晶 格缺陷在電晶體源極區域所産生漏失電流的話，則儲存在 與源極區域接觸的電容器的資料可能會顛倒。同樣的，元 件的再更新特性會降低。199236 A6 B 6 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (1) (Background of the invention) The present invention relates to semiconductor components and their manufacturing methods, in particular to semiconductor memory devices and their manufacturing methods, In the source and drain regions of transistors in one of the billion-element cell arrays, the concentration of impurities is lower than in the peripheral circuits. Semiconductor billion-element components include a dynamic random access memory (DRAM) Zhao Zhuan A matrix of cell arrays (cell array), each dynamic random access cell includes a transistor, a capacitor, a word line connected to a bit line and a line for storing and transmitting data and driving The peripheral circuit area of the billion-cell array. The miniaturization of unit cells in the billion-cell array of semiconductor billion-element components to increase the capacity of billion-element, faster and high-speed switching between data storage and transmission, and accurate data writing Extensive research is being done. Figure 1 shows the cross-sectional view of the memory cell array manufactured using traditional methods and the billions of dollars that make up the semiconductor memory device. The dividing line between the cell array and the surrounding path, so the reliability of the change of the billion-element component is checked according to the change of the characteristics of the transistors that make up the two regions. In the figure, a DRAM billion-element cell array area includes a transistor, with A drain region and a source region within the actuation region defined by a vaporized film 12 ^, a blue electrode and a capacitor in contact with the source region, a dual thin film and a flat plate electrode , The transistors that make up the peripheral circuit are arranged around the array of billions of cells. Generally speaking, the diffusion area of the impurity of the transistor is obtained by opening more gates on the substrate (SUBSTRATE), and then using this gate as a Covered, and then formed by impure materials -3- (please read the precautions on the back before filling the nest page)-installed .. ordered. • line. A 4 ⑵ΠΧ297 mm) 80. 5. 20,000 sheets (H) Αβ Β 6 199236 V. Description of the invention (2). When the small crystal becomes smaller in order to manufacture an effective high-integral billion-element component, the required power remains constant regardless of the size reduction, so it will increase the electric field strength inside the crystal, especially in the hoop near the drain In the PINCH-OFF area, the field will become much stronger, so the strong electric field in this area will generate hot carriers (HOT CARRIER). The hot carrier will be accelerated by the engraved field and enter the gate vaporization film. Otherwise, the hot carrier will gain energy to overcome the band gap of the silicon matrix (BAND GAP), so it will generate a new one according to the degree of impact ionization. Electron / ¾ hole pair; part of the newly generated frost will be injected into the gate vaporization film according to the strength of the dip field and part of it will flow into the matrix and become the matrix current. If a hot carrier is injected into the gate gasification film, a new interface state between the substrate and the gasification film will be generated to change the vegetable pressure threshold or reduce the mutual conduction. If part of the holes flow into the substrate, the voltage of the substrate will increase Π and cause parasitic (PARASITIC) bipolar collapse, thus reducing the withstand voltage capability of the drain region and hindering the reliability of the billion. In order to reduce the aforementioned hot carrier effect caused by the strong field, the transistor is made to have two impurity diffusion regions that use idle poles in the matrix as a shield and penetrate into low concentration impurities, so a cat is formed on the edge of the gate Spacer (SPACER) and use this spacer again as a shield to penetrate high-impurity impurities, this structure is called micro-draining LDD (LIGHTLY DOPED DRAIN), forming a region in the drain and near the pole Low concentration of impurity diffusion region, so by reducing the electric field strength to reduce the hot carrier effect, generally speaking, the first impurity diffusion region in the first LDD ^ S configuration * 4- A 4 (21 丨) 297 mm) 80. 5 . 20,000 sheets (H) ................................... W ·: ·· Pretend .................................................................. .... ~ ♦ (Please read the precautions on the back before filling out this page) Printed by the Ministry of Economy Central Standards Bureau Employee Consumer Cooperative 99236 A6 B 6 Printed by the Ministry of Economics Central Standards Bureau Employee Consumer Cooperative V. Invention Description (3) 100 is used as a mask to form a thin calendar by infiltrating phosphorus, and even , The second impurity diffusion region of high concentration by depositing a 200¾ spacers 18a between the electrode 14 side to enlighten Nao formed thick layer, and then using spacers as used in the shield when arsenic penetrate the skull. The use of the LDD structure in the memory cell array area and the peripheral circuit area of the traditional semiconductor device can improve the current driving ability through the above-mentioned effects, but the impure diffusion process is implemented in two steps, which will cause the leakage of the memory body of the billion cell array area. Flow, thus causing the phenomenon of reversal of reeds and reducing the renewal of memory. This is because there are a few defects in the semi-conductive skull matrix itself. This defect is due to the coating and corrosion gasification on the matrix forming the blue pole The film is caused by the process of forming the second impurity diffusion region or the process of flagging high concentration of impurities. This defect becomes a factor in matrix leakage® flow, thus causing the data stored in the capacitor to be reversed. <Overview of the Invention> The object of the present invention is to provide a semiconductor memory device. The impurity concentration of the transistor in the memory cell array is lower than the impurity concentration in the peripheral circuit, so that the memory device has a higher concentration Reliability to improve the state of the conventional semiconductor billion-element component described above. Another object of the present invention is to provide a manufacturing method suitable for manufacturing semiconductor billion-element components. In order to achieve the purpose of the invention, semiconductor memory devices have certain characteristics in the memory cell array and peripheral circuits, that is, the impurity concentration ratio of the impurity diffusion region of the source and drain regions of the transistors constituting the memory cell array constitutes the periphery Impurity diffusion area of the source and drain areas of the transistor of the circuit-5- (please read the precautions on the back before writing this page). Install · Order · _Line · A 4 (2IDX297 public loan) 80. 5_ 20,000 sheets (H) A 6 B 6 199236 V. Description of the invention (Bucket) Impurity Pandu is low. In order to achieve another purpose of cost invention, there are billions of cell arrays and peripheral chestnuts in the semiconductor billions of components. The manufacturing steps of the 100 million cell array and the surrounding transistors are as follows: in the first semiconductor substrate, a vaporized film is formed; on the entire surface of the semiconductor substrate, the gated vaporized film and the first conductive The thin calendar is divided into tungsten and corroded to form a dynode; a second type of impurity is inserted on the entire surface of the semiconductor substrate where the gate has been formed, to form the first impurity diffusion region; A spacer material is formed on the entire surface of the semiconductor matrix in the impurity diffusion region; a photoresist material is coated on the entire surface and the photoresist material on the surrounding road is removed using a photo-engraving procedure; the spacer forming material is different Directional corrosion to form a spacer on the side wall of the blue pole of the transistor arranged in the peripheral circuit area, and remove the remaining photoresist material; and use the spacer as a shield to penetrate the second conductivity type impurities In order to form the second impurity diffusion region. <Brief description of the illustration> The above-mentioned objects and other advantages of the present invention will be more apparent by referring to the accompanying drawings and description of the preferred examples: FIG. 1 is an exemplary memory cell array manufactured by a conventional method and A cross-sectional view of the peripheral circuit; Figure 2 is a memory cell array-6-A4 (210X297 public loan) manufactured by a specific example of the present invention 80. 5. 20,000 sheets (H) ... .................................> :. i ............ ............................................ ". Line. (Please read the notes on the back first Please fill in this page again.) Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Printed by the Central Bureau of Standards of the Ministry of Economy. Printed by the Consumer Cooperative of the Central Bureau of Economic Affairs 199236 A6 x__B_6_ V. Description of the invention (5) Sectional view of the row and surrounding IS roads; 3A to 3D Figure 4 is a cross-sectional view of a manufacturing sequence of a billion-cell array and peripheral circuits manufactured by a specific example of the present invention; Figure 4 is a cross-sectional view of a billion-cell array and peripheral circuits manufactured by another specific example of the present invention; It is a cross-sectional view of the memory cell array and the surrounding vegetable road made by another example of the invention; Detailed Description of the Invention> Figure 2 is a cross-sectional view of the semiconductor device according to the invention. Arranged in the memory cell array area is DRAM. DRAM has two transistors. Usually, there is a drain area defined by the vaporization film 12 and individual source areas and blue poles in the actuation area, and two 15 containers, Each capacitor is in contact with the source region of the transistor and contains a storage electrode, a double-electron film and a flat plate electrode. The transistors forming the peripheral circuit are arranged around the memory cell array area. In the memory cell array area The impurity concentration of the impurity diffusion region of the source and the drain of the transistor is lower than the impurity concentration of the impurity diffusion region of the source and the drain of the transistor in the peripheral circuit region. Figures 3A to 3D are cross-sectional views of the manufacturing sequence of semiconductor elements manufactured according to the present invention. First, FIG. 3A shows the procedure for forming the anode 14 and the first impurity diffusion region 100 on the semiconductor substrate 10. In order to distinguish the semiconductor substrate into an active area and a non-active area, the vaporization film 12 is formed on the lotus 10 of the P-type semiconductor. Then I asked the door armor 4 (210X297 public candidate) SO. 5. 20,000 sheets (Η) .................................. ............. Γ… r .......................... " ...... ................... C • Line · (Please read the precautions on the back before filling this page) A 6 B 6 199236 V. Description of the invention (6) Vaporized film 13 And the polysilicon layer for forming the gate is layered to cover the entire surface. Then, the photoresist material is coated on the entire surface of the sand polycrystalline tantalum, and the shielding pattern 1 (3 is formed by exposing and corroding the electrode to form an electrode. The blue pole 14 is formed by using the shielding pattern 16 It is used as a shielding anisotropic etched silicon polycrystalline tantalum and Xianmen vaporized film. Then, an N-type impurity such as phosphorus is used as a shield to diffuse to the entire surface of the substrate, so in each transistor The source and drain regions of the source form an automatically aligned first impurity diffusion region. In this case, the appropriate low concentration in the first impurity diffusion region is, for example, lower than 1Q ^ / crn3. The procedure for forming a spacer on the side wall of the anode, a spacer material 13, whether it is a conductive material or an insulating material, is automatically aligned in the first impurity diffusion region 100 and is coated on the entire surface of the semiconductor substrate with a photoresist material A thickness of about 1700μ ^ is formed. Then, only the photoresist material in the peripheral circuit area is removed through the photolithography process to form the photoresist pattern 20, so that the spacer material 13 formed in the peripheral circuit is exposed The exposed spacer material is made of anisotropic corrosion to create a residue on the side wall of the gate electrode 14 to form the spacer 18a. FIG. 3C shows the procedure for forming the second impurity diffusion region 200 in the peripheral circuit, Before or after the photoresist pattern 20 is removed, a high-concentration N-type impurity with a concentration higher than a monument is diffused, and a high-concentration impurity is diffused in the first impurity diffusion region formed on the peripheral circuit, thus forming a second value Impurity diffusion area 200, the impurities are automatically aligned by the spacer 18a formed on the gate side wall. Therefore, in the peripheral circuit area, the first concentration of the low concentration of the impurity diffusion-8- A 4 (210X297 public loan) 80. 5. 20,000 sheets (H> ............................................... ....... Pretend: ........................ tr '..................... ..- line. (Please read the notes on the back before filling out this page) Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 199236 A 6 B 6 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 7) The gate is used for shielding and the second impurity diffusion area The spacer 18 a is used as the shielding body, which is formed in the impurity diffusion region, that is, the source and drain regions. On the contrary, in the memory cell array, there is only the first impurity diffusion region with a low concentration using the anode as a shield Forming, therefore, the anisotropic erosion procedure for forming the spacer and the entry procedure for forming the second impurity diffusion region using a high concentration of impurities are omitted. Two procedures that cause damage to the impurity diffusion region of the billion cell array The corrosion and penetration procedures are prevented, and the lattice defects in the impurity region caused by the two procedures, namely, the source and drain regions, are reduced. Generally speaking, the lattice defects generated in the impurity diffusion region will cause leakage and loss of electricity. If the leakage current is generated in the source region of the transistor due to the lattice defect, it will be stored in the source. The information of the capacitor in the area contact may be reversed. Similarly, the renewal characteristics of components will be reduced.
第3D圖是顯示完成記億細胞陣列區域和周邊電路區域 的程序，在整個基質被在基質整個表面上成形的第二痼不 純物擴散區域200上成形的中間曆絕絲膜絕緣後，一單位 程序乃被實行，將記億細胞陣列上的DRAM記憶細胞排成矩 陣。更詳細的説，在記億細胞陣列區域成形的電晶體的源 極區域上所打出的接觸電洞會形成電容器C1和C2,每一値 電容器是由一値儲存電極30，介電膜32和一個平板電極所 組成，且在電容器成形的基質的整個表面塗上一層絕綠膜 。接箸，為了形成一條位元線40，在電晶體汲極區域上成 形的絕緣膜被移走以便打出一痼接觸電洞，且一種導踅材 料被排列成形成位元線40且基本上就完成在記憶細胞陣歹U _ Q - 甲 4 (2 丨丨）X 297公釐）80. 5. 20,000張（Η) .........................................一.......i-.........................訂.....................:線. (請先閲讀背面之注意事項再填寫本頁) A6 B 6 五、發明説明（8 ) 上DRAM排成矩陣的動作，周邊電路區域是經由移走在不純 物擴散區域上成形的中間靥絕緣膜，排列導電材料和將導 電材料做成型式以形成電極50而完成的。 因此，在周邊電路區域，因為在第一個不純物擴散區 域的低濃度和第二個不純物擴散區域的高濃度而形成一傾 獨立的不純物擴散區域，在源極和汲極區域間的電阻，由 於熱載子效應而較高，但現在已降低了，因此可改善電晶 體的電流驅動能力。另一方面，在記億細胞陣列區域，因 為祗有低濃度的第一個不純物擴散區域成形，漏失電流被 防止，因此可解決傳統資料顚倒問題與更新特性袞減的問 題以産生一估可靠度較高的半導體記憶元件。 第4圖是由本發明另一製造半導體記億元件的具體實 例的剖面圖，在周邊電路的不純物擴散區域具有第一痼和 第二個不純物擴散區域，第二個不纯物擴散區域比第一個 不純物擴散區域深，因此一部份的第二値不純物擴散區域 被涵蓋在第一値不純物擴散區域中。在上述第3A圖至3D圔 的具體圖例中，第二阔不純物擴散區域完全被第一個不純 物擴散區域所涵蓋。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填窝本頁) -…訂· .線- 第5圖表示由本發明另一實例製造半導體記憶元件的 剖面圔。在記憶細胞陣列的源極和汲極區域的不純物擴散 區域，祗有形成低濃度的第一個不純物擴散區域，因此改 善接合面的崩潰電壓持性，在周邊電路上電晶體的不纯物 擴散區域，額外形成高濃度的第二阔不純物擴散區域，因 此消除在不纯物擴散區域上貢獻離子移植的晶格缺陷以防 -10- 甲 4 ⑵丨）X297公贷）80. 5. 20,000張（η) A6 B6 199236 五、發明説明（9 ί 止由於這些晶格缺陷所造成的if届失電流。因此，資料顚倒 現象且更新待性的袞減問題可被解決。 第5圖表示本發明又一製造半導體記億元件的具體實 例剖面圖，在記憶細胞陣列的源極及汲極區域的不純物擴 散區域，只有低濃度的第一値不純物擴散區域被形成，因 此形成了接觸電洞，使儲存電極以及位元線與第一不純物 擴散區域100相連，而第三與第四不純物擴散區域300與 400偽經由接觸電洞被形成於第一不純物擴散區域100， 如此乃與接觸電洞成為自行對齊之情形。在周邊電路區域 之源極和汲極不純物擴散區域中，高濃度第二不純物擴散 區域傜增加形成在低濃度第一不純物擴散區域中，結果， 本實施例之半導體記憶元件增進了不純物擴散區與儲存電 極和位元線之間的接觸特性。 很顳然的，本發明不受限於這些具體實例，且可在不 必離開這技術觀念的範上經由這些技巧加以改進。 ....•…：.:...........................i ::,.l·..:·.汊“...........................訂..........f ................線 {請先«I讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)甲4規格（210x297公釐}Figure 3D shows the procedure for completing the billion cell array area and the peripheral circuit area. After the entire substrate is insulated by the intermediate barrier film formed on the second impurity diffusion area 200 formed on the entire surface of the substrate, a unit program It was implemented to arrange the DRAM memory cells on the billion cell array into a matrix. In more detail, the contact holes punched in the source region of the transistor formed in the area of the memory cell array will form capacitors C1 and C2. Each capacitor is composed of a storage electrode 30, a dielectric film 32 and It is composed of a flat electrode, and a green film is coated on the entire surface of the capacitor-forming substrate. Then, in order to form a bit line 40, the insulating film formed on the drain region of the transistor is removed to make a contact hole, and a conductive material is arranged to form the bit line 40 and basically Completed in the memory cell array U _ Q-A 4 (2 丨 丨) X 297 mm) 80. 5. 20,000 sheets (Η) ......................... .................................. i -.................. ....... Order ...............: Line. (Please read the precautions on the back before filling this page) A6 B 6 5. DESCRIPTION OF THE INVENTION (8) The operation of arranging the DRAM in a matrix, the peripheral circuit area is completed by removing the middle tantalum insulating film formed on the impurity diffusion area, arranging the conductive material, and forming the conductive material into the molding type to form the electrode 50. Therefore, in the peripheral circuit area, because of the low concentration in the first impurity diffusion area and the high concentration in the second impurity diffusion area, an independent impurity diffusion area is formed. The resistance between the source and the drain area is due to The hot carrier effect is higher, but now it has been reduced, so the current driving ability of the transistor can be improved. On the other hand, in the area of the billion cell array, because the first impurity diffusion area with low concentration is formed, the leakage current is prevented, so it can solve the problem of traditional data collapse and the reduction of update characteristics to produce an estimated reliability High degree semiconductor memory device. FIG. 4 is a cross-sectional view of another specific example of manufacturing a semiconductor billion-element device according to the present invention. The impurity diffusion region of the peripheral circuit has a first impure and a second impurity diffusion region, and the second impurity diffusion region is higher than the first. The impurity diffusion regions are deep, so a part of the second impurity diffusion region is covered in the first impurity diffusion region. In the specific illustrations of Figures 3A to 3D above, the second wide impurity diffusion area is completely covered by the first impurity diffusion area. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) -... order · .line-Figure 5 shows the cross-section of a semiconductor memory device manufactured by another example of the present invention. In the impurity diffusion region of the source and drain regions of the memory cell array, there is only the first impurity diffusion region that forms a low concentration, thus improving the breakdown voltage retention of the junction surface and the impurity diffusion of the transistor on the peripheral circuit Area, an additional high-concentration second broad impurity diffusion area is formed, so that lattice defects that contribute to ion implantation on the impurity diffusion area are eliminated to prevent -10- 甲 4 ⑵ 丨) X297 public loan) 80. 5. 20,000 sheets (Η) A6 B6 199236 V. Description of the invention (9) Only the if current loss due to these lattice defects will be prevented. Therefore, the problem of data collapse and update reduction can be solved. Figure 5 shows this In another embodiment of the invention, a cross-sectional view of a specific example of manufacturing a semiconductor memory device. In the impurity diffusion regions of the source and drain regions of the memory cell array, only low-concentration first impurity diffusion regions are formed, thus forming contact holes, The storage electrode and the bit line are connected to the first impurity diffusion region 100, and the third and fourth impurity diffusion regions 300 and 400 are formed on the first Impurity diffusion region 100 is thus in a self-aligned state with the contact hole. In the source and drain impurity diffusion regions of the peripheral circuit area, the high-concentration second impurity diffusion region increases and is formed in the low-concentration first impurity diffusion region As a result, the semiconductor memory device of the present embodiment improves the contact characteristics between the impurity diffusion region and the storage electrode and the bit line. Quite temporally, the present invention is not limited to these specific examples, and it is not necessary to leave this The range of technical concepts is improved by these techniques. .... • ...:.: ........................... i :: , .l · ..: ·. 擊 "........................... Ordered ... f ................ Line {Please «I read the precautions on the back and then fill out this page) The paper standards printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs are applicable to the Chinese national standards ( CNS) A 4 specifications (210x297mm)